Datasheet_RTL8672_v04_preliminary

RTL8672

Integrated ADSL2+ Router Controller

Datasheet

Rev. 0.4

6 May, 2008

Track ID: xxxx-nnnn-nn

?2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. CONFIDENTIALITY

This document is confidential and should not be provided to a third-party without the permission of Realtek Semiconductor Corporation.

USING THIS DOCUMENT

This document is intended for the software engineer’s reference and provides detailed programming information.

Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary

0.0 2008/01/18 First release.

0.1 2008/01/23 n Correcting pin 113 as ‘OVDD’

n Block diagram added

0.2 2008/01/30 n Correcting pin 12 as ‘VSS’

0.3 2008/01/31 n Correcting polarity of ‘U1ID’

0.4 2008/05/06 n‘U1ID’ should be input only, not I/O

Table of Contents

1.GENERAL DESCRIPTION (1)

2.FEATURES (2)

3.SYSTEM APPLICATIONS (2)

4.BLOCK DIAGRAM (3)

5.PIN ASSIGNMENTS (4)

6.PIN DESCRIPTIONS (5)

7.SYSTEM OVERVIEW (9)

8.ELECTRICAL REQUIREMENTS (10)

8.1.DC C HARACTERISTICS (10)

8.1.1.Absolute Maximum Rating (10)

8.1.2.Recommended Operation Conditions (10)

8.1.3.Power Consumption (10)

8.1.4.Reference Crystal (11)

8.1.5.V REF Input (11)

8.2.AC C HARACTERISTICS (11)

8.2.1.FLASH – Parallel (11)

8.2.2.FLASH – Serial (12)

8.2.3.SDRAM (12)

8.2.3.1SDRAM Input Timing (12)

8.2.3.2SDRAM Output Timing (13)

8.2.3.3SDRAM Access Control Timing (13)

8.2.4.AFE (14)

8.2.4.1Master clock (14)

8.2.4.2Transmission Interface (15)

8.2.4.3Reception Interface (15)

8.2.5.JTAG (15)

8.2.6.Reset (16)

8.2.7.V REF Timing (17)

8.2.8.Power-on sequence (17)

9.MECHANICAL DIMENSIONS (18)

10.ORDERING INFORMATION (20)

List of Tables

T ABLE 1P IN D ESCRIPTIONS OF RTL8672(128-PIN LQFP) (5)

T ABLE 2A BSOLUTE M AXIMUM R ATING (10)

T ABLE 3R ECOMMENDED O PERATION C ONDITIONS (10)

T ABLE 4P OWER C ONSUMPTION (10)

T ABLE 5R EFERENCE C RYSTAL (11)

T ABLE 6V REF I NPUT (11)

T ABLE 7FLASH I NTERFACE T IMING (11)

T ABLE 8SDRAM I NPUT T IMING (12)

T ABLE 9SDRAM O UTPUT T IMING (13)

T ABLE 10SDRAM C ONTROL T IMING (13)

T ABLE 11AFE I NTERFACE C LOCK (14)

T ABLE 12AFE TX I NTERFACE (15)

T ABLE 13AFE RX I NTERFACE (15)

T ABLE 14JTAG I NTERFACE T IMING (15)

T ABLE 15R ESET T IMING (16)

T ABLE 16V REF T IMING (17)

T ABLE 17D IMENSION OF LQFP-128 (19)

List of Figures

F IGURE 1T YPICAL A PPLICATION D IAGRAM I (2)

F IGURE 2T YPICAL A PPLICATION D IAGRAM I (2)

F IGURE 3B LOCK D IAGRAM (3)

F IGURE 4P IN-OUT D IAGRAM (4)

F IGURE 5F LASH A CCESS T IMING (12)

F IGURE 6SDRAM I NPUT T IMING (13)

F IGURE 7SDRAM O UTPUT T IMING (13)

F IGURE 8SDRAM A CCESS C ONTROL T IMING (14)

F IGURE 9B OUNDARY-S CAN G ENERAL T IMING (16)

F IGURE 10B OUNDARY-S CAN R ESET T IMING (16)

F IGURE 11R ESET T IMING (17)

F IGURE 12D RAWING OF LQFP-128 (18)

1. General Description

The Realtek RTL8672 is an integrated SoC featuring a RISC, an ADSL2+ Discrete Multi-tone (DMT) data-pump, a hardware-based ATM Segmentation and Reassembly (SAR), a hardware based packet accelerator, a 10/100Mbps IEEE 802.3 compliant Ethernet transceiver, and two USB PHY ports supporting host and device modes. Mated with Realtek RTL8271 (ADSL2+ Analog Front End), RTL8672 provides a low cost integrated solution for ADSL2+ CPE modems, routers, or gateways.

RTL8672 encompasses high-performance DSP technologies, optimized mix-signal designs, and an efficient architecture to provide a seamless WAN to LAN router controller. The embedded RISC network processor supports the MIPS I instruction set along with DSP extensions and achieves a 400MHz clock rate in a six-stage pipeline to support layer 2, 3, and other upper layer applications.

The DMT engine supports the upstream data rate from 32kbp to above 3Mbps and the downstream data rate from 32kbps to above 24Mbps throughput, and complies with:

n ANSI T1.413 Issue 2

n ITU-T G.992.1 (G..dmt) Annexes A and B

n G.992.2 (G..lite) Annexes A and B

n G.992.3 ADSL2 (G.dmt.bis) Annexes A, B, I, J, L, and M

n G.992.4 ADSL2 (G.lite.bis)

n G.992.5 ADSL2+

n Dual-latency on the same copper

n HDLC PTM on copper

The Ethernet interface offers high-speed transmission over CAT-5 UTP cable or CAT-3 UTP (10Mbps only) cable. Ethernet functions such as Crossover Detection & Auto-Correction and polarity correction are implemented to provide robust transmission and reception capability at high speeds.

2. Features

n Two-chip ADSL2+ CPE solution: RTL8672 (ADSL2+/Network Processor SoC) +

RTL8271B (ADSL2+ Analog Front End).

n Field proven DMT data-pump complies with ANSI T1.413 Issue 2, ITU-T G992.1,

G.992.2 , G.992.3, G.992.4, G.992.5

supporting Annexes A, B, I, J, L, and M.

Supports S=1/3 coding.

n Dual-latency supported on the same copper

n HDLC-PTM on copper supported

n High performance embedded RISC with MMU, TLB and DSP instruction extension. n Embedded hardware-based ATM SAR: up to 16 distinct VCs—ATM AAL5 adaptation, F4/F5 OAM cell, HEC, CRC, IP/TCP/UDP checksum offloading, and error packet

filtering— and QoS supported for CBR,

UBR, rt-VBR, and nrt-VBR.

n Embedded hardware-based packet accelerator for better throughput

performance and IP QoS

n Embedded 10/100 Base-TX Ethernet MAC and transceiver supporting Crossover

Detection & Auto-Correction and polarity

correction, IP/TCP/UDP checksum offload supported as well.

n Two on-chip USB PHY posts: one for host mode only, and one configurable as

host/device mode.

n Support serial SPI interface for device control

n Network device management via HTTP, SNMP, and CLI (UART).

n IP layer processing, DHCP, NAT, and typical higher layer applications supported n16-bit-wide, 166MHz SDRAM support up to 256Mb

n8/16-bit-wide parallel/SPI Flash support up to 128Mb

n 3.3V signaling, 1.2V core voltage; a embedded linear regulator controller to

reduce an external LDO

n Two 32-bit timers and a watchdog timer

n Embedded “Dying-Gasp” detection circuit n EJTAG interface

n Package of 128-pin LQFP available

3. System Applications

Figure 2 Typical Application Diagram I

4. Block Diagram

5. Pin Assignments

Figure 4 Pin-out Diagram

V M MD13V C T D D 3V D D 1T X O T X O V S R X I R X I V D D 1V D D 1C K I V S V D D 1V D D 3U 0D U 0D V S V S U 1D U 1D U 1I U 1V B U V D D 3D G N G P A 5/S V C S I V D A F T X D A F T X D A F T X D A F T X D A F R X D A F R X D D 14M D 15W E #O V D D R A S #C A S #M C S 3#D G N D M C S 2#I V D D M A 0M A 1M A 2M A 3O V D D M A 4M A 5M A 6M A 7I V D D M A 8M A 9M A 10M A 11M A 12O V D D M A 13M A 14M A 15M A 16M A 17M A 18

MD12IVDD MD11MD10OVDD MD9MD8MD7MD6SDCLK MD5IVDD MD4DGND MD3OVDD ENUSBOTG

MD2MD1MD0CK25MOUT

CKSEL VDD12

XI XO VSS NC VDD33IBREF VSS VREF

GPB7/JTDO GPB6/JTMS GPB5/JTDI GPB4/JTRST#GPB3/JTCK

GPB2/URTS#/SVDO GPB1/UTXD/SVDI GPB0/URXD/SVCS#IVDD

GPA7/UCTS#/SVCK

6. Pin Descriptions

Table 1 Pin Descriptions of RTL8672 (128-pin LQFP) Symbol 128 Pin# Type Description

100/10 Physical Layer

RXIP RXIN 7

8

I Ethernet physical layer differential

RX pins

TXOP TXON 4

5

O Ethernet physical layer differential

TX pins

IBREF 126 I Pull-down externally with 2.5k Ohm

for PHY reference

Ethernet PHY LED

NICLED[3:0] 55, 57, 59, 61 O LED driving signals for the

embedded Ethernet PHY;

Pins MA[22:21] sharing with

NICLED[1:0]

Clock & Reset

XI 121 I 25MHz crystal clock input.

XO 122 O 25MHz crystal clock output. CKSEL 119 I Reference clock selection; tied to

1.2 to select XO (25MHz), VSS to

select CKIN (35.328MHz) PWRRST# 41 I System reset.

SPI Control Interface

SVCS# 45 O SPI chip select pin (shared with

GPB0 and URXD)

SVDI 46 I SPI data in (shared with GPB1 and

UTXD)

SVDO 47 O SPI data out (shared with GPB2

and URTS#)

SVCK 48 O SPI reference clock (shared with

GPA7 and UCTS#)

USB Interface

U0DP, U0DM 15, 16 I/O Differential data I/O of USB PHY 0

(Host)

U1DP, U1DM 20, 19 I/O Differential data I/O of USB PHY 1

(host/device controlled by ID)

U1ID 21 I Pull-low/high to select PHY 1 as

host/device

U1VBUS 22 I USB VBUS detect pin; used for

PHY 1 configured in device mode USBLED[1:0] 54, 53 O USB LED driver output

UseOTG 114 I USB PHY1 wired to OTG block

AFE Interface

AFPWDN 40 O Power down control to AFE AFRXD[3:0] 34, 33, 32, 31 I Data input from AFE

AFTXD[3:0] 30, 29, 28, 27 O Data output to AFE

AFCLWD 35 I Word clock input from AFE

CKIN 11 I Master clock from AFE

AFCTRL 37 O Control data output to AFE

VREF 128 I Dying Gasp voltage detect input

Memory Bus

MD[15:0] 95, 96, 97, 98, 100, 101, 103, 104,

105, 106, 108, 110, 112, 115, 116, 117 I/O Data for SDRAM, parallel Flash, and ROM

MA[22:0] 59, 61, 62, 64, 65, 66, 67, 68, 69, 70,

72, 73, 74, 75, 76, 78, 79, 80, 81, 83,

84, 85, 86

O Address for SDRAM and Flash

SDCLK 107 O SDRAM clock

MCS2# 88 O Bank 0 chip select SDRAM chip

select.

MCS3# 90 O Bank 1 chip select SDRAM chip

select

OE#/RAS# 92 O Raw address strobe for SDRAM

interface; output enable for FLASH

interface

CAS# 91 O Column address strobe

WE# 94 O Write enable for SDRAM/ FLASH

interface

DQM[3:0] 66, 65, 68, 67 O DQM[3:0] for SDRAM; shared with

AA17, AA18, AA15, AA16

MCS0# 63 O ROM Bank 0 chip select for FLASH

memory

SFCS# 63 O Chip select of SPI FLASH interface

if enabled (AFPWDN pull-up on

power-on reset)

SFDI 35 I Serial data in of SPI FLASH

interface if enabled; shared with

AFCLWD

SFDO 62 O Serial data out of SPI FLASH

interface if enabled; shared with

MA20

SFCK 64 O Reference clock of SPI FLASH

interface if enabled; shared with

MA19

GPIO

GPIOA[7:5] 43, 42, 25 I/O GPIO port A

GPIOB[7:0] 52, 51, 50, 49, 48, 47, 46, 45 I/O GPIO port B

UART

UCTS# 43 I Clear to send; shared with GPA7

and SV_CK

URXD 45 I RX data; shared with GPB0 and

SV_CS#

UTXD 46 O TX data; shared with GPB1 and

SV_DI

URTS# 47 O Request to send; shared with

GPB2 and SV_DO

JTAG (shared with GPIOB7-3)

JTCK 48 I JTAG test clock; shared with GPB3 JTMS 51 I JTAG test mode select; shared with

GPB6

JTDO 52 O JTAG test data output; shared with

GPB7

JTDI 50 I JTAG test data in; shared with

GPB5

JTRST# 49 I JTAG test reset; shared with GPB4

POWER & GND

VDD12 3, 9, 10, 13, 120 P Analog 1.2V supply

VDD33 2, 14, 23, 125 P Analog 3.3V supply

VSS 6, 12, 17, 18, 123, 127 P Analog ground

DGND 24, 58, 89, 111 P Digital ground

OVDD 39, 60, 71, 82, 93, 102, 113 P 3.3V digital I/O supply

IVDD 26, 36, 44, 56, 77, 87, 99, 109 P 1.2V digital kernel supply

Misc

CK25MOUT 118 O Clock output of 25MHz for possible

peripheral use

VCTRL 1 O Output of the embedded regulator

controller to generate 1.2V VDD for

the kernel supply of the chip.

Connecting to an external PNP-BJT

base if used (BJT collector output

to IVDD); leaving no connection if

not used.

DTEST 124 - No used; leaving no connection TESTMODE 38 I Test only; leaving no connection

Pulled-down internally for normal

operation

7. System Overview TBD

8. Electrical Requirements

8.1. DC Characteristics

8.1.1. Absolute Maximum Rating

Table 2 Absolute Maximum Rating

Parameters Symbol Min Max Unit I/O supply voltage V DDIO TBD TBD V Core supply voltage V DDC TBD TBD V Storage temperature T STG TBD

ESD protection VESD TBD V

8.1.2.Recommended Operation Conditions

Table 3 Recommended Operation Conditions

Parameters Symbol Condition Min Typ Max Unit Operating

temperature

T A Ambient TBD TBD TBD °C

Digital supply for I/O

ring

V DDR TBD 3.3 TBD V

Core power supply

voltage

V DDC TBD 1.2 TBD V Input high voltage V IH TBD V Input low voltage V IL TBD V Input current V IN TBD TBD μA

8.1.3. Power Consumption

Table 4 Power Consumption

Parametes Symbol Condition Estimated Power Unit

Digital supply for I/O ring (3.3V)*V DDR ADSL (ADSL2+

interleaved mode),

Ethernet, PCI are

active

TBD mA

Core power supply voltage (1.2V) V DDC ADSL (ADSL2+

interleaved mode),

Ethernet, PCI active

TBD mA

8.1.4. Reference Crystal

Table 5 Reference Crystal

Parameters Symbol Min Typ Max Unit Center frequency f cf25 MHz Frequency tolerance +-50 ppm

8.1.5. V REF Input

Table 6 V REF Input

Parameters Symbol Min Typ Max Unit Dying gasp trigger level (high to low) V trigger 1.18 V Dying gasp trigger level (low to high) V trigger 1.42 V Thermal drift D Thermal0 V/°C

8.2. AC Characteristics

8.2.1. FLASH – Parallel

Table 7 FLASH Interface Timing

Symbol Parameter Min. Typ. Max. Units Notes T CS The timing interval between

F_CS0#(or F_CS1#) and WE#

ns

T WP The timing interval for WE# to

pulled low (RAS# for read

operation).

ns

Figure 5 Flash Access Timing

8.2.2. FLASH – Serial

TBD

8.2.3. SDRAM 8.2.3.1

SDRAM Input Timing

Table 8

SDRAM Input Timing Symbol Parameter

Min. Typ. Max. Units Notes

T SETUP

Input setup prior to rising edge of clock. Inputs included in this timing are D[15: 0] (during a read operation)

TBD

ns

T HOLD Input hold-time after the rising edge of clock. Inputs include in this timing are D[15: 0] (during a read operation)

TBD TBD ns

Figure 6 SDRAM Input Timing

8.2.3.2 SDRAM Output Timing

Table 9 SDRAM Output Timing

8.2.3.3 SDRAM Access Control Timing

Table 10 SDRAM Control Timing

Symbol Parameter Min. Typ. Max. Units Notes T REFRESH Auto-refresh timing μs

TBD ns T RCD The time interval between

RAS# active and CAS#

active

TBD ns T RP The time interval between

pre-charge and the next

active

TBD ns T RAS The time interval between

active and pre-charge

T RC The time interval between

TBD ns

active and the next active

TBD ns T RFC The time interval between

auto-refresh and active

T CAS_LATENCY The data output delay after

TBD ns

The CAS# active

Figure 8 SDRAM Access Control Timing

8.2.4. AFE

8.2.4.1 Master clock

Table 11 AFE Interface Clock

Symbol Parameter Min. Typ. Max. Units Notes

F Clock frequency 35.328 MHz

T h Clock duty cycle 50 %

8.2.4.2 Transmission Interface

Table 12 AFE TX Interface

Symbol Parameter Min. Typ. Max. Units Notes Tva r Setup time before falling edge of clock. 12 18 ns AFE

latch data

at falling

edge of

clock

8.2.4.3 Reception Interface

Table 13 AFE RX Interface

Symbol Parameter Min. Typ. Max. Units Notes

3 ns

T s Data setup-time prior to falling edge of

clock

T h Data hold-time after falling edge of clock 3 ns

8.2.5. JTAG

Table 14 JTAG Interface Timing

Symbol Parameter Min. Typ. Max. Units Notes T BSCL JTAG clock low time ns

T BSCH JTAG clock high time ns

ns T BSIS TDI, TMS setup time to rising edge of

TCK

T BSIH TDI, TMS hold time from rising edge of

ns

TCK

T BSOH TDO hold time after falling edge of TCK ns

T BSOD TDO output from falling edge of TCK ns

T BSR JTAG reset period ns

ns T BSRS TMS setup time to rising edge of JTAG

reset

T BSRH TMS hold time from rising edge of JTAG

ns

reset