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FN9062.2

ISL6504, ISL6504A

Multiple Linear Power Controller with ACPI Control Interface

The ISL6504 and ISL6504A complement other power building blocks (voltage regulators) in ACPI-compliant designs for microprocessor and computer applications. The IC integrates three linear controllers/regulators, switching, monitoring and control functions into a 16-pin wide-body SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5.

One linear controller generates the 3.3V DUAL/3.3V SB voltage plane from the ATX supply’s 5V SB output, powering the south bridge and the PCI slots through an external NPN pass transistor during sleep states (S3, S4/S5). In active state (during S0 and S1/S2), the 3.3V DUAL/3.3V SB linear regulator uses an external N-channel pass MOSFET to connect the outputs directly to the 3.3V input supplied by an ATX power supply, for minimal losses.

A controller powers up the 5V DUAL plane by switching in the ATX 5V output through an NMOS transistor in active states, or by switching in the ATX 5V S

B through a PMOS (or PNP) transistor in S3 sleep state. In S4/S5 sleep states, the

ISL6504 5V DUAL output is shut down. In the ISL6504A, the 5V DUAL output stays on during S4/S5 sleep states. This is the only difference between the two parts; see Table 1.

An internal linear regulator supplies the 1.2V for the voltage identification circuitry (VID) only during active states (S0 and S1/S2), and uses the 3V3 pin as input source for its internal pass element. Another internal regulator outputs a 1.5V SB chip-set standby supply, which uses the 3V3DL pin as input source for its internal pass element. The 3.3V DUAL/3.3V SB and 1.5V SB outputs are active for as long as the ATX 5V SB voltage is applied to the chip.Features

?Provides four ACPI-Controlled Voltages

-5V DUAL USB/Keyboard/Mouse

- 3.3V DUAL/3.3V SB PCI/Auxiliary/LAN

- 1.2V VID Processor VID Circuitry

- 1.5V SB ICH4 Resume Well

?Excellent Output Voltage Regulation

-All Outputs: ±2.0% over temperature (as applicable)?Small Size; Very Low External Component Count ?Undervoltage Monitoring of All Outputs with Centralized FAULT Reporting and Temperature Shutdown

?QFN Package:

-Near Chip Scale Package Footprint; Improved PCB

Efficiency; Thinner profile

?Pb-Free Available (RoHS Compliant) Applications

?ACPI-Compliant Power Regulation for Motherboards

-ISL6504: 5V DUAL is shut down in S4/S5 sleep states -ISL6504A: 5V DUAL stays on in S4/S5 sleep states

Data Sheet April 13, 2004

Pinouts

ISL6504/A (WIDE BODY SOIC)

TOP VIEW

ISL6504/A (6X 6 QFN)

TOP VIEW

101112131415167

654

321

3V3DLSB 3V3DL S31V2VID 3V31V5SB

5VSB VID_PG DLA SS FAULT

5VDL S5

VID_CT GND 5VDLSB 9

NOTE:SOIC layout should accomodate both wide and narrow footprints.

NOTE:The QFN bottom pad is electrically connected to the IC substrate, at GND potential. It can be left unconnected, or connected to GND; do NOT connect to another potential.

3V 3D L S B

N C

5V S B

1V 5S B

V I D _C T

N C

G N D

F A U L T

S 5

D L A

3V3DL

1V2VID

3V3NC S3

VID_PG NC 5VDL SS 5VDLSB

12345

678910151413121120

1918

1716

Ordering Information

PART NUMBER TEMP. RANGE (o C)PACKAGE PKG. DWG. #ISL6504CB 0 to 7016 Ld SOIC M16.3ISL6504CBZ (Note)0 to 7016 Ld SOIC (Pb-free)M16.3ISL6504CBN 0 to 7016 Ld SOIC M16.15ISL6504CBNZ (Note)0 to 7016 Ld SOIC (Pb-free)M16.15ISL6504CR 0 to 7020 Ld 6x6 QFN L20.6x6ISL6504CRZ (Note)

0 to 70

20 Ld 6x6 QFN (Pb-free)

L20.6x6

ISL6504EVAL1Evaluation Board

ISL6504ACB 0 to 7016 Ld SOIC M16.3ISL6504ACBZ (Note)

0 to 7016 Ld SOIC (Pb-free)M16.3ISL6504ACBN 0 to 7016 Ld SOIC M16.15ISL6504ACBNZ (Note)0 to 7016 Ld SOIC (Pb-free)M16.15ISL6504ACR 0 to 7020 Ld 6x6 QFN L20.6x6ISL6504ACRZ (Note)

0 to 70

20 Ld 6x6 QFN (Pb-free)

L20.6x6

ISL6504AEVAL1

Evaluation Board

Add “-T” suffix for tape and reel.

NOTE:Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL6504, ISL6504A

Simplified Power System Diagram

Typical Application

+5VSB

+3.3VIN

+12VIN SX

+5VIN FAULT

SHUTDOWN

FIGURE 2.

GND

5VSB

+3.3VIN

+5VSB VID_PG

VID_CT

1V5SB

CCT_VID

ISL6504/A

+12VIN VID PGOOD

SLP_S3S3VOUT3

3.3VDUAL/3.3VSB

COUT3

+5VIN COUT4

VOUT45VDUAL

3V3DL

3V3DLSB

DLA

5VDLSB

FAULT

5VDL

SS 1V2VID

SHUTDOWN

FAULT VOUT11.5VSB

VOUT21.2VVID

COUT1

COUT2

SLP_S5

S5CSS

3V3

RDLA

FIGURE 3.

Absolute Maximum Ratings Thermal Information

Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV Recommended Operating Conditions

Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V Digital Inputs, V Sx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . .0o C to 70o C Junction Temperature Range . . . . . . . . . . . . . . . . . . .0o C to 125o C Thermal Resistance (Typical)θJA (o C/W)θJC (o C/W) SOIC Package (Note 1) . . . . . . . . . . .70N/A

QFN Package (Note 2) . . . . . . . . . . . .32 4.0 Maximum Junction Temperature (Plastic Package) . . . . . . . .150o C Maximum Storage Temperature Range . . . . . . . . . -65o C to 150o C Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300o C (SOIC - Lead Tips Only)

For Recommended soldering conditions see Tech Brief TB389.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1.θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT

Nominal Supply Current I5VSB-17-mA Shutdown Supply Current I5VSB(OFF)V SS = 0.8V-4-mA POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS

Rising 5VSB POR Threshold-- 4.5V

5VSB POR Hysteresis-0.9-V Rising 3V3 Threshold- 2.75-V

3V3 Hysteresis-150-mV Falling Threshold Timeout (All Monitors)-10-μs Soft-Start Current I SS-10-μA Shutdown Voltage Threshold V SD--0.8V

VID_PG Rising Threshold- 1.02-V

VID_PG Hysteresis-56-mV 1.5V SB LINEAR REGULATOR (V OUT1)

Regulation-- 2.0%

1V5SB Nominal Voltage Level V1V5SB- 1.5-V

1V5SB Undervoltage Rising Threshold- 1.25-V

1V5SB Undervoltage Hysteresis-75-mV

1V5SB Output Current I1V5SB V3V3DL = 3.3V85--mA 1.2V VID LINEAR REGULATOR (V OUT2)

Regulation-- 2.0%

1V2VID Nominal Voltage Level V1V2VID- 1.2-V

1V2VID Undervoltage Rising Threshold-0.96-V

1V2VID Undervoltage Hysteresis-60-mV

1V2VID Output Current I1V2VID V3V3 = 3.3V40--mA

3.3V DUAL /3.3V SB LINEAR REGULATOR (V OUT3)Sleep State Regulation -- 2.0%3V3DL Nominal Voltage Level V 3V3DL

- 3.3-V 3V3DL Undervoltage Rising Threshold - 2.75-V 3V3DL Undervoltage Hysteresis -150-mV 3V3DLSB Output Drive Current

I 3V3DLSB

V 5VSB = 5V

5V DUAL SWITCH CONTROLLER (V OUT4)5VDL Undervoltage Rising Threshold - 4.10-V 5VDL Undervoltage Hysteresis -200-mV 5VDLSB Output Drive Current I 5VDLSB

V 5VDLSB = 4V , V 5VSB = 5V

-20

-40

TIMING INTERVALS

Active State Assessment Past Input UV Thresholds (Note 3)

202530ms Active-to-Sleep Control Input Delay -200-μs VID_CT Charging Current I VID_CT

V VID_CT = 0V

μA

CONTROL I/O (S3, S5, FAULT)High Level Input Threshold -- 2.2V Low Level Input Threshold

0.8--V S3, S5 Internal Pull-up Impedance to 5VSB -50-k ?FAULT Output Impedance FAULT = high

100

TEMPERATURE MONITOR Fault-Level Threshold (Note 4)125--o C Shutdown-Level Threshold (Note 4)-155

-o C

NOTES:

3.Guaranteed by Correlation.

4.Guaranteed by Design.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Functional Pin Description (SOIC pinout)

3V3 (Pin 5)

Connect this pin to the ATX 3.3V output. This pin provides the output current for the 1V2VID pin, and is monitored for power quality.

5VSB (Pin 16)

Provide a very well de-coupled 5V bias supply for the IC to this pin by connecting it to the ATX 5V SB output. This pin provides all the chip’s bias as well as the base current for Q2 (see typical application diagram). The voltage at this pin is monitored for power-on reset (POR) purposes.

GND (Pin 8)

Signal ground for the IC. All voltage levels are measured with respect to this pin.

S3 and S5 (Pins 6 and 7)

These pins switch the IC’s operating state from active (S0, S1/S2) to S3 and S4/S5 sleep states. These are digital inputs featuring internal 50k? (typical) resistor pull-ups to

5VSB. Internal circuitry de-glitches these pins for disturbances lasting as long as 2μs (typically). Additional circuitry blocks any illegal state transitions (such as S3 to

S4/S5 or vice versa). Respectively, connect S3 and S5 to the computer system’s SLP_S3 and SLP_S5 signals.

FAULT (Pin 9)

In case of an undervoltage on any of the controlled outputs, on any of the monitored ATX voltages, or in case of an overtemperature event, this pin is used to report the fault condition by being pulled to 5VSB. Connect a 1k? resistor from this pin to GND.

SS (Pin 13)

Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1μF recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages. Pulling this pin low with an open-drain device shuts down all the outputs as well as force the FAULT pin low. The C SS capacitor is also used to provide a controlled voltage slew rate during active-to-sleep transitions on the

3.3V DUAL/3.3V SB output.

3V3DL (Pin 3)

Connect this pin to the 3.3V dual/stand-by output (V OUT3). In sleep states, the voltage at this pin is regulated to 3.3V; in active states, ATX 3.3V output is delivered to this node through a fully-on N-MOS transistor. During all operating states, this pin is monitored for undervoltage events. This pin provides all the output current delivered by the 1V5SB pin.

3V3DLSB (Pin 2)

Connect this pin to the base of a suitable NPN transistor. In sleep state, this transistor is used to regulate the voltage at the 3V3DL pin to 3.3V.DLA (Pin 10)

This pin is an open-collector output. Connect a 1k? resistor from this pin to the ATX 12V output. This resistor is used to pull the gates of suitable N-MOSFETs to 12V, which in active state, switch in the ATX 3.3V and 5V outputs into the 3.3V DUAL/3.3V SB and 5V DUAL outputs, respectively.

5VDL (Pin 12)

Connect this pin to the 5V DUAL output (V OUT4). In either operating state (when on), the voltage at this pin is provided through a fully-on MOS transistor. This pin is also monitored for undervoltage events.

5VDLSB (Pin 11)

Connect this pin to the gate of a suitable P-MOSFET or bipolar PNP. ISL6504: In S3 sleep state, this transistor is switched on, connecting the ATX 5V SB output to the

5V DUAL regulator output. ISL6504A: In S3 and S4/S5 sleep state, this transistor is switched on, connecting the ATX

5V SB output to the 5V DUAL regulator output.

1V5SB (Pin 1)

This pin is the output of the internal 1.5V regulator (V OUT1). This internal regulator operates for as long as 5V SB is applied to the IC and draws its output current from the

3V3DL pin. This pin is monitored for undervoltage events.

1V2VID (Pin 4)

This pin is the output of the internal 1.2V voltage identification (VID) regulator (V OUT2). This internal regulator operates only in active states (S0, S1/S2) and is shut off during any sleep state. This regulator draws its output current from the 3V3 pin. This pin is monitored for undervoltage events.

VID_PG (Pin 14)

This pin is the open collector output of the 1V2VID power good comparator. Connect a 10k? pull-up resistor from this pin to the 1V2VID output. As long as the 1V2VID output is below its UV threshold, this pin is pulled low.

VID_CT (Pin 15)

Connect a small capacitor from this pin to ground. The capacitor is used to delay the VID_PG reporting the 1V2VID has reached power good limits.

Description

Operation

The ISL6504/A controls 4 output voltages (Refer to Figures 1, 2, and 3). It is designed for microprocessor computer applications with 3.3V, 5V, 5V SB, and 12V bias input from an ATX power supply. The IC is composed of three linear controllers/regulators supplying the computer system’s

1.5V SB (V OUT1), 3.3V SB and PCI slots’ 3.3V AUX power (V OUT3), the 1.2V VID circuitry power (V OUT2), a dual switch controller supplying the 5V DUAL voltage (V OUT4), as

well as all the control and monitoring functions necessary for complete ACPI implementation.

Initialization

The ISL6504/A automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the 5V SB input supply voltage, initiating

3.3V DUAL /3.3V SB and 1.5V SB soft-start operation shortly after exceeding POR threshold.

Dual Outputs Operational Truth Table

Table 1 describes the truth combinations pertaining to the 3.3V DUAL/SB and 5V DUAL outputs. The last two lines highlight the only difference between the ISL6504 and

ISL6504A. The internal circuitry does not allow the transition from an S3 (suspend to RAM) state to an S4/S5 (suspend to disk/soft off) state or vice versa. The only ‘legal’ transitions are from an active state (S0, S1) to a sleep state (S3, S5) and vice versa.

Functional Timing Diagrams

Figures 4 (ISL6504), 5 (ISL6504A), and 6 are timing diagrams, detailing the power up/down sequences of all the outputs in response to the status of the sleep-state pins (S3, S5), as well as the status of the input ATX supply. Not shown in these

diagrams is the deglitching feature used to protect against false sleep state tripping. Both S3 and S5 pins are protected against noise by a 2μs filter (typically 1–4μs). This feature is useful in noisy computer environments if the control signals have to travel over significant distances. Additionally, the S3 pin

features a 200μs delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200μs interval, if the S5 pin is low, the ISL6504/A switches into S5 sleep state; if the S5 pin is high, the ISL6504/A goes into S3 sleep state.

TABLE 1.5V DUAL OUTPUT (V OUT4) TRUTH TABLE S5S3 3.3VDL/SB

5VDL COMMENTS 11 3.3V 5V S0/S1/S2 States (Active)10 3.3V

01Note

Maintains Previous State 00 3.3V 0V S4/S5 (ISL6504)0

3.3V 5V S4/S5 (ISL6504A)

NOTE:Combination Not Allowed.

FIGURE 4.5V DUAL AND 3.3V DUAL /3.3V SB TIMING

DIAGRAM; ISL6504

5VSB 3.3V, 5V S3S55VDLSB DLA 3V3DLSB

3V3DL 5VDL

FIGURE 5.5V DUAL AND 3.3V DUAL /3.3V SB TIMING

DIAGRAM; ISL6504A

5VSB 3.3V, 5V S3S55VDLSB DLA 3V3DLSB

3V3DL 5VDL

FIGURE 6.1.5V SB , AND 1.2V VID TIMING DIAGRAM

5VSB 3.3V,S3S51V2VID

DLA 1V5SB 5V, 12V

Soft-Start into Sleep States (S3, S4/S5)

The 5V SB POR function initiates the soft-start sequence. An internal 10μA current source charges an external capacitor. The error amplifiers reference inputs are clamped to a level proportional to the SS (soft-start) pin voltage. As the SS pin voltage slews from about 1.25V to 2.5V, the input clamp allows a rapid and controlled output voltage rise.

Figures 7 (ISL6504) and 8 (ISL6504A) show the soft-start sequence for the typical application start-up into a sleep state. At time T0 5V SB (bias) is applied to the circuit. At time T1, the 5V SB surpasses POR level. An internal fast charge circuit quickly raises the SS capacitor voltage to

approximately 1V, then the 10μA current source continues the charging.

The soft-start capacitor voltage reaches approximately 1.25V at time T2, at which point the 3.3V DUAL /3.3V SB and 1.5V SB error amplifiers’ reference inputs start their transition, resulting in the output voltages ramping up

proportionally. The ramp-up continues until time T3 when the two voltages reach the set value. As the soft-start capacitor voltage reaches approximately 2.75V, the undervoltage monitoring circuit of this output is activated and the soft-start capacitor is quickly discharged to approximately 1.25V.

Following the 3ms (typical) time-out between T3 and T4, the soft-start capacitor commences a second ramp-up designed to smoothly bring up the remainder of the voltages required by the system. At time T5, voltages are within regulation limits, and as the SS voltage reaches 2.75V, all the

remaining UV monitors are activated and the SS capacitor is quickly discharged to 1.25V, where it remains until the next transition. As the 1.2V VID output is only active while in an active state, it does not come up, but rather waits until the main ATX outputs come up within regulation limits.

Soft-Start into Active States (S0, S1)

If both S3 and S5 are logic high at the time the 5V SB is

applied, the ISL6504/A will assume active state wake-up and keep off the required outputs until some time (typically

25ms) after the monitored main ATX output (3.3V) exceeds the set threshold. This time-out feature is necessary in order to ensure the main ATX outputs are stabilized. The time-out also assures smooth transitions from sleep into active when sleep states are being supported. 3.3V DUAL /3.3V SB and 1.5V SB outputs will come up right after bias voltage surpasses POR level.

TIME

SOFT-START (1V/DIV)

OUTPUT (1V/DIV)

VOLTAGES VOUT1 (1.5VSB)

VOUT4 (5VDUAL) IF S3

T1T2

5VSB (1V/DIV)

VOUT3 (3.3VDUAL/3.3VSB)

VOUT2(1.2VVID)

VOUT4 (5VDUAL) if S5

FIGURE 7.SOFT-START INTERVAL IN A SLEEP

STATE; ISL6504

SOFT-START (1V/DIV)

OUTPUT (1V/DIV)

VOLTAGES VOUT1 (1.5VSB)

VOUT4 (5VDUAL)

5VSB (1V/DIV)

VOUT3 (3.3VDUAL/3.3VSB)

VOUT2(1.2VVID)

FIGURE 8.SOFT-START INTERVAL IN A SLEEP

STATE; ISL6054A

TIME

During sleep-to-active state transitions from conditions where the 5V DUAL output is initially 0V (such as S5 to S0 transition, or simple power-up sequence directly into active state), the circuit goes through a quasi soft-start, the

5V DUAL output being pulled high through the body diode of the N-Channel MOSFET connected between it and the 5V ATX. Figure 9 exemplifies this start-up case. 5V SB is already present when the main ATX outputs are turned on, at time T0. As a result of +5V IN ramping up, the 5V DUAL output capacitors charge up through the body diode of Q4 (see Typical Application). At time T1, all main ATX outputs exceed the ISL6504/A’s undervoltage thresholds, and the internal 25ms (typical) timer is initiated. At T2, the time-out initiates a soft-start, and the 1.2V voltage ID output is ramped-up, reaching regulation limits at time T3.

Simultaneous with the beginning of this ramp-up, at time T2, the DLA pin is released, allowing the pull-up resistor to turn on Q2 and Q4, and bring the 5V DUAL output in regulation. Shortly after time T3, as the SS voltage reaches 2.75V, the soft-start capacitor is quickly discharged down to

approximately 2.45V, where it remains until a valid sleep state request is received from the system.

Fault Protection

All the outputs are monitored against undervoltage events. A severe overcurrent caused by a failed load on any of the outputs, would, in turn, cause that specific output to

suddenly drop. If any of the output voltages drops below 80% (typical) of their set value, such event is reported by having the FAULT pin pulled to 5V. Additionally, exceeding

the maximum current rating of an integrated regulator (output with pass regulator on chip) can lead to output

voltage drooping; if excessive, this droop can ultimately trip the undervoltage detector and send a FAULT signal to the computer system.

A FAULT condition occurring on an output when controlled through an external pass transistor will only set off the

FAULT flag, and it will not shut off or latch off any part of the circuit. A FAULT condition occurring on an output controlled through an internal pass transistor, will set off the FAULT flag, and it will shut off the respective faulting regulator only. If shutdown or latch off of the entire circuit is desired in case of a fault, regardless of the cause, this can be achieved by externally pulling or latching the SS pin low. Pulling the SS pin low will also force the FAULT pin to go low and reset any internally latched-off output.

Special consideration is given to the initial start-up sequence. If, following a 5V SB POR event, any of the 1.5V SB or 3.3V DUAL /3.3V SB outputs is ramped up and is subject to an undervoltage event before the end of the second soft-start ramp, then the FAULT output goes high and the entire IC latches off. Latch-off condition can be reset by cycling the bias power (5V SB ). Undervoltage events on the 1.5V SB and the 3.3V DUAL /3.3V SB outputs at any other times are handled according to the description found in the second paragraph under the current heading.

Another condition that could set off the FAULT flag is chip overtemperature. If the ISL6504/A reaches an internal

temperature of 140o C (typical), the FAULT flag is set, but the chip continues to operate until the temperature reaches 155o C (typical), when unconditional shutdown of all outputs takes place. Operation resumes only after powering down the IC (to create a 5V SB POR event) and a start-up

(assuming the cause of the fault has been removed; if not, as it heats up again, it will repeat the FAULT cycle).In ISL6504/A applications, loss of the active ATX output (3.3V IN ; as detected by the on-board voltage monitor) during active state operation causes the chip to switch to S5 sleep state, in addition to reporting the input UV condition on the FAULT pin. Exiting from this forced S5 state can only be achieved by returning the faulting input voltage above its UV threshold, by resetting the chip through removal of 5V SB bias voltage, or by bringing the SS pin at a potential lower than 0.8V.

Application Guidelines

Soft-Start Interval

The 5V SB output of a typical ATX supply is capable of 725mA, with newer models rated for 1.0A, and even 2.0A. During power-up in a sleep state, the 5V SB ATX output needs to provide sufficient current to charge up all the applicable output capacitors and, simultaneously, provide some amount of current to the output loads. Drawing

FIGURE 9.SOFT-START INTERVAL IN ACTIVE STATE

TIME

T1T2T3

分销商库存信息:

INTERSIL

ISL6504CBZ-T ISL6504ACRZ ISL6504ACRZ-T ISL6504CBZ ISL6504ACB ISL6504ACB-T ISL6504ACBN ISL6504ACBN-T ISL6504ACR ISL6504ACR-T ISL6504CB ISL6504CB-T ISL6504CBN ISL6504CBN-T ISL6504CR

ISL6504CR-T