Verilog编写7人投票选择器

Verilog编写7人投票选择器

module vote7(pass,vote,absent,agree,object,outabsent); outputpass,agree,object,outabsent;

input[6:0] vote,absent;

reg[2:0] object,agree,outabsent;

integeri;

reg pass;

always@(absent or vote)

begin

object=0;

agree=0;

outabsent=7;

for(i=0;i<=6;i=i+1)

begin

if(absent[i])

begin

outabsent=outabsent-1;

if(vote[i]) agree=agree+1;

else object=object+1;

end

end

if(agree[2:0]>=object[2:0]) pass=1;

else pass=0;

end

endmodule