SPEAR-09-B042中文资料
Preliminary Data
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
May 2008 Rev 11/66
SPEAR-09-B042
SPEAr ? BASIC
ARM 926EJ-S core, customizable logic, large IP portfolio SoC
Features
■ARM926EJ-S core @333 MHz
–16 Kbyte instructions/data cache ■
Reconfigurable logic array:
–300 Kgate (100% utilization rate)–102 I/O lines
–No clock domain limitation
–64 Kbyte + 8 Kbyte configurable memory pool ■Multilayer AMBA 2.0 compliant bus with f MAX 166 MHz
■32-Kbyte boot ROM
■8 Kbyte common static RAM
–Shared with reconfigurable array ■Dynamic power saving features ■High performance DMA –8 channels
■Ethernet 10/100 MAC with MII interface. (IEEE-802.3)
■USB 2.0 device with integrated PHY ■ 2 USB 2.0 host with integrated PHY ■
External DRAM memory interface:–8/16-bit (LPDDR@166 MHz)–8/16-bit (DDR2@333 MHz)– 2 banks available ■Flash interface:
–SPI serial (up to 50 Mbps)
■
SPI master/slave up to 50 Mbps –Compliant with Motorola, Texas
instruments and National semiconductor protocols ■I 2C master/slave mode – high, fast and slow speed
■UARTs (up to 460.8 Kbps)
■
IrDA (FIR/MIR/SIR) compliant serial link from 9.6 Kbps to 4 Mbps speed-rate
■ 6 legacy GPIO bidirectional signals with interrupt capability
■
ADC 10-bit, 1 Msps 8 inputs
–Hw supporting up to 13.5 bits at 8 KSPS by oversampling and accumulation ■JPEG codec accelerator (1 clock/pixel)■C3 crypto accelerator
■ 3 pairs of 16-bit general purpose timers with programmable prescaler ■Real-time clock ■Watchdog ■System controller
■Miscellaneous internal control registers –SOC parameter configuration ■JTAG (IEEE1149.1) interface ■ETM9 interface
■Operating temperature: - 40 to 85 °C ■Low power consumption technology
Description
SPEAr BASIC is a powerful digital engine belonging to SPEAr family, the innovative customizable system-on-chip. The device
integrates an ARM 926 core with an extensive set of proven IPs and a large configurable logic block that allows very fast customization of unique and/or proprietary solutions.
https://www.wendangku.net/doc/602108576.html,
Contents SPEAR-09-B042
Contents
1Reference documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4Architecture properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1Core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1Functional pin group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2Special I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.1USB 2.0 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.2SSTL_2/SSTL_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8Main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1.2CPU ARM 926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.3.1Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.3.2Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.4RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4.1Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4.2Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.5Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.6USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.7USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.832-Kbyte boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/66
SPEAR-09-B042Contents
8.9Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.10JPEG (codec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.11Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.12Low jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.13Main PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.13.1PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.13.2Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.13.3Fractional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.13.4Double side dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.13.5Single side dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.14ADC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.15UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.16IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.17SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.18I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.19DDR memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.20Reconfigurable logic array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.20.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.20.2Custom project development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.20.3Customization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9Standard customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3Standard customization memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4PL_GPIO sharing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4.1LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4.2SD card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.4.3Flexible static memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.4.4Keyboard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.4.5TDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.4.6I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.4.7SPI_I2C cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.4.8GPIO_IT cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4.9One bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Contents SPEAR-09-B042
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9.4.10ADC enhanced control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.4.11Camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.4.12Interrupt and DMA request management . . . . . . . . . . . . . . . . . . . . . . . 55 9.5TDM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.5.1I2S interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.2DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.3General purpose I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.4LPDDR and DDR2 pad electrical characteristics . . . . . . . . . . . . . . . . . . . 62
10.5Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.6PowerGood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPEAR-09-B042List of tables List of tables
Table 1.Pin description by functional group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2.Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3.Main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 4.ICM1 – Low speed connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5.ICM4 – High speed connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6.ML1 – Multi layer CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7.ICM3 – Basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8.Equivalent values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 9.Equivalent values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10.Endpoint assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11.Reconfigurable logic array interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 12.RAS_M – communication subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 13.PL_CLK mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 14.PL_GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 15.KBREG coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 16.TDM block pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 17.I2S interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 18.DAC performances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 19.Maximum picture size according data format and buffer size. . . . . . . . . . . . . . . . . . . . . . . 53 Table 20.Camera interface pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 21.Camera interface timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 22.TDM timing specification (1024 TS = 65536 kHz = 15.26 ns). . . . . . . . . . . . . . . . . . . . . . . 58 Table 23.I2S timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 24.Absolute maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 25.Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 26.Low voltage TTL DC input specification (3V< V DD <3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 27.Low voltage TTL DC output specification (3V< V DD <3.6V). . . . . . . . . . . . . . . . . . . . . . . . 61 Table 28.Pull-up and pull-down characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 29.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 30.Driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 31.On die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 32.Reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 33.Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 34.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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List of figures SPEAR-09-B042 List of figures
Figure 1.SPEAr BASIC functional interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3.Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 4.Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 5.Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 6.Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7.PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 8.SPEAr BASIC standard block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 9.Pre-defined frame sync shapes (slave or master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 10.Switching constant delay between TSy and TSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 11.Type of data carried by the TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 12.External HSYNC synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 13.External VSYNC synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 14.ITU656 embedded synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 15.CSI2 embedded synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 16.Camera interface waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 17.Interrupt and DMA block for telecom peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 18.TDM signals description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 19.TDM signals description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 20.LFBGA289 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6/66
SPEAR-09-B042Reference documentation
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1 Reference documentation
1.
ARM926EJ-S - technical reference manual 2. AMBA 2.0 specification 3. E
IA/J E
SD8-9 specification 4. E
IA/J E SD8-15 specification 5. USB2.0 specification 6. OHCI specification 7. E HCI specification 8. IRPHY version1.39.
IRLAP version 1.110. IE E E 1149.111. IEEE 802.3 – 2002
12. I 2C - bus specification version 2.1
Product overview SPEAR-09-B042
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2 Product overview
An outline diagram of the main SPEAr BASIC functional interfaces is shown in Figure 1.
SPEAR-09-B042Features
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3 Features
The main functionalities implemented in the SPEAr BASIC SoC device are as follows:
●ARM926EJ-S core @333 MHz, 16+16 KB-I/D cache, configurable TMC-I/D size, MMU, TLB, JTAG and ETM trace module (multiplexed interfaces)
●300 KGate reconfigurable logic array (100% utilization rate, 4 metal and 4 vias masks)●64 + 8 Kbyte configurable internal memory pool (single and dual memory port)●32 Kbyte boot ROM (code customizable) ●Dynamic power save features
●High performance linked list 8 channels DMA ●Ethernet MAC 10/100 Mbps (MII PHY interface)
●USB2.0 device (high-full speed), integrated PHY transceiver ● 2 USB2.0 host (high-full-low speed), integrated PHY transceiver
●External memory interface: 8/16-bit mobile LPDDR@166 MHz/DDR2@333 MHz ●Flash interface: SPI serial (up to 50 Mbps)
●SPI master/slave (Motorola, Texas instruments, National semiconductor) up to 50 Mbps ●I2C (high-fast-slow speed) master/slave ●UART (speed rate up to 460.8 Kbps)
●IrDA (FIR/MIR/SIR) 9.6 Kbps to 4 Mbps speed-rate ● 6 legacy GPIOs bidirectional signals with interrupt capability
●102 RAS GPIOs. (User customizable bidirectional signals with no clock domain limitations)
●ADC (1μs/1Msps) with 8 analog input channels, 10-bit approximation (supporting up to 13.5 bits at 8 KSPS by oversampling and accumulation)●JPEG codec accelerator 1clock/pixel
●
ST C3 (channel controller co-processor) flexible engine is a configurable array of
Macro-Functions (channels) controlled by instruction dispatchers allowing symmetric or public key cryptography
● 3 pairs of 16-bits general purpose timers with programmable prescaler ●RTC – WDOG – SYSCTR – MISC internal control registers ●JTAG (IEEE1149.1) interface
●
ETM9 interface and EmbeddedICE-RT
Architecture properties SPEAR-09-B042
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4 Architecture properties
●
Power save features:–Operating frequency SW programmable –Clock gating functionality –Low frequency operating mode
–
Automatic power saving controlled from application activity demands ●
Customizable logic to embed the customer's application:–300 Kgate standard cell array
–Internal memory pool (64 + 8 Kbyte) fully configurable
–Up to 10 internal source clocks (some of these are programmable)–No clock domain limits (every PL_GPIO can clock the customizable logic)–
Three memory paths toward the DRAM controller to ensure for optimal bandwidth
●Easily extendable architecture
●
External memory bandwidth of each master tuneable to meet the target performance of
different applications
SPEAR-09-B042Block diagram
11/66
5 Block diagram
5.1 Core architecture
The SoC internal architecture is based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix as detailed in Figure 2.The switch matrix structure allows different subsystem dataflows to be executed in parallel improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller reducing the memory access latency. Three different memory paths (two of them shared with other masters) are reserved for the programmable logic to enhance the user application throughput. The overall memory bandwidth assigned to each master port can be
programmed and optimized through an internal efficient weighted round-robin arbitration mechanism.
The internal memory pool is completely configurable to improve the performance of the user application custom logic.
SPEArBASIC
Configurable Cell Array Subsystem
Common Subsystems
Applic Subsys.C3
Low Speed Subsystem Basic Subsystem HS Subsystem
DMA (8-chan.)
ROM (32KB)
Flash Serial
Multi-layer Interconnection Matrix
SDRAM
Controller -DDR2 -DDRmob
CPU
1
4
2
5-23
ARM Subsystem
Tmr APB
Eth.Mac
USB2.0Dev
USB2.0
hub-2host
A
B D Cell Array
(Applic. configurable)
M
1-123
M 0
M 1
M 2M 3M 4C F G
E
H
R I -O
Tmr 1-2
WDG RTC
Gpio
Sys Ctr Misc
3
Uart
SPI
I2C
34
F
P L
Q
ARM926EJ-S
Cache: 16kI 16kD
Coprocessor i/f Tcm-I/D I D
SRAM 16KB
SRAM
16KB SRAM 16KB
SRAM 16KB JPEG (Codec)
RAM (8KB)
IrDA
Int.Ctr
ADC
M t x -7
4-12
4
3-12
C 2-12(4)
M t x -8
6
G 1-2
6-78
I
7
8
7
6
Pins description SPEAR-09-B042
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6 Pins description
6.1 Functional pin group
Table 1 shows the pin list with functional pins grouped by IP , and power pins (including
grounds) grouped seperately. Please refer also to Section 11.
Table 1.
Pin description by functional group
Group Signal name
Ball Direction Function
Pin type
ADC
AIN_0N16Input
ADC analog input channel
Analog buffer 2.5V tolerant
AIN_1N15AIN_2P17AIN_3P16AIN_4P15AIN_5R17AIN_6R16AIN_7R15ADC_VREFN N14ADC negative voltage reference
ADC_VREFP
P14ADC positive voltage reference
DEBUG TEST_0K16Input
T est configuration ports. For functional mode they must be set to zero.
TTL input buffer, 3.3 V tolerant, PD TEST_1K15TEST_2K14TEST_3K13TEST_4J15BOOT_SEL
J14
nTRST
L16
Input
T est reset input
TTL Schmitt trigger input buffer, 3.3 V tolerant, PU TDO L15Output T est data output TTL output buffer, 3.3 V capable,4 mA
TCK L17Input T est clock TTL Schmitt trigger input buffer, 3.3 V tolerant, PU
TDI L14Input T est data input TMS
L13Input T est mode select PL_I/O
PL_GPIO_0F3I/O
Shared I/O
TTL BIDIR buffer, 3.3 V
capable, 4mA 3.3 V tolerant, PU
PL_GPIO_1E3PL_GPIO_2E4PL_GPIO_3
D1
SPEAR-09-B042Pins description
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PL_GPIO_4C1PL_GPIO_5D2PL_GPIO_6B1PL_GPIO_7D3PL_GPIO_8C2PL_GPIO_9B2PL_GPIO_10C3PL_GPIO_11E5PL_GPIO_12D4PL_GPIO_13A1PL_GPIO_14A2PL_GPIO_15B3PL_GPIO_16E6PL_GPIO_17C4PL_GPIO_18D5PL_GPIO_19A3PL_GPIO_20B4PL_GPIO_21C5PL_GPIO_22D6PL_GPIO_23A4PL_GPIO_24B5PL_GPIO_25C6PL_GPIO_26A5PL_GPIO_27B6PL_GPIO_28A6PL_GPIO_29A7PL_GPIO_30B7PL_GPIO_31
C7PL_I/O PL_GPIO_32D7I/O
Shared I/O
TTL BIDIR buffer, 3.3 V
capable, 4mA 3.3 V tolerant, PU
PL_GPIO_33E7PL_GPIO_34E8PL_GPIO_35D8PL_GPIO_36C8PL_GPIO_37B8PL_GPIO_38
A8
Table 1.
Pin description by functional group (continued)
Group
Signal name Ball Direction
Function
Pin type
Pins description SPEAR-09-B042
14/66PL_GPIO_39A9 PL_GPIO_40B9 PL_GPIO_41C9 PL_GPIO_42D9 PL_GPIO_43E9 PL_GPIO_44A10 PL_GPIO_45B10 PL_GPIO_46A11 PL_GPIO_47C10 PL_GPIO_48B11 PL_GPIO_49C11 PL_GPIO_50A12 PL_GPIO_51D10 PL_GPIO_52B12 PL_GPIO_53D11 PL_GPIO_54E10 PL_GPIO_55A13 PL_GPIO_56C12 PL_GPIO_57E11 PL_GPIO_58D12 PL_GPIO_59B13 PL_GPIO_60A14 PL_GPIO_61E12 PL_GPIO_62A15 PL_GPIO_63C13 PL_GPIO_64D13 PL_GPIO_65B14 PL_GPIO_66E13 PL_GPIO_67C14 PL_GPIO_68B15 PL_GPIO_69A16 PL_GPIO_70C15 PL_GPIO_71D14 PL_GPIO_72B16 PL_GPIO_73A17
Table 1.Pin description by functional group (continued)
Group Signal name Ball Direction Function Pin type
SPEAR-09-B042Pins description
15/66
PL_GPIO_74C16PL_GPIO_75E14PL_GPIO_76F13PL_GPIO_77B17PL_GPIO_78D15PL_GPIO_79F14PL_GPIO_80D16PL_GPIO_81C17PL_GPIO_82E15PL_GPIO_83E16PL_GPIO_84D17PL_GPIO_85F15PL_GPIO_86E17PL_GPIO_87G13PL_GPIO_88F16PL_GPIO_89F17PL_GPIO_90G14PL_GPIO_91G15PL_GPIO_92G16PL_GPIO_93G17PL_GPIO_94H13PL_GPIO_95H14PL_GPIO_96H15PL_GPIO_97
H16PL_CLK PL_CLK_1K17I/O
Shared external clock
TTL BIDIR buffer, 3.3 V capable,
8mA 3.3 V tolerant, PU
PL_CLK_2J17PL_CLK_3J16PL_CLK_4
H17DDR I/F DDR_ADD_0T2Output
Address line
SSTL_2/SSTL_18
DDR_ADD_1T1DDR_ADD_2U1DDR_ADD_3U2DDR_ADD_4U3DDR_ADD_5U4DDR_ADD_6
U5
Table 1.
Pin description by functional group (continued)
Group
Signal name Ball Direction
Function
Pin type
Pins description SPEAR-09-B042
16/66
DDR_ADD_7T5
DDR_ADD_8R5
DDR_ADD_9P5
DDR_ADD_10P6
DDR_ADD_11R6
DDR_ADD_12T6
DDR_ADD_13U6
DDR_ADD_14R7
DDR_BA_0P7Output Bank select SSTL_2/SSTL_18
DDR_BA_1P8
DDR_BA_2R8
DDR_RAS U8Output Row add. strobe SSTL_2/SSTL_18
DDR_CAS T8Output Col. add. strobe SSTL_2/SSTL_18
DDR_WE T7Output Write enable SSTL_2/SSTL_18
DDR_CLKEN U7Output Clock enable SSTL_2/SSTL_18
DDR_CLK_P T9Output Differential clock Differential SSTL_2/SSTL_18 DDR_CLK_N U9
DDR_CS_0P9Output Chip select SSTL_2/SSTL_18
DDR_CS_1R9
DDR_ODT_0T3I/O On-die termination
enable lines
SSTL_2/SSTL_18
DDR_ODT_1T4
DDR_DA T A_0P11I/O Data lines
(lower byte)
SSTL_2/SSTL_18
DDR_DA T A_1R11
DDR_DA T A_2T11
DDR_DA T A_3U11
DDR_DA T A_4T12
DDR_DA T A_5R12
DDR_DA T A_6P12
DDR_DA T A_7P13
DDR_DQS_0U10Output Lower data strobe Differential SSTL_2/SSTL_18 DDR_nDQS_0T10
DDR_DM_0U12Output Lower data mask SSTL_2/SSTL_18
DDR_GA TE_0R10I/O Lower gate open SSTL_2/SSTL_18
DDR_DA T A_8T17
I/O Data lines
(upper byte)
SSTL_2/SSTL_18
Table 1.Pin description by functional group (continued)
Group Signal name Ball Direction Function Pin type
SPEAR-09-B042Pins description
17/66
DDR_DA T A_9T16DDR_DA TA_10U17DDR_DA TA_11U16DDR_DA TA_12U14DDR_DA TA_13U13DDR_DA TA_14T13DDR_DA TA_15R13DDR_DQS_1U15I/O
Upper data strobe
Differential
SSTL_2/SSTL_18DDR_nDQS_1T15DDR_DM_1T14I/O Upper data mask SSTL_2/SSTL_18DDR_GA TE_1R14I/O Upper gate open SSTL_2/SSTL_18DDR_VREF P10Input Reference voltage Analog DDR_COMP_GND R4Power Return for external resistors
Power DDR_COMP_1V8
P4Power External resistor 1.8V Analog
DDR2_EN
J13Input Configuration TTL input buffer 3.3 V tolerant, PU
USB DEV_DP M1I/O
USB device D+Bidirectional analog buffer 5V tolerant
DEV_DM M2USB device D-DEV_VBUS G3Input USB device VBUS TTL Input buffer 3.3 V tolerant, PD
HOST1_DP H1I/O USB HOST1 D+Bidirectional analog buffer 5V tolerant
HOST1_DM H2USB HOST1 D-HOST1_VBUS H3Output USB HOST1 VBUS
TTL output buffer 3.3 V capable, 4mA
HOST1_OVRC J4Input USB host1 over-current TTL input buffer 3.3 V
tolerant, PD HOST0_DP K1I/O USB HOST0 D+Bidirectional analog buffer 5v tolerant HOST0_DM K2USB HOST0 D-HOST0_VBUS J3Output USB HOST0 VBUS
TTL Output Buffer 3.3 V capable, 4mA
HOST0_OVRC H4Input USB host0 over-current TTL input buffer 3.3 V
tolerant, PD USB_TXRTUNE K5Output Reference resistor Analog USB_ANALOG_TE
ST
L4Output Analog test output Analog
Master Clock
MCLK_XI P1Input Output 24 MHz crystal I Oscillator 2.5V capable
MCLK_XO
P2
24 MHz crystal O
Table 1.
Pin description by functional group (continued)
Group
Signal name Ball Direction
Function
Pin type
Pins description SPEAR-09-B042
18/66
Note:PU means Pull Up and PD means pull down
RTC
RTC_XI E2Input 32KHz crystal I Oscillator 1V capable
RTC_XO
E1Output 32 KHz crystal O SMI
SMI_DA TAIN M13I/O Serial Flash input data
TTL input buffer 3.3 V tolerant, PU
SMI_DA TAOUT M14I/O Serial Flash output data TTL output buffer 3.3 V
capable, 4mA
SMI_CLK N17I/O Serial Flash clock SMI_CS_0M15Output
Serial Flash chip select
SMI_CS_1
M16Reset MRESET M17Input Main reset TTL Schmitt trigger input buffer, 3.3 V tolerant, PU 3.3 V Com-pens.
DIGITAL_REXT G4Output Configuration Analog, 3.3 V capable DIGIT AL_GND_RE
XT
F4
Power
Power
Power
Table 1.
Pin description by functional group (continued)
Group Signal name Ball Direction Function
Pin type
SPEAR-09-B042
Pins description
19/66
6.2 Special I/Os
6.2.1 USB 2.0 transceiver
SPEAr BASIC has three USB 2.0 transceivers. One transceiver is used by the USB device
controller, and two are used by the hosts. The transceivers are all integrated into a single USB three-PHY macro.
6.2.2 SSTL_2/SSTL_18
Fully complaint with JEDEC specification with programmable integrated terminations.
Table 2.
Power supply
Signal name
Ball
Value GND G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11 J6 J7 J8 J9 J10 J11 K6 K7 K8 K9 K10 K11 L6 L7 L8 L9 L10 M8 M9 M100 V AGND F2, G1, J2, L1, L3, L5, N2, N4, P3, R30 V VDD3F5 F6 F7 F10 F11 F12 G5 J12 K12 L12 M12 3.3 V VDD F8 F9 G12 H5 H12 J5 L11 M6 M7 M11 1.2 V HOST0_VDDbc L2 2.5 V HOST0_VDDb3K4 3.3 V HOST1_VDDbc K3 2.5 V HOST1_VDDb3J1 3.3 V DEVICE_VDDbc N1 2.5 V USB_VDDbs M3 1.2 V DEVICE_VDDb3N3 3.3 V MCLK_VDD R1 1.2 V MCLK_VDD2v5R2 2.5 V DITH1_AVDD G2
2.5 V SSTL_VDDe M5 N5 N6 N7 N8 N9 N10 N11 1.8 V ADC_AGND N120V ADC_AVDD N13 2.5 V DITH2_AVDD M4 2.5 V RTC_VDD
F1
1.5 V
Memory map SPEAR-09-B042
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7 Memory map
Table 3.
Main memory map
Start address End address Peripheral Notes 0x0000.00000x3FFF .FFFF External DRAM
Low power DDR or
DDR20x4000.00000xBFFF .FFFF RAS_M
Customizable logic
array
0xC000.00000xCFFF .FFFF -Reserved 0xD000.00000xD7FF .FFFF ICM1Low speed connection
0xD800.00000xDFFF .FFFF -Reserved 0xE000.00000xE7FF .FFFF ICM4High speed connection
0xE800.00000xEFFF .FFFF -Reserved 0xF000.00000xF7FF .FFFF ML1Multi layer CPU subsystem 0xF800.0000
0xFFFF .FFFF
ICM3
Basic subsystem
Table 4.
ICM1 – Low speed connection
Start address End address Peripheral Notes
Bus 0xD000.00000xD007.FFFF UART APB 0xD008.00000xD00F .FFFF ADC
APB
0xD010.00000xD017.FFFF SPI APB 0xD018.00000xD01F .FFFF I2C APB 0xD020.00000xD07F .FFFF -Reserved
APB 0xD080.00000xD0FF .FFFF JPEG codec
AHB 0xD100.00000xD17F .FFFF IrDA AHB 0xD180.00000xD1FF .FFFF -Reserved AHB 0xD280.00000xD2FF .FFFF SRAM Static RAM shared memory (8 Kbyte)
AHB 0xD300.0000
0xD7FF .FFFF
-Reserved AHB