ESD、EOS Solution
ESD/EOS Solution
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OUTLINE
◆ Component Level ESD Event ◆ System Level ESD/CDE/EFT/Surge Event ◆ Transient Voltage Suppressor (TVS) ◆ System ESD Protection Design ◆ Summary
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Component Level ESD Event
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ESD : ElectroStatic Discharge
Discharge event due to tribo-electrically generated charges. ESD is a High-Current (~Amps) and Short-duration (~ ns) stress event.
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ESD Is So Serious !
Electrostatic Voltage Means of Static Generation
10% R.H.
End-user’s Endenvironment
40% R.H.
15,000 V 5,000 V 500 V 700 V 4,000 V 20,000 V 11,000 V
55% R.H.
7,500 V 3,000 V 400 V 400 V 2,000 V 7,000 V 5,500 V
Person walking across Carpet Person walking across Vinyl Floor Worker at a Bench Ceramic DIP in Plastic Tube
35,000 V 12,000 V 6,000 V 2,000 V 11,500 V 26,000 V 21,000 V
Factory’s environment
Ceramic DIP in Vinyl Set-up Trays IC Packs as Bubble Plastic Cover is removed IC Packs as Packed in Foam Lined Shipping Box
Need ESD Control in the Factory Environment!!!
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ESD Events for IC’s (Component Level) Component Level:
(To Simulate the ESD events in a well well-controlled environment, such as factory environment) To characterize a component’s (e.g. (e.g. IC’s) IC’s) electrostatic discharge (ESD) susceptibility fully, it should be tested to the following three ESD test standards: Human Body Model– Model–HBM : Discharge to the IC’s. (ANSI/ESD STM5.1STM5.1-2001) Machine Model– Model–MM : Discharge to the IC’s. (ANSI/ESD STM5.2STM5.2-1999) Charged Device Model– Model–CDM: Discharge from the IC’s. (ANSI/ESD STM5.3.1STM5.3.1-1999)
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(1). Human Body Model (HBM)
Discharge to the Component
R
A
B
1.5k?
+
V
_
0Ω?
100pF
DEVICE UNDER TEST
CHBM= 100pF; RHBM= 1.5k?
Ips = 1.33 A ±10% (for 2 kV) Rise time (tr) = 2 ~ 10 ns Decay time (td) = 150 ± 20 ns
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(2). Machine Model (MM)
Discharge to the Component
Approximate 500 NanoHenry R
A B
+
V
_
200pF
DEVICE UNDER TEST
Standards : 1. EIAJ ED-4701/300 Test Method 304 2. EIA/JESD 22-A115-A 3. ANSI/ESD STM5.2
Ip1 = ~ 3.8A (for 200V), 7.0 A (for 400V) Ip1 × 90% ≥ Ip2 ≥ Ip1 × 67% 90 ns ≥ tpm ≥ 66 ns, Freq. ~ 16 MHz
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(3). Charged Device Model (CDM)
Discharge from the Component
Surface Resistance
Rg Rd Ld Cd GND
Device Under Test
VESD
Ipeak= 15A (for 1000-V CDM @ 4pF) tr < 200ps (for CDM @4pF)
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Comparisons among the ESD Pulses
A 50
40 30 20 10 0 -10 -20
CDM (30pf Test Module)
HBM (0.67A Peak)
Comparison of 1kV CDM, HBM, and MM discharges
MM
50
100
150
200 ns
Rise Time: CDM < MM < HBM
Duration : HBM > MM > CDM
Peak Current: CDM > MM > HBM
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General ESD Specifications for IC Products
HBM Okay Safe Super +/- 2kV +/- 4kV +/- 10kV MM +/- 200V +/- 400V +/- 1kV CDM +/- 1kV +/- 1.5kV +/- 2kV
Basic Spec. for Commercial IC’s
* An IC during ESD test with all pin combinations has to pass above ESD specifications (both positive and negative ESD voltages). * ESD failure criterion including pin leakage current and all function testing.
This Spec. Can’t Guarantee System Level ESD Performance!
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System Level ESD Event
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SystemSystem -Level ESD Testing Standard
? IEC 6100061000-4-2: Electromagnetic Compatibility (EMC) Part 4: Testing and measurement techniques Session 2: Electrostatic discharge immunity Test.
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SystemSystem -Level ESD Gun (IEC/EN 6100061000-4-2)
Contact discharge head
Air discharge head
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