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82541中文资料

82541 Family of Gigabit Ethernet Controllers

Networking Silicon - 82541(PI/GI/EI)

Datasheet Product Features

■PCI Bus

—PCI revision 2.3, 32-bit, 33/66 MHz

—Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands

—CLK_RUN# signal

—3.3 V (5 V tolerant PCI signaling)

■MAC Specific

—Low-latency transmit and receive queues

—IEEE 802.3x-compliant flow-control support with software-controllable thresholds —Caches up to 64 packet descriptors in a single burst

—Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to

256 B)

—Wide, optimized internal data path

architecture

—64 KB configurable Transmit and Receive FIFO buffers

■PHY Specific

—Integrated for 10/100/1000 Mb/s full- and half-duplex operation

—IEEE 802.3ab Auto-Negotiation and PHY compliance and compatibility

—State-of-the-art DSP architecture implements digital adaptive equalization, echo and cross-

talk cancellation

—Automatic polarity detection

—Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds ■Host Off-Loading

—Transmit and receive IP, TCP, and UDP checksum off-loading capabilities

—Transmit TCP segmentation and advanced packed filtering

—IEEE 802.1Q VLAN tag insertion and stripping and packet filtering for up to 4096

VLAN tags

—Jumbo frame support up to 16 KB

—Intelligent Interrupt generation (multiple packets per interrupt)

■Manageability

—On-chip SMBus 2.0 port

—ASF 1.0 and 2.0

—Compliance with PCI Power Management v1.1/ACPI v2.0

—Wake on LAN* (WoL) support

—Smart Power Down mode when no signal is detected on the wire

—Power Save mode switches link speed from 1000 Mb/s down to 10 or 100 Mb/s when on

battery power

■Additional Device

—Four programmable LED outputs

—On-chip power regulator control circuitry

—BIOS LAN Disable pin

—JTAG (IEEE 1149.1) Test Access Port built in silicon (3.3 V, 5 V tolerant PCI signaling)■Lead-free a 196-pin Ball Grid Array (BGA).

Devices that are lead-free are marked with a

circled “e1” and have the product code:

LUxxxxxx.

a.This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at

<1000 ppm.The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at:

ftp://https://www.wendangku.net/doc/e48531200.html,/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks

In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device.

For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales represen-tative

318138-002

Revision 2.7

Revision History

Revision

Revision Description

Date

Aug 20020.25?Initial Release.

Sep 20020.75?Changed package diagram to molded plastic BGA.

?Added DC/AC specifications.

?Corrected pinout information.

Oct 2002 1.0?Identified FIFO as 64 KB and verified ballout tables.

July 2003 1.5?Added 82547GI coverage.

?Signals CLKR_CAP and XTAL_CAP changed to RSVD_NC and NC, respectively.

Oct 2004 2.0?Added Architecture Overview chapter.

?Update signal names to match Design Guide and EEPROM Map and Program-

ming Application Note.

Nov 2004 2.1?Updated lead-free information.

?Added information about migrating from a 2-layer 0.36 mm wide-trace substrate

to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and

Pinout Information.

?Added statement that no changes to existing soldering processes are needed for

the 2-layer 0.32 mm wide-trace substrate change in the section describing “Pack-

age Information”.

Jan 2005 2.2?Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See

Table 2, Recommended Operating Conditions and Table 6, DC Characteristics.

Apr 2005 2.3?Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is

not used then an external pull-down resistor is required.

June 2006 2.4?Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is

not used then an external pull-up resistor is required.

Aug 2006 2.5?Removed note “b” from Table 2 and note “a” from Tables 3 and 4.

?Moved the note following Table 5 before Table 3.

Aug 2007 2.6?Replace Intel logo, updated the Product Features title page, and document order-

ing information.

Dec 2007 2.7?Updated Section 3.3. Removed the internal pullup device text from the FLASH

Serial Data Output / LAN Disable pin description.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82541 Family of Gigabit Ethernet Controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

P.O. Box 5937

Denver, CO 80217-9808

or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-296-9333

Intel? is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without intent to infringe.

Networking Silicon — 82541(PI/GI/EI) Contents

1.0Introduction (7)

1.1Document Scope (7)

1.2Reference Documents (8)

1.3Product Codes (8)

2.0Architectural Overview (11)

2.1External Architecture Block Diagram (11)

2.2Internal MAC Architecture Block Diagram (12)

2.3Integrated 10/100/1000Mbps PHY (12)

2.4System Interface (12)

3.0Signal Descriptions (11)

3.1Signal Type Definitions (11)

3.2PCI Bus Interface Signals (56) (11)

3.2.1PCI Address, Data and Control Signals (44) (12)

3.2.2Arbitration Signals (2) (13)

3.2.3Interrupt Signal (1) (13)

3.2.4System Signals (4) (13)

3.2.5Error Reporting Signals (2) (14)

3.2.6Power Management Signals (3) (14)

3.2.7SMB Signals (3) (14)

3.3EEPROM and Serial FLASH Interface Signals (9) (15)

3.4Miscellaneous Signals (15)

3.4.1LED Signals (4) (15)

3.4.2Other Signals (4) (16)

3.5PHY Signals (16)

3.5.1Crystal Signals (2) (16)

3.5.2Analog Signals (10) (16)

3.6Test Interface Signals (6) (17)

3.7Power Supply Connections (17)

3.7.1Digital and Analog Supplies (17)

3.7.2Grounds, Reserved Pins and No Connects (18)

3.7.3Voltage Regulation Control Signals (2) (18)

4.0Voltage, Temperature, and Timing Specifications (19)

4.1Absolute Maximum Ratings (19)

4.2Targeted Recommended Operating Conditions (19)

4.2.1General Operating Conditions (19)

4.2.2Voltage Ramp and Sequencing Recommendations (20)

4.3DC Specifications (22)

4.4AC Characteristics (25)

4.5Timing Specifications (27)

5.0Package and Pinout Information (33)

5.1Package Information (33)

5.2Thermal Specifications (35)

5.3Pinout Information (36)

82541(PI/GI/EI) — Networking Silicon

5.4Visual Pin Assignments (46)

Figures

182541(PI/GI/EI) External Architecture Block Diagram (11)

2Internal Architecture Block Diagram (12)

3AC Test Loads for General Output Pins (27)

4AC Test Loads for General Output Pins (28)

5AC Test Loads for General Output Pins (29)

6AC Test Loads for General Output Pins (29)

7TVAL (max) Rising Edge Test Load (30)

8TVAL (max) Falling Edge Test Load (30)

9TVAL (min) Test Load (30)

10TVAL Test Load (PCI 5 V Signaling Environment) (31)

11Link Interface Rise/Fall Timing (31)

1182541(PI/GI/EI) Mechanical Specifications (33)

12196 PBGA Package Pad Detail (34)

13Visual Pin Assignments (46)

Tables

1Absolute Maximum Ratings (19)

2Recommended Operating Conditions (19)

3 3.3V Supply Voltage Ramp (20)

4 1.8V Supply Voltage Ramp (20)

5 1.2V Supply Voltage Ramp (21)

6DC Characteristics (22)

7Power Specifications - D0a (22)

8Power Specifications - D3cold (23)

9Power Specifications D(r) Uninitialized (23)

10Power Specifications - Complete Subsystem (24)

11I/O Characteristics (24)

12AC Characteristics: 3.3 V Interfacing (25)

1325 MHz Clock Input Requirements (25)

14Reference Crystal Specification Requirements (26)

15Link Interface Clock Requirements (26)

16EEPROM Interface Clock Requirements (26)

17PCI Bus Interface Clock Parameters (27)

18PCI Bus Interface Timing Parameters (28)

19PCI Bus Interface Timing Measurement Conditions (29)

20Link Interface Rise and Fall Times (31)

21EEPROM Link Interface Clock Requirements (32)

22EEPROM Link Interface Clock Requirements (32)

13Thermal Characteristics (35)

14PCI Address, Data and Control Signals (36)

15PCI Arbitration Signals (36)

16Interrupt Signals (36)

17System Signals (36)

18Error Reporting Signals (37)

19Power Management Signals (37)

20SMB Signals (37)

Networking Silicon — 82541(PI/GI/EI) 21Serial EEPROM Interface Signals (37)

22Serial FLASH Interface Signals (37)

23LED Signals (37)

24Other Signals (38)

25IEEE Test Signals (38)

26PHY Signals (38)

27Test Interface Signals (38)

28Digital Power Signals (38)

29Analog Power Signals (39)

30Grounds and No Connect Signals (39)

31Voltage Regulation Control Signals (39)

32Signal Names in Pin Order (40)

82541(PI/GI/EI) — Networking Silicon

Note:This page is intentionally blank.

Networking Silicon — 82541(PI/GI/EI) 1.0Introduction

The Intel? 82541(PI/GI/EI) Gigabit Ethernet is a single, compact component with an integrated

Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop,

workstation and mobile PC Network designs with critical space constraints, the Intel? 82541(PI/

GI/EI) allows for a Gigabit Ethernet implementation in a very small area that is footprint

compatible with current generation 10/100 Mbps Fast Ethernet designs.

The Intel? 82541(PI/GI/EI) integrates fourth generation gigabit MAC design with fully integrated,

physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable

of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to

managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral

Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz.

The 82541(PI/GI/EI) also incorporates the Clock Run protocol and hardware supported downshift

capability to two-pair and three-pair 100 Mbps operation. These features optimize mobile

applications.

The 82541(PI/GI/EI) on-board System Management Bus (SMB) port enables network

manageability implementations required by information technology personnel for remote control

and alerting via the Local Area Network (LAN). With SMB, management packets can be routed to

or from a management processor. The SMB port enables industry standards, such as Intelligent

Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2.0, to be implemented

using the 82541(PI/GI/EI). In addition, on chip ASF 2.0 circuitry provides alerting and remote

control capabilities with standardized interfaces.

The 82541(PI/GI/EI) Gigabit Ethernet Controller Architecture is designed for high performance

and low memory latency. Wide internal data paths eliminate performance bottlenecks by efficiently

handling large address and data words. The 82541(PI/GI/EI) controller includes advanced interrupt

handling features to limit PCI bus traffic and a PCI interface that maximizes efficient bus usage.

The 82541(PI/GI/EI) uses efficient ring buffer descriptor data structures, with up to 64 packet

descriptors cached on chip. A large 64-KByte onchip packet buffer maintains superior performance

as available PCI bandwidth changes. In addition, using hardware acceleration, the controller

offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP

segmentation.

The 82541(PI/GI/EI) is packaged in a 15 mm x 15 mm 196-ball grid array and is pin compatible

with the 82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller,

82562EZ(EX) Platform LAN Connect devices, and the 82540EP(EM) Gigabit Ethernet Controller.

1.1Document Scope

The 82541EI is the original device and is now being manufactured in a B0 stepping. The 82541GI

(B1 stepping) and 82541PI (C0 stepping) are pin compatible, however, a different Intel software

driver is required from the 82541EI. This document contains datasheet specifications for the

82541(PI/GI/EI) Gigabit Ethernet Controllers including signal descriptions, DC and AC

parameters, packaging data, and pinout information.

82541(PI/GI/EI) — Networking Silicon

1.2Reference Documents

This document assumes that the designer is acquainted with high-speed design and board layout

techniques. The following documents provide additional information:

?82540EP/82541(PI/GI/EI) & 825462EZ(EX) Dual Footprint Design Guide, AP-444. Intel Corporation.

?82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map and Programming Information Guide, AP-446. Intel Corporation.

?PCI Local Bus Specification, Revision 2.3. PCI Special Interest Group (SIG).

?PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group (SIG).

?IEEE Standard 802.3, 2000 Edition. Incorporates various IEEE standards previously published separately. Institute of Electrical and Electronic Engineers (IEEE).

?PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group (SIG).

Software driver developers should contact their local Intel representatives for programming

information.

1.3Product Codes

The product ordering codes for the 82541 Family of Gigabit Ethernet Controllers:

?GD82541PI

?GD82541GI

?GD82541EI

?LU82541PI

?LU82541GI

?LU82541EI

Networking Silicon — 82541(PI/GI/EI) 2.0Architectural Overview

2.1External Architecture Block Diagram

The 82541(PI/GI/EI) architecture is a derivative of the 82542, 82543, and 82544 designs that

provided Media Access Controller (MAC) functionality as well as an integrated 10/100/1000Mbps

copper PHY. The 82541(PI/GI/EI) family architecture now adds SMBus-based manageability and

an integrated ASF controller functionality to the MAC.

Figure 1. 82541(PI/GI/EI) External Architecture Block Diagram

82541(PI/GI/EI) — Networking Silicon

2.2Internal MAC Architecture Block Diagram

Figure 2 shows the major internal function blocks of 82541(PI/GI/EI) MAC device. Compared to

its predecessors, the 82541(PI/GI/EI) MAC adds improved receive-packet filtering to support

SMBus-based manageability, as well as the ability to support transmit of SMBus-based

manageability packets. In addition, an ASF-compliant TCO controller is integrated into the MAC

for reduced-cost basic ASF manageability.

Figure 2. Internal Architecture Block Diagram

2.3Integrated 10/100/1000Mbps PHY

The 82541(PI/GI/EI) contains an integrated 10/100/1000Mbps-capable Copper PHY. This PHY

communicates with the MAC controller using a standard GMII/MII interface internal to the

component to transfer transmit and receive data. A standard MDIO interface, accessible to

software via MAC control registers, is used to configure and monitor the PHY operation.

2.4System Interface

82541(PI/GI/EI) provides a 32-bit PCI 2.2 bus interface which is capable of up to 66 MHz

operation in conventional PCI mode. In conventional PCI systems with a dedicated I/O bus per

connector, this interface should provide sufficient bandwidth to support a sustained 1000 Mb/sec

transfer rate. 64 KB of on-chip buffering mitigates instantaneous receive bandwidth demands and

eliminates transmit under-runs by buffering the entire outgoing packet prior to transmission.

Networking Silicon — 82541(PI/GI/EI)

3.0

Signal Descriptions

3.1

Signal Type Definitions

The signals of the 82541(PI/GI/EI) controller are electrically defined as follows:

3.2PCI Bus Interface Signals (56)

When the Reset signal (RST#) is asserted, the 82541(PI/GI/EI) will not drive any PCI output or bi- directional pins. The Power Management Event signal (PME#) can be active by configuring manageability functions.

Name Definition

I Input. Standard input only digital signal.O Output. Standard output only digital signal.

Tri-state. Bi-directional tri-state digital input/output signal.

STS

Sustained Tri-state. An active low tri-state signal owned and driven by only one agent at a time. The agent that drives an STS pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving an STS signal any sooner than one clock after the previous owner tri-states it. A pull-up resistor is required to sustain the inactive state until another agent drives it, and must be provided by the central resource.OD

Open Drain. Wired-OR with other agents.

The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state.A Analog. PHY analog data signal.

Power. Power connection, voltage reference, or other reference connection.

82541(PI/GI/EI) — Networking Silicon

3.2.1PCI Address, Data and Control Signals (44)

Symbol Type Name and Function

AD[31:0]TS Address and Data. Address and data signals are multiplexed on the same PCI pins. A bus transaction includes an address phase followed by one or more data phases.

The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, a DWORD address. The 82541(PI/GI/EI) device uses little endian byte ordering.

During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24] contain the most significant byte (MSB).

C/BE#[3:0]TS Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/

BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data.

C/BE[0]# applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB).

PAR TS Parity. The Parity signal is issued to implement even parity across AD[31:0] and C/

BE#[3:0]. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase.

When the 82541(PI/GI/EI) controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases.

FRAME#STS Cycle Frame. The Frame signal is driven by the 82541(PI/GI/EI) device to indicate the beginning and length of a bus transaction.

While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phas e.

IRDY#STS Initiator Ready. Initiator Ready indicates the ability of the 82541(PI/GI/EI) controller (as a bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted.

During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541(PI/GI/EI) controller drives IRDY# when acting as a master and samples it when acting as a slave.

TRDY#STS Target Ready. The Target Ready signal indicates the ability of the 82541(PI/GI/EI) controller (as a selected device) to complete the current data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted.

During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541(PI/GI/EI) device drives TRDY# when acting as a slave and samples it when acting as a master.

STOP#STS Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82541(PI/GI/EI) controller drives STOP# to request the bus master to stop the transaction. As a master, the 82541(PI/GI/EI) controller receives STOP# from the slave to stop the current transaction.

Networking Silicon — 82541(PI/GI/EI)

3.2.2Arbitration Signals (2)

3.2.3Interrupt Signal (1)

3.2.4System Signals (4)

IDSEL

Initialization Device Select. The Initialization Device Select signal is used by the

82541(PI/GI/EI) as a chip select signal during configuration read and write transactions. DEVSEL#STS

Device Select. When the Device Select signal is actively driven by the 82541(PI/GI/EI), it signals the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.

VIO P

VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage.

Note: VIO should be connected to 3.3 V Aux or 5 V Aux in order to be compatible with the pull-up clamps specification.

Symbol Type Name and Function

REQ#TS Request Bus. The Request Bus signal is used to request control of the bus from the arbiter. This signal is point-to-point.

GNT#

Grant Bus. The Grant Bus signal notifies the 82541(PI/GI/EI) that bus access has been granted. This is a point-to-point signal.

Symbol Type Name and Function

INTA#

Interrupt A. Interrupt A is used to request an interrupt of the 82541(PI/GI/EI). It is an active low, level-triggered interrupt signal.

Symbol

Type

Name and Function

CLK I

PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and is an input to the 82541(PI/GI/EI) device. All other PCI signals, except the Interrupt A (INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other timing parameters are defined with respect to this edge.

M66EN I

66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz.RST#I

PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the Power Management Event signal (PME#), are floated and all input signals are ignored. The PME# context is preserved, depending on power management settings.Most of the internal state of the 82541(PI/GI/EI) is reset on the de-assertion (rising edge) of RST#.

CLK_RUN#

I/O OD

Clock Run. This signal is used by the system to pause the PCI clock signal. It is used by the 82541(PI/GI/EI) controller to request the PCI clock. When the CLK_RUN# feature is disabled, leave this pin unconnected.

Symbol Type Name and Function

82541(PI/GI/EI) — Networking Silicon

3.2.5Error Reporting Signals (2)

3.2.6Power Management Signals (3)

3.2.7SMB Signals (3)

Note:If the SMB is disconnected, then an external pull-up resistor should be used for these pins.

Symbol Type Name and Function

SERR#

System Error. The System Error signal is used by the 82541(PI/GI/EI) controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error.

PERR#STS

Parity Error. The Parity Error signal is used by the 82541(PI/GI/EI) controller to report data parity errors during all PCI transactions except by a Special Cycle. PERR# is

sustained tri-state and must be driven active by the 82541(PI/GI/EI) controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present.

Symbol Type Name and Function

LAN_

PWR_GOOD

Power Good (Power-on Reset). The LAN_PWR_GOOD signal is used to indicate that stable power is available for the 82541(PI/GI/EI). When the signal is low, the 82541(PI/GI/EI) holds itself in reset state and floats all PCI signals.

PME#OD

Power Management Event. The 82541(PI/GI/EI) device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b.

AUX_PWR I

Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82541(PI/GI/EI) device should support the D3cold power state.

Symbol Type Name and Function

SMBCLK TS OD SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface.

SMBDATA TS OD SMB Data. The SMB Data signal is an open drain signal for serial SMB interface.

SMB_ALERT#/LAN_PWR_GOOD

TS OD

Multiplexed pin: SMB Alert, LAN Power Good. The SMB_ALERT# signal is open drain for serial SMB interface. The signal acts as an interrupt pin of a slave device on the SMBUS in TCO mode. (82559 mode). In ASF mode, this signal acts as LAN_PWR_GOOD input.

Networking Silicon — 82541(PI/GI/EI)

3.3EEPROM and Serial FLASH Interface Signals (9)

3.4

Miscellaneous Signals

3.4.1

LED Signals (4)

Symbol

Type

Name and Function

EEMODE I

EEPROM Mode. The EEPROM Mode pin is used to select the interface and

source of the EEPROM used to initialize the device. For a MIcrowire* EEPROM on the standard EEPROM pins, tie this pin to ground with a 1 K ? pull-down resistor (for the 82541PI, use a 100 ? pull-down resistor instead). For an Serial Peripheral Interface (SPI*) EEPROM attached to the Flash memory pins, leave this pin unconnected.

EEDI O EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device.

EEDO I EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. EEDO includes an internal pull-up resistor.

EECS

EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device.

EESK O EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the EEPROM interface, which is approximately 1 MHz for Microwire* and 2 MHz for SPI.

FLSH_CE#O FLASH Chip Enable Output. Used to enable FLASH device.

FLSH_SCK O FLASH Serial Clock Output. The clock rate of the serial FLASH interface is approximately 1 MHz.

FLSH_SI

FLASH Serial Data Input. This pin is an output to the memory device.

FLSH_SO/

LAN_DISABLE#

FLASH Serial Data Output / LAN Disable. This pin is an input from the FLASH memory. Alternatively, the pin can be used to disable the LAN port from a system GP (General Purpose) port. If the 82541(PI/GI/EI) is not using Flash functionality, the pin should be connected to external pull-up resistor.

If this pin is used as LAN_DISABLE#, the device goes to low power state and the LAN port is disabled when the pin is sampled low on rising edge of PCI reset.

Symbol Type Name and Function

LED0 / LINK_UP#O LED0 / LINK Up. Programmable LED indication. Defaults to indicate link connectivity.

LED1 / ACTIVITY#O LED1 / Activity. Programmable LED indication. Defaults to flash to indicate transmit or receive activity.

LED2 / LINK100#O LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at 100 Mbps.

LED3 / LINK1000#

LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at 1000 Mbps.

82541(PI/GI/EI) — Networking Silicon

3.4.2Other Signals (4)

3.5

PHY Signals

3.5.1

Crystal Signals (2)

Note:

The 82541 clock input circuit is optimized for use with an external crystal. However, an oscillator may also be used in place of the crystal with the proper design considerations. The 82540EP/

82541(PI/GI/EI) & 825462EZ(EX) Dual Footprint Design Guide (AP-444) should be consulted for further details.

3.5.2Analog Signals (10)

Symbol

Type

Name and Function

SDP[3:0]TS

Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power-up but may be configured differently by the EEPROM. The upper two bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals.

Symbol Type Name and Function

XTAL1I Crystal One. The Crystal One pin is a 25 MHz +/- 30 ppm input signal. It should be connected to a crystal, and the other end of the crystal should be connected to XTAL2.XTAL2

Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.

Symbol

Type

Name and Function

MDI[0]+/-A

Media Dependent Interface [0].

1000BASE-T : In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X configuration, MDI[0]+/- corresponds to BI_DB+/-.

100BASE_TX : In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair.

10BASE-T : In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair.MDI[1]+/-A

Media Dependent Interface [1].

1000BASE-T : In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X configuration, MDI[1]+/- corresponds to BI_DA+/-.

100BASE_TX : In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair.

10BASE-T : In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair.MDI[2]+/-A

Media Dependent Interface [2].

1000BASE-T : In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X configuration, MDI[2]+/- corresponds to BI_DD+/-.100BASE_TX : Unused.10BASE-T : Unused.

Networking Silicon — 82541(PI/GI/EI)

3.6Test Interface Signals (6)

3.7

Power Supply Connections

3.7.1

Digital and Analog Supplies

MDI[3]+/-A

Media Dependent Interface [3].

1000BASE-T : In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDI-X configuration, MDI[3]+/- corresponds to BI_DD+/-.100BASE_TX : Unused.10BASE-T : Unused.

IEEE_TEST-A IEEE test pin output minus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing.

IEEE_TEST+

Analog test pin output plus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing.

Symbol

Type Name and Function

TEST I Test Enable. Enables test mode.Normal mode: connect to VSS.JTAG_TCK I JTAG Test Access Port Clock. JTAG_TDI I JTAG Test Access Port Data In. JTAG_TDO O JTAG Test Access Port Data Out. JTAG_TMS

JTAG Test Access Port Mode Select.

JTAG_TRST#I

JTAG Test Access Port Reset. This is an active low reset signal for JTAG. To disable the JTAG interface, this signal should be terminated using pull-down resistor (1 K ? for the 82541GI(EI) and 100 ? for the 82541PI) to ground. It must not be left unconnected.

Symbol Type Name and Function

3.3V

P 3.3 V I/O Power Supply. ANALOG_1.8V P 1.8 V Analog Power Supply.

CLKR_1.8V P 1.8 V analog power supply for the clock recovery. XTAL_1.8V P Input power for the XTAL regulator.

1.2V

P 1.2 V Power supply. For analog and digital circuits.ANALOG_1.2V P 1.2 V Analog Power Supply. PLL_1.2V

Input power for the ICS regulator.

82541(PI/GI/EI) — Networking Silicon

3.7.2Grounds, Reserved Pins and No Connects

3.7.3Voltage Regulation Control Signals (2)

Symbol Type Name and Function

VSS P Ground.

AVSS P Shared analog Ground.

RSVD_VSS

Reserved Ground. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to ground.

RSVD_NC P Reserved No connect. This pin is reserved by Intel and may have factory test functions. For normal operation, do not connect any circuit to these pins. Do not connect pull-up or pull-down resistors.

No Connect. This pin is not connected internally.

Symbol

Type

Name and Function

CTRL12A

1.2 V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.2 V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external regulator.

CTRL18A

1.8 V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.8 V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external regulator.

Networking Silicon — 82541(PI/GI/EI)

4.0

Voltage, Temperature, and Timing Specifications

4.1

Absolute Maximum Ratings

4.2

Targeted Recommended Operating Conditions

4.2.1

General Operating Conditions

Table 1. Absolute Maximum Ratings a

a.Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are

exceeded. These values should not be used as the limits for normal device operations.

Symbol Parameter

Min Max Unit VDD (3.3)DC supply voltage on 3.3 V pins with respect to VSS

VSS - 0.5 4.6

V VDD (1.8)DC supply voltage on 1.8 V pins with respect to VSS

VSS - 0.5 2.5 or

VDD (1.8) + 0.5b b.The maximum value is the lesser value of 2.5 V or VDD (2.5) + 0.5 V. This specification applies to biasing the device to a

steady state for an indefinite duration.

V VDD (1.2)DC supply voltage on 1.2 V pins with respect to VSS VSS - 0.5 1.7 or

VDD (1.2) + 0.5c

c.The maximum value is the lesser value of 1.7 V or VDD (2.5) + 0.5 V.V VDD DC supply voltage VSS - 0.5 4.6V VI / VO Input voltage VSS - 0.5

4.6d d.The maximum value must also be less than VIO.

V IO Output current

40mA TSTG

Storage temperature range -40125

°C

ESD per MIL_STD-883 Test

Method 3015, Specification 2001V Latchup Over/Undershoot: 150 mA, 125 C

VDD overstress: VDD (3.3) * (7.2 V)

Table 2. Recommended Operating Conditions (Sheet 1 of 2)a

Symbol Parameter

Min Max Unit VDD (3.3)DC supply voltage on 3.3 V pins 3.0 3.6V VDD (1.8)DC supply voltage on 1.8 V pins 1.71b 1.89c V VDD (1.2)DC supply voltage on 1.2 V pins 1.14d 1.26e V VIO PCI bus reference voltage 3.0 5.25V tR / tF

Input rise/fall time (normal input)

200

82541(PI/GI/EI) — Networking Silicon

4.2.2

Voltage Ramp and Sequencing Recommendations

Note:

In any case or time period (greater than 1 ns), the supply voltage should comply with 3.3 V > 1.8 V > 1.2V . This is important to avoid stress in the ESD protection circuits. After 3.3 V reaches 10% of its final value, all voltage rails (1.8 V and 1.2 V) have 150 ms to reach their final operating values.

tr/tf input rise/fall time (Schmitt input)010ms T A Operating temperature range (ambient)

70°C T J

Junction temperature

≤125

°C

a.Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating

limits, might result in permanent damage.

b.The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is

1.67 V.

c.The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is

1.926 V.

d.The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is

1.12 V.

e.The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the maximum value is

1.284 V.

Table 3. 3.3V Supply Voltage Ramp

Parameter Description

Min Max Unit Rise Time Time from 10% to 90% mark 0.1

100ms Monotonicity Voltage dip allowed in ramp

0mV Slope Ramp rate at any time between 10% to 90%28800V/s Operational Range Voltage range for normal operating conditions 3 3.6V Ripple Maximum voltage ripple at a bandwidth equal to 50 MHz

70mV Overshoot

Maximum voltage allowed

Table 4. 1.8V Supply Voltage Ramp

Symbol Parameter

Min Max Unit Rise Time Time from 10% to 90% mark 0.1

100ms Monotonicity Voltage dip allowed in ramp

0mV Slope Ramp rate at any time between 10% to 90%57600V/s Operational Range Voltage range for normal operating conditions 1.71 1.89V Ripple Maximum voltage ripple at frequency below 1 MHz

280

mV pk-to-pk

Ripple Minimum voltage ripple at frequency below 1 MHz

1.55

V Overshoot

Maximum voltage allowed

2.2

Table 2. Recommended Operating Conditions (Sheet 2 of 2)a

Symbol Parameter

Min Max Unit