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LT1247中文资料

Current Mode PWM and DC/DC Converter

FEEDBACK

COMPENSATION

I SENSE

R T /C T

V CC

GND OUTPUT

V REF D U

ESCRIPTIO

FEATURE U S

A O

PPLICATI

s Current Mode Operation to 1MHz s 30ns Current Sense Delay s < 250μA Low Start-Up Current

s Current Sense Leading Edge Blanking s Pin Compatible with UC1842

s Undervoltage Lockout with Hysteresis s No Cross-Conduction Current s Trimmed Bandgap Reference s 1A Totem Pole Output

s Trimmed Oscillator Frequency and Sink Current s

Active Pull-Down on Reference and Output During Undervoltage Lockout

18V High Level Output Clamp

s Off-Line Converters s

DC/DC Converters

The LT ?1246/LT1247 are 8-pin, fixed frequency, current mode, pulse width modulators. These devices are de-signed to be improved plug compatible versions of the industry standard UC1842 PWM circuit. The LT1246/LT1247 are optimized for off-line and DC/DC converter applications. They contain a temperature compensated reference, high gain error amplifier, current sensing com-parator, and a high current totem pole output stage ideally suited to driving power MOSFETs. Start-up current has been reduced to less than 250μA. Cross-conduction cur-rent spikes in the totem pole output stage have been eliminated, making 1MHz operation practical. Several new features have been incorporated. Leading edge blanking has been added to the current sense comparator. This minimizes or eliminates the filter that is normally required.Eliminating this filter allows the current sense loop to operate with minimum delays. Trims have been added to the oscillator circuit for both frequency and sink current,and both of these parameters are tightly specified. The output stage is clamped to a maximum V OUT of 18V in the on state. The output and the reference output are actively pulled low during under-voltage lockout.

BLOCK Minimum Start-Up Operating Maximum Device Threshold Voltage Duty Cycle Replaces LT124616V 10V 100%UC1842LT1247

8.4V

7.6V

100%

UC1843

LT1246/LT1247

PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Section Output Voltage I O = 1mA, T J = 25°C 4.925

5.000 5.075V Line Regulation 12V < V CC < 25V q 320mV Load Regulation 1mA < I REF < 20mA q

–6–25mV Temperature Stability 0.1

mV/°C

Total Output Variation Line, Load, Temperature q 4.87

5.13

V Output Noise Voltage 10Hz < F < 10kHz, T J = 25°C 50μV Long-Term Stability T A = 125°C, 1000 Hrs.

25mV Output Short-Circuit Current q –30–90–180mA Oscillator Section Initial Accuracy R T = 10k, C T = 3.3nF, T J = 25°C 47.55052.5kHz R T = 6.2k, C T = 500pF, T J = 25°C 465

500535kHz Voltage Stability 12V < V CC < 25V, T J = 25°C 1

%Temperature Stability T MIN < T J < T MAX –0.05%/°C Amplitude

Pin 4

1.7

Clock Ramp Reset Current V OSC (Pin 4) = 2V, T J = 25°C

7.98.28.5mA Error Amplifier Section Feedback Pin Input Voltage V PIN 1 = 2.5V q 2.42 2.50 2.58V Input Bias Current V FB = 2.5V q –2

μA Open-Loop Voltage Gain 2 < V O < 4V q

6590dB Unity-Gain Bandwidth T J = 25°C 12

MHz Power Supply Rejection Ratio 12V < V CC < 25V

q 60dB Output Sink Current V PIN 2 = 2.7V, V PIN 1 = 1.1V q 26mA Output Source Current

V PIN 2 = 2.3V, V PIN 1 = 5V

q –0.5

–0.75mA

(Notes 1, 2)

ELECTRICAL C C HARA TERISTICS W U

PACKAGE/ORDER I FOR ATIO

A U G W

A W U

W A R BSOLUTE

XI TI S

Supply Voltage ....................................................... 25V Output Current...................................................... ±1A*Output Energy (Capacitive Load per Cycle)............. 5μJ Analog Inputs (Pins 2, 3).............................. –0.3 to 6V Error Amplifier Output Sink Current..................... 10mA Power Dissipation at T A ≤ 25°C............................... 1W Operating Junction Temperature Range

LT1246C/LT1247C ............................. 0°C to 100°C Storage Temperature Range................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C

*The 1A rating for output current is based on transient switching requirements.

Consult factory for Industrial and Military grade parts.

LT1246/LT1247 ELECTRICAL C C

HARA TERISTICS(Notes 1, 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS Error Amplifier Section

Output Voltage High Level V PIN2 = 2.3V, R L = 15k to GND q5 5.6V Output Voltage Low Level V PIN2 = 2.7V, R L = 15k to Pin 8q0.2 1.1V Current Sense Section

Gain q 2.85 3.00 3.15V/V Maximum Current Sense Input Threshold V PIN 3 < 1.1V q0.90 1.00 1.10V Power Supply Rejection Ratio70dB Input Bias Current q–1–10μA Delay to Output30ns Blanking Time60ns Blanking Override Voltage 1.5V Output Section

Output Low Level I OUT = 20mA q0.250.4V

I OUT = 200mA q0.75 2.2V Output High Level I OUT = 20mA q12.0V

I OUT = 200mA q11.75V Rise Time C L = 1nF, T J = 25°C3070ns Fall Time C L = 1nF, T J = 25°C2060ns Output Clamp Voltage I O = 1mA q1819V Undervoltage Lockout

Start-Up Threshold LT1246q151617V

LT1247q7.88.49.0V Minimum Operating Voltage LT1246q9.01011V

LT1247q7.07.68.2V Hysteresis LT1246q 5.5 6.0V

LT1247q0.40.8V PWM

Maximum Duty Cycle T J = 25°C94100% Minimum Duty Cycle T J = 25°C0% Total Device

Start-Up Current q170250μA Operating Current q1320mA

The q denotes those specifications which apply over the full operating temperature range.

Note 1: Unless otherwise specified, V CC = 15V, R T = 10k, C T = 3.3nF.Note 2: Low duty cycle pulse techniques are used during test to maintain junction temperature close to ambient.

LT1246/LT1247

C C HARA TERISTICS

U W

A TYPICAL PERFOR CE LT1246 Undervoltage Lockout

LT1247 Undervoltage Lockout

Start-Up Current

Oscillator Sink Current

Reference Short-Circuit Current

Reference Voltage

TEMPERATURE (°C)

–50

V C C (V )

–25

2575

125

LT1246 ? TPC01

050100

TEMPERATURE (°C)

–506

V C C (V )

–25

2575125

1247 TPC02

050100TEMPERATURE (°C)

–500

S T A R T -

U P C U R R E N T (μA )

4080120160200–25

2575125

LT1246 ? TPC03

050100180

1401006020

TEMPERATURE (°C)

–50–10

F R E Q U E

N C Y C H A N G E (%)

–6–22610–25

2575125

LT1246 ? TPC06

050100–8

–4048

Start-Up Current

Supply Current

Oscillator Frequency

TEMPERATURE (°C)

–50

I C C (m A )

1415

–2525

125

LT1246 ? TPC05

100

V CC (V)

0S T A R T -U P C U

R R E N T (μA )

100

150

200

1246/7 TPC04

146

16 TEMPERATURE (°C)

–507.7

O S C I L L A T O R S I

N K C U R R E N T (m A )

8.7

–25

2575

125

LT1246 ? TPC07

050100

7.8

8.08.28.48.68.57.98.18.3TEMPERATURE (°C)

–5020

R E F E R E N C E S H O

R T -C I R C U I T C U R R E N T (m A )

140–25

125

LT1246 ? TPC08

100

408010012060TEMPERATURE (°C)

–504.95

R E F E R E N

C E V O L T A G E (V )

5.05–25

2575125

LT1246 ? TPC09

0501004.96

5.005.014.974.984.995.025.035.04

LT1246/LT1247

C C HARA TERISTICS

U W

A TYPICAL PERFOR CE High Level Output Feedback Pin Input Voltage

Current Sense Clamp Voltage

Saturation Voltage

Low Level Output Low Level Output Saturation Voltage Supply Current vs Saturation Voltage

During Undervoltage Lockout

Oscillator Frequency

OUTPUT SOURCE CURRENT (mA)

O U T P U T S A T U R A T I O N V O L T A G E (V )

4.0200

LT1246 ? TPC12

0.52.02.51.01.53.03.5

100

Error Amplifier Open-Loop Gain and Phase

Current Sense Input Threshold

TEMPERATURE (°C)

–502.45

F E E D B A C K P I N I N P U T V O L T A

G E (V )

2.55

–25

125

LT1246 ? TPC10

100

2.462.502.512.472.482.492.522.532.54

TEMPERATURE (°C)

–500.95

C U R R E N T S E N S E C L A M P V O L T A G E (V )

1.05–25

125

LT1246 ? TPC11

100

0.961.001.010.970.980.991.021.031.04

OSCILLATOR FREQUENCY (Hz)

10k

9S U P P L Y C U R R E N T (m A )

1314

100k

LT1246 ? TPC15

OUTPUT SINK CURRENT (mA)

O U T P U T S A T U R A T I O N V O L T A G E (V )

LT1246 ? TPC14

OUTPUT SINK CURRENT (mA)

O U T P U T S A T U R A T I O N V O L T A G E (V )

1.0

100

200

LT1246 ? TPC13

0.5

FREQUENCY (Hz)

10–20

A V O L , O P E N L O O P V O L T A G E G A I N (d

B )

100

10k 10M

LT1246 ? TPC16

400206080100

1k 100k 1M PHASE (DEGREES)

ERROR AMP OUTPUT VOLTAGE (V)

C U R R E N T S E N S E I N P U T T H R E S H O L

D (V )

1.2

LT1246 ? TPC17

0.60.20.40.8

1.01245

LT1246/LT1247

C C HARA TERISTICS

U W

A TYPICAL PERFOR CE Timing Resistor vs Oscillator Frequency

I SENSE (Pin 3): Current Sense. This is the input to the current sense comparator. The trip point of the compara-tor is set by, and is proportional to, the output voltage of the Error Amplifier.

R T /C T (Pin 4) : The oscillator frequency and the deadtime are set by connecting a resistor (R T ) from V REF to R T /C T and a capacitor (C T ) from R T /C T to GND.

The rise time of the oscillator waveform is set by the RC time constant of R T and C T . The fall time, which is equal to the output deadtime, is set by a combination of the RC time constant and the oscillator sink current (8.2mA typ.).

COMP (Pin 1): Compensation Pin. This pin is the output of the Error Amplifier and is made available for loop compen-sation. It can also be used to adjust the maximum value of the current sense clamp voltage to less than 1V. This pin can source a minimum of 0.5mA (0.8mA typ.) and sink a minimum of 2mA (4mA typ.)

FB (Pin 2): Voltage Feedback. This pin is the inverting input of the Error Amplifier. The output voltage is normally fed back to this pin through a resistive divider. The noninverting input of the Error Amplifier is internally committed to a 2.5V reference point.

PI U

FU U C U S

O TI OSCILLATOR FREQUENCY (Hz)

10k

1T I M I N G R E S I S T O R (k ?)

100

100k

LT1246 ? TPC19

O U T P U T V O L T A G E

V CC = 15V TIME 50ns/DIV

C L = 1nF

1246/7 G20

V CC = 15V TIME 50ns/DIV

C L = 1nF

1246/7 G21

C U R

R E N

T S E N S E I N P U T 1V /D I V

O U T P U T V O L T A G E 5V /D I V

Output Rise and Fall Time

Current Sense Delay Output Cross-Conduction

O U T P U T V O L T A G E 5V /D I V

O U T P U T C R O S S -C O N D U C T I O N C U R R E N T 20m A /D I V

V CC = 15V TIME 50ns/DIV

C L = 15pF

1246/7 G22

Output Deadtime vs Oscillator Frequency

OSCILLATOR FREQUENCY (kHz)

0D E A D T I M E (%)

2030

405060

100

1000

LT1246 ? TPC18*

LT1246/LT1247

GND (Pin 5): Ground.

OUTPUT (Pin 6): Current Output. This pin is the output of a high current totem pole output stage. It is capable of driving up to ±1A of current into a capacitive load such as the gate of a MOSFET.

V CC (Pin 7): Supply Voltage. This pin is the positive supply of the control IC.

V REF (Pin 8): Reference. This is the reference output of the IC. The reference output is used to supply charging current to the external timing resistor R T . The reference provides biasing to a large portion of the internal circuitry, and is used to generate several internal reference levels includ-ing the V FB level and the current sense clamp voltage.

PI U

FU U C U S

U S A O

PPLICATI

W U

U I FOR ATIO

deadtime at that frequency. Curves of oscillator frequency and deadtime for various values of R T and C T appear in the Typical Performance Characteristics section. Frequency and deadtime can also be calculated using the following formulas:

Oscillator Rise Time: t r = 0.583 ? RC

Oscillator Discharge Time:Oscillator Period: t OSC = t r + t d

Oscillator Frequency:Maximum Duty Cycle:The above formulas will give values that will be accurate

to approximately ±5%, at the oscillator, over the full operating frequency range. This is due to the fact that the oscillator trip levels are constant versus frequency and the discharge current and initial oscillator frequency are trimmed. Some fine adjustment may be required to achieve more accurate results. Once the final R T /C T combination is selected, the oscillator characteristics will be repeatable from device to device. Note that there will be some slight differences between maximum duty cycle at the oscillator and maximum duty cycle at the output due to the finite rise and fall times of the output.Error Amplifier

The LT1246/LT1247 contain a fully compensated error amplifier with a DC gain of 90dB and a unity-gain fre-quency of 2MHz. Phase margin at unity-gain is 80°. The noninverting input is internally committed to a 2.5V refer-ence point derived from the 5V reference of pin 8. The

Minimum Start-Up Operating Maximum Device Threshold Voltage Duty Cycle Replaces LT124616V 10V 100%UC1842LT1247

8.4V

7.6V

100%

UC1843

Oscillator

The LT1246/LT1247 are fixed frequency current mode pulse width modulators. The oscillator frequency and the oscillator discharge current are both trimmed and tightly specified to minimize the variations in frequency and deadtime. The oscillator frequency is set by choosing a resistor and capacitor combination, R T and C T . This RC combination will determine both the frequency and the maximum duty cycle. The resistor R T is connected from V REF (pin 8) to the R T /C T pin (pin 4). The capacitor C T is connected from the R T /C T pin to ground. The charging current for C T is determined by the value of R T . The discharge current for C T is set by the difference between the current supplied by R T and the discharge current of the LT1246/LT1247. The discharge current of the device is trimmed to 8.2mA. For large values of R T discharge time will be determined by the discharge current of the device and the value of C T . As the value of R T is reduced it will have more effect on the discharge time of C T . During an oscil-lator cycle capacitor C T is charged to approximately 2.8V and discharged to approximately 1.1V. The output is enabled during the charge time of C T and disabled, in an off state, during the discharge time of C T . The deadtime of the circuit is equal to the discharge time of C T . The maximum duty cycle is limited by controlling the deadtime of the oscillator. There are many combinations of R T and C T that will yield a given oscillator frequency, however there is only one combination that will yield a specific

t RC

R d =

??346001641173

...f t OSC OSC

D t t t t

t MAX r OSC OSC d

OSC ==?

LT1246/LT1247

U S A O

PPLICATI

W U U

I FOR ATIO

inverting input (pin 2) and the output (pin 1) are made available to the user. The output voltage in a regulator circuit is normally fed back to the inverting input of the error amplifier through a resistive divider. The output of the error amplifier is made available for external loop compensation. The output current of the error amplifier is limited to approximately 0.8mA sourcing and approxi-mately 6mA sinking.

In a current mode PWM the peak switch current is a function of the output voltage of the error amplifier. In the LT1246/LT1247 the output of the error amplifier is offset by two diodes (1.4V at 25°C), divided by a factor of three,and fed to the inverting input of the current sense com-parator. For output voltages less than 1.4V the duty cycle of the output stage will be zero. The maximum offset that can appear at the current sense input is limited by a 1V clamp. This occurs when the error amplifier output reaches 4.4V at 25°C. The output of the error amplifier can be clamped below 4.4V in order to reduce the maximum voltage allowed across the current sensing resistor to less than 1V. The supply current will increase by the value of the output source current when the output voltage of the error amplifier is clamped.

Current Sense Comparator and PWM Latch

LT1246/LT1247 are current mode controllers. Under nor-mal operating conditions the output (pin 6) is turned on at the start of every oscillator cycle, coincident with the rising edge of the oscillator waveform. The output is then turned off when the switch current reaches a threshold level proportional to the error voltage at the output of the error amplifier. Once the output is turned off it is latched off until the start of the next cycle. The peak switch current is thus proportional to the error voltage and is controlled on a cycle by cycle basis. The peak switch current is normally sensed by placing a sense resistor in the source lead of the output MOSFET. This resistor converts the switch current to a voltage that can be fed into the current sense input. For normal operating conditions the peak inductor current,which is equal to the peak switch current, will be equal to:

I V V

R PK

PIN S

?()

()

1143.During fault conditions the maximum threshold voltage at

the input of the current sense comparator is limited by the internal 1V clamp at the inverting input. The peak switch current will be equal to:

I V

R PK MAX S

()=

10.In certain applications such as high power regulators it may be desirable to limit the maximum threshold voltage to less than 1V in order to limit the power dissipated in the sense resistor or to limit the short-circuit current of the regulator circuit. This can be accomplished by clamping the output of the error amplifier. A voltage level of approximately 1.4V at the error amplifier output will give a threshold voltage of 0V. A voltage level of approximately 4.4V at the output of the error amplifier will give a thresh-old level of 1V. Between 1.4V and 4.4V the threshold voltage will change by a factor of one third of the change in the error amplifier output voltage. The threshold voltage will be 0.333V for an error amplifier voltage of 2.4V. To reduce the maximum current sense threshold to less than 1V the error amplifier output should be clamped to less than 4.4V.Blanking

A unique feature of the LT1246/LT1247 is the built-in blanking circuit at the output of the current sense com-parator. A common problem with current mode PWM circuits is erratic operation due to noise at the current sense input. The primary cause of noise problems is the leading edge current spike due to transformer interwinding capacitance and diode reverse recovery time. This current spike can prematurely trip the current sense comparator causing an instability in the regulator circuit. A filter at the current sense input is normally required to eliminate this instability. This filter will in turn slow down the current sense loop. A slow current sense loop wil increase the minimum pulse width which will increase the short-circuit current in an overload condition. The LT1246/LT1247blank (lock out) the signal at the output of the current sense comparator for a fixed amount of time after the switch is turned on. This prevents the PWM latch from tripping due to the leading edge current spike. The blank-ing time will be a function of the voltage at the feedback pin (pin 2). The blanking time will be 60ns for normal operat-

LT1246/LT1247

U S A O

PPLICATI W U U

I FOR ATIO

collector of the lower transistor, which is n-type silicon,forms a p-n junction with the substrate of the device. The substate of the device is tied to ground. This junction is reverse biased during normal operation. In some applica-tions the parasitic LC of the external MOSFET gate can ring and pull the output pin below ground. If the output pin is pulled negative by more than a diode drop, the parasitic diode formed by the collector of the output NPN and the substrate will turn on. This can cause erratic operation of the device. In these cases a Schottky clamp diode is recommended from output to ground.Reference

The internal reference of the LT1246/LT1247 is a 5V Bandgap reference, trimmed to within ±1% initial toler-ance. The reference is used to power the majority of the internal logic and the oscillator circuitry. The oscillator charging current is supplied from the reference. The feedback pin voltage and the clamp level for the current sense comparator are derived from the reference voltage.The reference can supply up to 20mA of current to power external circuitry. Note that using the reference in this manner, as a voltage regulator, will significantly increase the power dissipation in the device, which will reduce the operating ambient temperature range.Design/Layout Considerations

LT1246/LT1247 are high speed circuits capable of gener-ating pulsed output drive currents of up to 1A peak. The rise and fall time for the output drive current is in the range of 10ns to 20ns. High Speed circuit layout techniques must be used to insure proper operation of the devices. Do not attempt to use Proto-boards or wire-wrap tech-niques to breadboard high speed switching regulator circuits. They will not work properly.

Printed circuit layouts should include separate ground paths for the voltage feedback network, oscillator capaci-tor, and switch drive current. These ground paths should be connected together directly at the ground pin (pin 5) of the LT1246/LT1247. This will minimize noise problems due to pulsed ground pin currents. V CC should be by-passed, with a minimum of 0.1μF, as close to the device as possible. High current paths should be kept short and they should be separated from the feedback voltage net-work with shield traces if possible.

ing conditions (V FB = 2.5V). The blanking time goes to zero as the feedback pin is pulled to 0V. This means that the blanking time will be minimized during start-up and also during an output short-circuit fault. This blanking circuit eliminates the need for an input filter at the current sense input except in extreme cases. Eliminating the filter allows the current sense loop to operate with minimum delays,reducing peak currents during fault conditions.Undervoltage Lockout

The LT1246/LT1247 incorporate an undervoltage lockout comparator which prevents the internal reference circuitry and the output from starting up until the supply voltage reaches the start-up threshold voltage. The quiescent current, below the start-up threshold, has been reduced to less than 250μA (170μA typ.). This minimizes the power loss due to the start-up resistor used in off-line converters.In undervoltage lockout both V REF (pin 8) and the Output (pin 6) are actively pulled low by Darlington connected PNP transistors. They are designed to sink a few milliamps of current and will pull down to about 1V. The pull-down transistor at the reference pin can be used to reset the external soft start capacitor. The pull-down transistor at the output eliminates the external pull-down resistor re-quired, with earlier devices, to hold the external MOSFET gate low during undervoltage lockout.Output

The LT1246/LT1247 incorporate a single high current totem pole output stage. This output stage is capable of driving up to ±1A of output current. Cross-conduction current spikes in the output totem pole have been elimi-nated. These devices are primarily intended for driving MOSFET switches. Rise time is typically 30ns and fall time is typically 20ns when driving a 1.0nF load. A clamp is built into the device to prevent the output from rising above 18V in order to protect the gate of the MOSFET switch. The output is actively pulled low during undervoltage lockout by a Darlington PNP. This PNP is designed to sink several milliamps and will pull the output down to approximately 1V. This active pull-down eliminates the need for the external resistor which was required in older designs.The output pin of the device connects directly to the emitter of the upper NPN drive transistor and the collector of the lower NPN drive transistor in the totem pole. The

LT1246/LT1247

Adjustable Clamp Level with Soft Start

Soft Start

External Clock Synchronization

LT1246 ? TA06

LT1246 ? TA07

V CLAMP ≈

1.67

R2 + 1

R1(

(

I PK (MAX) ≈

V CLAMP

R S

WHERE: O ≤ V CLAMP ≤ 1.0V

t SOFT START =

–ln 1 –

V C C R1 R2 3 ? V

CLAMP R1 + R2

LT1246 ? TA05

EXTERNAL SYNC INPUT

T U S

A O

PPLICATI

TYPICAL

LT1246/LT1247

Slope Compensation at I SENSE Pin

LT1246 ? TA08

Slope Compensation at Error Amp

LT1246 ? TA09

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

U S

A O

PPLICATI

TYPICAL

LT1246/LT1247

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487(408) 432-1900 q

FAX : (408) 434-0507 q

TELEX : 499-3977

? U

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

N8 0694

–0.381

8.255

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).

0.053 – 0.069 BSC

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).

N8 Package 8-Lead Plastic DIP

S8 Package 8-Lead Plastic SOIC

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