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HIP4086EVAL中文资料

FN4220.6

HIP4086

80V , 0.5A Three Phase Driver

The HIP4086 is a Three Phase Bridge N-Channel MOSFET driver IC. The HIP4086 is specifically targeted for PWM motor control. It makes bridge based designs simple and flexible. Like the HIP4081, the HIP4086 has a flexible input protocol for driving every possible switch combination. Unlike the HIP4081, the user can override the shoot-through

protection for switched reluctance applications. The HIP4086 has reduced drive current compared to the HIP4081 (0.5A vs 2.5A) and a much wider range of programmable dead times (0.25μs to 4.5μs) - like the HIP4082. The HIP4086 is suitable for applications requiring DC to 100kHz. Unlike the previous family members, the HIP4086 has a programmable undervoltage set point.

Also refer to the HIP4083, three phase upper only MOSFET driver, for a lower current solution optimized for smaller motors.

Pinout

HIP4086(PDIP , SOIC)TOP VIEW

Features

?Independently Drives 6 N-Channel MOSFETs in Three Phase Bridge Configuration ?Bootstrap Supply Max Voltage to 95VDC ?Bias Supply Operation from 7V to 15V ? 1.25A Peak T urn-Off Current

?User-Programmable Dead Time (0.25μs to 4.5μs)?Charge-Pump and Bootstrap Maintain Upper Bias Supplies ?Programmable Bootstrap Refresh Time

?Drives 1000pF Load with T ypical Rise Time of 20ns and Fall Time of 10ns ?DIS (Disable) Overrides Input Control

?Input Logic Thresholds Compatible with 5V to 15V Logic Levels ?Dead Time Disable Capability

?Programmable Undervoltage Set Point ?Pb-free available

Applications

?Brushless Motors ?AC Motor Drives

?Switched Reluctance Motor Drives ?Battery Powered Vehicles

Application Block Diagram

Ordering Information

PART NUMBER TEMP. RANGE (o C)PACKAGE PKG. DWG. #HIP4086AB*-40 to 12524 Ld SOIC M24.3HIP4086ABZ*(See Note)-40 to 12524 Ld SOIC (Pb-free)M24.3HIP4086AP -40 to 12524 Ld PDIP E24.3HIP4086APZ (See Note)

-40 to 125

24 Ld PDIP (Pb-free)

E24.3

*Add “-T” suffix to part number for tape and reel packaging.

NOTE:Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

123456789101112

161718192021222324151413AHB BHO BLO ALO BHS V DD AHS AHO CHO CHB

CLO CHS BHB BHI AHI BLI ALI V SS DIS RFSH CHI UVLO CLI RDEL 12V

80V

GND

GND HIP4086Data Sheet

July 2004

元器件交易网https://www.wendangku.net/doc/016127163.html,

Functional Block Diagram (1/3 of HIP4086 )

Typical Application (PWM Mode Switching)

TRUTH TABLE

INPUT

OUTPUT

ALI, BLI, CLI

AHI, BHI, CHI

UV DIS RDEL ALO, BLO, CLO

AHO, BHO, CHO

X X X 1X 00X X 1X X 001X 00>100mV

100000X 010

00X 001 0

<100mV

NOTE:X signifies that input can be either a “1” or “0”.

CHARGE PUMP

V DD DIS ALI UVLO

AHB

AHO AHS UV

208

10ns DELAY

10UNDERVOLTAGE DETECTOR RFSH 9

RFSH PULSE

4LEVEL SHIFTER TURN-ON DELAY

DRIVER

161718TURN-ON DELAY

V DD

ALO V SS

DRIVER

20216

DEAD TIME CURRENT MIRRORS

RDEL

2μs

DELAY

+-100mV +

-V SS

DEAD TIME DISABLE

80V

+12V

PWM INPUTS

C RFSH

R DIS

FROM OPTIONAL OVERCURRENT

LATCH

R DEL

3-PHASE LOAD

GND

12345678910111216171819202122232415

1413

BHB BHI

AHI BLI ALI V SS AHB BHO BLO ALO BHS V DD AHS AHO DIS

RFSH

CHI

UVLO CLI CHO CHB CLO CHS RDEL (OPTIONAL)

R UV

(OPTIONAL)

+12V

Pin Descriptions

NUMBER SYMBOL DESCRIPTION

16 1 13AHB

BHB

CHB

(xHB)

High-Side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin.

5 2 12AHI

BHI

CHI

(xHI)

High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO (Pin

17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the

dead time is disabled by connecting RDEL (Pin 7) to ground, the low side input of each phase will override the corresponding high side input on that phase - see Truth Table on previous page. If RDEL is tied to ground, dead time is disabled and the outputs follow the inputs. Care must be taken to avoid shoot-through in this application. DIS (Pin 10) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than V DD).

4 3 11ALI

BLI

CLI

(xLI)

Low-Side Logic Level Inputs. Logic at these three pins controls the three low side output drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL (Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than V DD).

6V SS Ground. Connect the sources of the Low-Side power MOSFETs to this pin.

7RDEL Dead Time Setting. Connect a resistor from this pin to V DD to set timing current that defines the dead time between drivers - see Figure 15. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees

no shoot-through by delaying the turn-on of all drivers. When RDEL is tied to V SS, both upper and lowers can

be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1μF

or smaller may be connected between RDEL and V SS.

8UVLO Undervoltage Setting. A resistor can be connected between this pin and V SS to program the undervoltage set point, see Figure 16. With this pin not connected, the undervoltage disable is typically 6.6V. When this pin is

tied to V DD, the undervoltage disable is typically 6.2V.

9RFSH Refresh Pulse Setting. An external capacitor can be connected from this pin to V SS to increase the length of the start up refresh pulse - see Figure 14. If this pin is not connected, the refresh pulse is typically 1.5μs.

10DIS Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other inputs.

With DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V

(no greater than V DD).

17 24 14AHO

BHO

CHO

(xHO)

High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase.

15 23 15AHS

BHS

CHS

(xHS)

High-Side Source Connection. Connect the sources of the High-Side power MOSFETs to these pins. The negative side of the bootstrap capacitors should also be connected to these pins.

20V DD Positive Supply. Decouple this pin to V SS (Pin 6).

21 22 19ALO

BLO

CLO

(xLO)

Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins.

NOTE:x = A, B and C.

Absolute Maximum Ratings Thermal Information

Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V DD +0.3V Voltage on xHS . . . . . . . . . -6V (T ransient) to 85V (-40o C to 150o C) Voltage on xHB . . . . . . . . . . . . . . . . . . . .V xHS -0.3V to V xHS +V DD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . V SS -0.3V to V DD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . .V xHS -0.3V to V xHB +0.3V Phase Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns Operating Conditions

Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V to +15V Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V xHS + V DD Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V Ambient T emperature Range. . . . . . . . . . . . . . . . . . -40o C to 125o C Junction Temperature Range. . . . . . . . . . . . . . . . . . -40o C to 150o C Thermal Resistance (T ypical, Note 1)θJA (o C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Storage T emperature Range. . . . . . . . . . -65o C to 150o C Maximum Junction T emperature . . . . . . . . . . . . . . . . . . . . . . .150o C Maximum Lead T emperature (Soldering 10s) . . . . . . . . . . . . .300o C (SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1.θJA is measured with the component mounted on an evaluation PC board in free air.

2.All voltages are relative to V SS unless otherwise specified.

3.x = A, B and C. For example, xHS refers to AHS, BHS and CHS.

Electrical Specifications V DD = V xHB = 12V, V SS = V xHS = 0V, R DEL = 20K, R UV = ∞, Gate Capacitance (C GA TE) = 1000pF

PARAMETER TEST CONDITIONS

T J = 25o C

T J = -40o C TO

150o C

UNITS MIN TYP MAX MIN MAX

SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION

V DD Quiescent Current xHI = 5V, xLI = 5V 2.7 3.4 4.2 2.1 4.3 mA V DD Operating Current f = 20kHz, 50% Duty Cycle 6.38.2510.5511mA xHB On Quiescent Current xHI = 0V-4080-100μA xHB Off Quiescent Current xHI = V DD 0.60.8 1.30.5 1.4mA xHB Operating Current f = 20kHz, 50% Duty Cycle0.70.9 1.3- 2.0mA Qpump Output Voltage No Load11.512.51410.514.5V Qpump Output Current V xHS = 12V, V xHB = 22V50100130-140μA xHB, xHS Leakage Current V xHS = 80V, V xHB = 93V72445-50μA V DD Rising Undervoltage Threshold R UV open 6.27.18.0 6.18.1V V DD Falling Undervoltage Threshold R UV open 5.75 6.67.5 5.67.6V Minimum Undervoltage Threshold R UV = V DD5 6.2 6.8 4.9 6.9V INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS

Low Level Input Voltage-- 1.0-0.8V High Level Input Voltage 2.5-- 2.7-V Input Voltage Hysteresis-35---mV Low Level Input Current V IN = 0V-60-100-135-55-140μA High Level Input Current V IN = 5V-1-+1-10+10μA GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO

Low Level Output Voltage (V OUT - V SS)I SINKING = 30mA-100--200mV Peak Turn-On Current V OUT = 0V0.30.50.7- 1.0A Peak Turn-Off Current V OUT = 12V0.7 1.1 1.50.5 1.7A

Switching Specifications V DD = V xHB = 12V, V SS = V xHS = 0V, C GA TE = 1000pF, R DEL = 10k

PARAMETER TEST CONDITIONS

T J = 25o C

T J = -40o C TO

150o C

UNITS MIN TYP MAX MIN MAX

TURN-ON DELAY AND PROPAGATION DELAY

Dead Time R DEL = 100K 3.8 4.5637μs

R DEL = 10K0.380.50.650.30.7μs Dead Time Channel Matching R DEL = 10K-715-20% Lower Turn-Off Propagation Delay

(xLI-xLO)

No Load-3045-65ns

Upper Turn-Off Propagation Delay

(xHI-xHO)

No Load-7590-100ns

Lower Turn-On Propagation Delay

(xLI-xLO)

No Load-4575-90ns Upper Turn-On Propagation Delay (xHI-xHO)No Load-6590-100ns Rise Time C GA TE = 1000pF-2040-50ns Fall Time C GA TE = 1000pF-1020-25ns Disable Turn-Off Propagation Delay

(DIS - Lower Outputs)

-5580-90ns

Disable Turn-Off Propagation Delay

(DIS - Upper Outputs)

-8090-100ns

Disable to Lower Turn-On Propagation Delay

(DIS - xLO)

-5580-100ns Disable to Upper Enable (DIS - xHO)R DEL = 10K, C RFSH Open- 2.0---μs Refresh Pulse Width (xLO)C RFSH Open- 1.5---μs

Timing Diagrams

FIGURE 1.

FIGURE 2.DISABLE FUNCTION

NOTES:

4.X means any “A”, “B”, or “C” phase.

5.With RDEL resistor tied to V DD , lowers and uppers cannot be turned on at the same time. Low side logic overrides high side logic unless RDEL < 100mV.

XLI

XHI

XLO

XHO

XLO XHO DEAD TIME

DEAD TIME

(R DEL = V SS )

LOWER LOWER UPPER UPPER (R DEL = V SS )

TURN-ON TURN-OFF

TURN-ON

TURN-OFF

DIS OR UV

XHI, XLI

XLO

XHO

DISABLE TO LOWER DISABLE TURN-OFF DISABLE TO UPPER

REFRESH TURN-ON PROP DELAY

PULSE WIDTH

PROP DELAY (UPPERS)

ENABLE

Typical Performance Curves

FIGURE 3.V DD SUPPLY CURRENT vs V DD SUPPLY VOLTAGE

FIGURE 4.V DD SUPPLY CURRENT vs SWITCHING

FREQUENCY

FIGURE 5.FLOATING I XHB BIAS CURRENT

FIGURE 6.OFF-STATE I XHB BIAS CURRENT

FIGURE 7.CHARGE PUMP OUTPUT CURRENT FIGURE 8.CHARGE PUMP OUTPUT VOLTAGE

-60

-40

-20

020406080100120

140

160

JUNCTION TEMPERATURE (o C)

V D D S U P P L Y C U R R E N T (m A )

V DD = 7V V DD = 8V V DD = 10V V DD = 12V

V DD = 15V V DD = 16V

ALL GATE CONTROL INPUTS = 5V

-60

-40-20

020406080100120140160

1015

JUNCTION TEMPERATURE (o C)

V D D S U P P L Y C U R R E N T (m A )

200kHz

C GATE = 1000pF

20kHz 50kHz

100kHz

10kHz

02040

60801001201401601802000

1000

2000

3000

4000SWITCHING FREQUENCY (kHz)

F L O A T I N

G B I A S C U R R E N T (μA )

C GATE = NO LOAD

C GATE = 1000pF

T J = 25o C

JUNCTION TEMPERATURE (o C)

-60

-40-20020406080100120140160

0.60.81.01.21.41.61.8

B I A S

C U R R E N T (m A )

V DD = 10V V DD = 12V

V DD = 15V

V DD = 7V

V DD = 8V -60

-40-20020406080100120140160

200

150

100

0JUNCTION TEMPERATURE (o C)O U T P U T C U R R E N T (μA )

V xHB - V xHS = 10V

-60

-40

-20

100

120

140

160

67891011121314JUNCTION TEMPERATURE (o C)

C H A R G E P U M P O U T P U T V O L T A G E (V )

V DD = 7V

V DD = 12V

V DD = 10V

V DD = 8V

V DD = 15V

FIGURE 9.AVERAGE TURN-ON CURRENT (0 TO 5V)

FIGURE 10.AVERAGE TURN-OFF CURRENT (V DD TO 4V)

FIGURE 11.RISE AND FALL TIMES (10-90%)FIGURE 12.PROPAGATION DELAY

FIGURE 13.DISABLE PIN PROPAGATION DELAY FIGURE 14.REFRESH TIME

-60

-40-20

020406080100120140160

00.2

0.40.6

0.8

JUNCTION TEMPERATURE (o C)

A V E R A G E T U R N -O N C U R R E N T (A )

C GATE = 1000pF

V DD = 15V

V DD

= 8V

V DD = 10V V DD = 12V V DD = 7V

-40-20

020406080100120140160

00.4

0.8

1.21.6

JUNCTION TEMPERATURE (o C)

A V E R A G E T U R N -O F F C U R R E N T (A )

C GATE = 1000pF

V DD = 15V

V DD = 8V V DD = 10V

V DD = 12V

V DD = 7V -60

-40-20

020406080100120140160

010

JUNCTION TEMPERATURE (o C)

R I S E A N D F A L L T I M E S (n s )

RISE

FALL

V DD = XHB-XHS = 12V, C GATE = 1000pF

-60

-40-20020406080100120140160

2040

100

JUNCTION TEMPERATURE (o C)

P R O P A G A T I O N D E L A Y (n s )

xHI to xHO

xLI to xLO

JUNCTION TEMPERATURE (o C)

-60

-40-20

020406080100120140160

10100

P R O P A G A T I O N D E L A Y (n s )

LOWER ENABLE TURN-ON

LOWER DISABLE TURN-OFF

UPPER DISABLE TURN-OFF

C RFSH (pF)

50100150

200250300350400450500

020

R E F R E S H T I M E (μs )

T J = 25o C

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Intersil Corporation’s quality certifications can be viewed at https://www.wendangku.net/doc/016127163.html,/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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FIGURE 15.DEAD TIME FIGURE 16.UNDERVOLTAGE THRESHOLD

FIGURE 17.I xHS LEAKAGE CURRENT

JUNCTION TEMPERATURE (o C)

-60

-40-20

020406080100120

140

160

D E A D T I M E (μs )

RDEL = 100k ?

RDEL = 10k ?

JUNCTION TEMPERATURE (o C)

U N D E R V O L T A G E S H U T D O W N /-60

-40

-20

020406080100120140160

66.5

77.588.599.51010.511E N A B L E V O L T A G E

ENABLE (50K, UVLO TO GND)

TRIP (50K, UVLO TO GND)

ENABLE (UVLO OPEN)

TRIP (UVLO OPEN)TRIP/ENABLE (0K, UVLO TO V DD )

JUNCTION TEMPERATURE (o C)

-60

-40-20

020406080100120140160

1015

L E A K A G E C U R R E N T (μA )

V xHS = 80V