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MSTM-S3-TR-99-077.76M中文资料

Application

The Connor-Winfield MSTM-S3-TR Simplified Control Timing Module acts as a complete system clock module for Stratum 3 timing applications in accordance with GR-1244, Issue 2 and GR-253, Issue 3.

Connor Winfield’s Stratum 3 timing modules helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design.Features

?5V Miniature Timing Module ?Redundant References

? 2 Synchronous Outputs Available From 8 kHz to 77.76MHz

?40 sec., Filtered, Hold Over History ?Operational Status

Flags

MSTM-S3-TR

Stratum 3

Timing Module

Bulletin TM027

Page 1 of 16

Revision P05

Date02 DEC 02

Issued By

General Description

The Connor-Winfield Stratum 3 Simplified Control Timing Mod-ule acts as a complete system clock module for general Stratum 3 timing applications. The MSTM is designed to replace similar units from TF Systems (TF118B) and Raltron (SY0001B).

Full external control input allows for selection and monitoring of any of four possible operating states: 1) Holdover, 2) External Reference #1, 3) External Reference #2, and 4) Free Run. Table #1 illustrates the control signal inputs and corresponding opera-tional states.

In the absence of External Control Inputs (A,B), the MSTM enters the Free Run mode and signals an External Alarm. The MSTM will enter other operating modes upon application of a proper control signal. Mode 1 operation (A=1, B=0) results in an output signal that is phase locked to the External Reference Input #1. Mode 2 operation (A=0, B=1) results in an output sig-nal that is phase locked to External Reference Input #2. Hold-over mode operation (A=1, B=1) results in an output signal at or near the frequency as determined by the latest (last) locked-signal input values and the holdover performance of the MSTM.Free Run ModeFree Run mode operation (A=0, B=0) is a guar-anteed output of 4.6 ppm of the nominal frequency.

Alarm signals are generated at the Alarm Output during Hold-over and Free Run operation. Alarm Signals are also generated by Loss-of-Lock and Loss-of-Reference conditions. A high level indicates an alarm condition. Real-time indication of the opera-tional mode is available at unique operating mode outputs on pins 1-4.

Control loop 0.1 Hz filters effectively attenuate any reference jitter, smooth out phase transients, comply with wander transfer and jitter tolerances.

Absolute Maximum Rating

Table 2

Symbol Parameter

Minimum Nominal

Maximum Units Notes V CC Power Supply Voltage -0.57.0Volts 1.0V I Input Voltage -0.5V CC + 0.5Volts 1.0T s

Storage Temperature

-55

100

deg. C

1.0

Functional Block Diagram

Figure 1

CNTL CNTL Operational

Ref 1Ref 2Hold Over

Free Run PLL Unlock

Alarm Out

A B Mode

00 Free Run (Default Mode)000101External Normal

1000001

Reference PLL_Unlock 100010#1 LOR 001001External Normal

01000001Reference PLL_Unlock 010010#2 LOR 0010011

Hold Over

Function Control Table

Table 1

NOTES:

1.0:Stresses beyond those listed under Absolute Maximum Rating may cause damage

to the device. Operation beyond Recommended Conditions is not implied.2.0:

Logic is 3.3V CMOS 3.0 GR-1244-CORE 3.2.1

Recommended Operating Conditions

Table 3

Symbol Parameter

Minimum Nominal Maximum Units Notes

V cc Power supply voltage 4.75 5.00

5.25Volts V TH Reset threshold voltage 4.25 4.5Volts V IH High level input voltage - TTL 2.0V CC Volts V IL Low level input voltage - TTL 0

0.8Volts t IN Input signal transition - TTL 250ns C IN Input capacitance 15pF V OH High level output voltage, 2.4 5.25Volts 2.0 I OH = -4.0mA, V CC = min.V OL Low level output voltage,0.4

Volts

I OL = 12.0 mA, V CC = min.t TRANS

Clock output transition time

4.0

ns t PULSE 8kHz input reference pulse 30ns width( positive or negative)T OP

Operating temperature

°C

Specifications

Table 4

Parameter

Specifications Notes

Frequency Range (Sync_Out)8 kHz to 77.76 MHz Frequency Range (Opt_Out)8 kHz to 77.76 MHz

Supply Current

250 mA typical, 400 mA during warm-up (Maximum)Timing Reference Inputs

8 kHz - 19.44 MHz

3.0Jitter, Wander and Phase Transient Tolerances GR-1244-CORE

4.2-4.4, GR-253-CORE

5.4.4.3.6Wander Generation GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2Wander Transfer GR-1244-CORE 5.4

Jitter Generation GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3Jitter Transfer GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1Phase Transients GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3Free Run Accuracy 4.6 ppm over T OP

Hold Over Stability

±0.37 ppm for initial 24 hrs 4.0

Inital Offset ±0.05 ppm Temperature ±0.28 ppm Drift

±0.04 ppm Maximum Hold Over History 40 seconds

Pull-in/ Hold-in Range ±13.8 ppm minimum 5.0Lock Time 30 seconds typical DPLL Bandwidth

< 0.1 Hz

4.0:Hold Over stability is the cumulative fractional frequency offset as described by GR-1244-CORE,

5.2

5.0:

Pull-in Range is the maximum frequency deviation from nominal clock rate on the

reference inputs to the timing module that can be overcome to pull into synchronization with the reference

Pin Description

Table 5

Pin #Connection Description

1Hold Over Indicator output. High output when Hold Over mode is selected by control pins. 2Ref 1Indicator output. High output when Ref 1 mode is selected by control pins.

3Ref 2Indicator output. High output when Ref 2 mode is selected by control pins.

4Free Run Indicator output. High output when Free Run mode is selected by control pins. 5GND Ground

6Alarm _Out Alarm output. High output if module is in Free Run, or Hold Over, or LOR.

7CNTL A Mode control input

8CNTL B Mode control input

9PLL_Unlock Indicates that the PLL is not locked to a reference.

10Tri-State/GND0 = Normal operation, 1= Tri-State. Pin is pulled low internally.

Ground pin for normal operation.

11Sync_Out Primary timing output signal. Signal is sychronized to reference.

12GND Ground

13Opt_Out Secondary output signal. Signal is derived from Sync_Out or from an internal

reference clock depending upon the choosen configuration.

14GND Ground

15Ex_Ref_2External Input Reference #2

16GND Ground

17Ex_Ref_1External Input Reference #1

18Vcc+5V dc supply

Typical Application

Figure 2

Typical System Test Set-up

Figure 3

Input Select

MUX MUX MUX

MUX

System Select

BITS System Signal

CW’s STM/MSTM module

CW’s SCG 2000/4000

S A

Timing Card #N

Line Card 1

Line Card N

(1.544 M H z ), E 1 ra te R Z w ith n o is e m o d u la tio T E K T R O N IX S J 300E

C lo c k o r B IT S c lo c k in p u t (T T e tc.)

H P 53310A

o d u la tio n A n a ly z e r / T im e In te rv a l A n a ly z T b re r A n a ly z e r d a ta (IE E E -488)

S J 300E

T im in g S o u r c e

MSTM-S3-TR Typical Current Draw

Figure 4

Typical Calibrated Wander Transfer TDEV Figure 5

Typical Wander Generation MTIE Figure 6

Typical Wander Generation TDEV Figure 7

Typical Phase Transient MTIE

Figure 9

1μs Phase Transient TIE

Figure 8

-200

200

400

600

800

1000

1200

Time (sec)

T I E (n s )

Entry Into Hold Over Figure 10

Return from Hold Over Figure 11

Loss of Reference Timing Diagram

Power on Reset Levels

Figure 14

Solder Clearance Figure 15

VIA KEEP OUT AREA:

It is recommended that there be no vias or feed throughs underneath the main body of the module between the pins. It is suggested that the traces in this area be kept to a minimum and protected by a layer of solder mask. See Figure 17.

SOLDER MASK:

A solder mask is recommended to cover most the top pad to avoid excessive solder underneath the shoulder of the pin to avoid rework damage. See Table 6 and Figure 18.

PAD CONSTRUCTION:

The recommended pad construction is shown in Figure 17. For the pin diameter of .040” a hole diameter of .055” is suggested for ease of insertion and rework. A pad diameter of .150” is also suggested for support. This leaves a spacing of .050” between the pads which is sufficient for most signal lines to pass through.

PAD ARRAY AND PAD SPACING:

The pins are arranged in a dual-in-line

configuration as shown in Figure 17. There is .2”space between the pins in-line and each line is separated by 1.6”. See Figures 16 & 17 and T able 6.

MECHANICAL OUTLINE:

The mechanical outline of the MSTM-S3-TR is shown in Figure 16. The board space required is 2” x 2”. The pins are .040” in diameter and are .150” in length. The unit is spaced off the PCB by .030”shoulders on the pins. Due to the height of the device it is recommended to have heat sensitive devices away where the air flow might not be blocked.

MODULE BAKEOUT:

Do not bakeout the MSTM-S3-TR

WASHING RECOMMENDATIONS:

The MSTM-S3-TR is not in a hermetic enclosure.It is recommended that the leads be hand cleaned after soldering. Do not completely immerse the module.

SOLDERING RECOMMENDATIONS:

Due to the sensitive nature of this part, hand soldering or wave soldering of the pins is recommended after reflow processes.

POWER SUPPLY REGULATION:

Good power supply regulation is recommended for the MSTM-S3-TR The internal oscillators are regulated to operate from 4.75 - 5.25 volts. Large jumps within this range may still produce varying degrees of wander. If the host system is subject to large voltage jumps due to hot-swapping and the like,it is suggested that there be some form of external regulation such as a DC/DC converter.

GROUND AND POWER SUPPLY LINES:

Power specifications will vary depending primarily on the temperature range. At wider temperature ranges starting at 0 to 70 deg. C., an ovenized

oscillator, OCXO, will be incorporated. The turn-on current for an OCXO requires a peak current of about .4A for about a minute. The steady state current will the vary from 50-150 mA depending on the temperature. It is suggested to plan for the peak current in the power and ground traces pin 18 and pin 5. The other four ground pins 10, 12, 14, and 16are intended for signal grounds.

Package Dimensions

Figure 16

Recommended Footprint Dimensions Figure 17Side Assembly View

Figure 18

Characteristic Measurements Table 6

Revision Revision Date Note

P007/27/01Preliminary Release

P018/01/01Added POR figure and Tri-state pin P028/14/01Added new input frequency

P034/9/02Added Opt_Out information

P044/9/02Updated Pin descriptions

P0512/2/02Corrected Table 1