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IDT7207L25J中文资料

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

The IDT7207 is a monolithic dual-port memory buffer with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. Data is toggled in and out of the device through the use of the Write (W ) and Read (R ) pins.

The devices 9-bit width provides a bit for a control or parity at the user’s option. It also features a Retransmit (RT ) capa-bility that allows the read pointer to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes.

The IDT7207 is fabricated using IDT’s high-speed CMOS technology. It is designed for applications requiring asynchro-nous and simultaneous read/writes in multiprocessing, rate buffering, and other applications.

Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.

?32768 x 9 storage capacity ?High-speed: 15ns access time ?Low power consumption — Active: 660mW (max.)

— Power-down: 44mW (max.)

?Asynchronous and simultaneous read and write ?Fully expandable in both word depth and width

?Pin and functionally compatible with IDT720x family ?Status Flags: Empty, Half-Full, Full ?Retransmit capability

?High-performance CMOS technology

?Military product compliant to MIL-STD-883, Class B ?Industrial temperature range (-40o C to +85o C) is avail-able, tested to military electrical specifications

DATA INPUTS FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP TOP VIEW

PLCC/LCC TOP VIEW

ABSOLUTE MAXIMUM RATINGS (1)

NOTE:3140 tbl 011.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING

NOTE:

3140 tbl 02

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS FOR THE 7207

3140 tbl 04

1.Measurements with 0.4 ≤ V IN ≤ V CC .

R ≥ V IH , 0.4 ≤ V OUT ≤ V CC .

3.I CC measurements are made with outputs open (only capacitive loading).

4.Tested at f = 20MHz.

FF D 2D 1D 0XI Q 0Q 1GND

Q 2Q 3EF XO/HF Vcc FL/RT RS D 3D 8W Q 8D 6D 5D 4D 7Q 5Q 6Q 7Q 4

3140 drw 02

D D D Q Q EF XO /HF 67NC FL /RT RS 76

NC Q C c G N Q Q 8N C Q Q R 3140 drw 03

AC ELECTRICAL CHARACTERISTICS(1)

NOTES:3140 tbl 05

1.Timings referenced as in AC Test Conditions.

2.Pulse widths less than minimum are not allowed.

3.Values guaranteed by design, not currently tested.

4.Only applies to read data flow-through mode.

CAPACITANCE (1)

(T A = +25°C, f = 1.0 MHz)

1.This parameter is sampled and not 100% tested.

2.With output deselected.

READ ENABLE (R ) — A read cycle is initiated on the falling edge of the Read Enable (R ), provided the Empty Flag (EF ) is not set. The data is accessed on a First-In/First-Out basis, inde-pendent of any ongoing write operations. After Read Enable (R )goes HIGH, the Data Outputs (Q 0 through Q 8) will return to a high-impedance condition until the next Read operation. When all the data has been read from the FIFO, the Empty Flag (EF )will go LOW, allowing the “final” read cycle but inhibiting further read operations, with the data outputs remaining in a high-impedance state. Once a valid write operation has been accom-plished, the Empty Flag (EF ) will go HIGH after t WEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes will not affect the FIFO when it is empty.

FIRST LOAD/RETRANSMIT (FL /RT ) — This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device loaded (see Operating Modes). The Single Device Mode is initiated by grounding the Expansion In (XI ).

The IDT7207 can be made to retransmit data when the Retransmit Enable Control (RT ) input is pulsed LOW. A retrans-mit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. Read Enable (R ) and Write Enable (W ) must be in the HIGH state during retransmit. This feature is useful when less than 32,768 writes are performed between resets. The retrans-mit feature is not compatible with the Depth Expansion Mode.EXPANSION IN (XI ) — This input is a dual-purpose pin.Expansion In (XI ) is grounded to indicate an operation in the single device mode. Expansion In (XI ) is connected to Expan-sion Out (XO ) of the previous device in the Depth Expansion or Daisy-Chain Mode.

Figure 1. Output Load *Includes jig and scope capacitances.

SIGNAL DESCRIPTIONS Inputs:

DATA IN (D 0–D 8) — Data inputs for 9-bit wide data.

Controls:

RESET (RS ) — Reset is accomplished whenever the Reset (RS ) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place.Both the Read Enable (R ) and Write Enable (W ) inputs must be in the HIGH state during the window shown in Figure 2(i.e. t RSS before the rising edge of RS ) and should not change until t RSR after the rising edge of RS .

WRITE ENABLE (

W ) — A write cycle is initiated on the falling edge of this input if the Full Flag (FF ) is not set. Data set-up and hold times must be adhered-to, with respect to the rising edge of the Write Enable (W ). Data is stored in the RAM array sequentially and independently of any on-going read operation.After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF ) will be set to LOW,and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF ) is reset by the rising edge of the read operation.

To prevent data overflow, the Full Flag (FF ) will go LOW on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag (FF ) will go HIGH after t RFF , allowing a new valid write to begin. When the FIFO is full, the internal write pointer is blocked from W , so external changes in W will not affect the FIFO when it is full.

1.1K ?

30pF*

D.U.T.

OR EQUIVALENT CIRCUIT

3140 drw 04

Outputs:

FULL FLAG (FF ) — The Full Flag (FF ) will go LOW, inhibiting further write operations, when the device is full. If the read pointer is not moved after Reset (RS ), the Full Flag (FF ) will go LOW after 32,768 writes.

EMPTY FLAG (EF ) — The Empty Flag (EF ) will go LOW,inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty.EXPANSION OUT/HALF-FULL FLAG (XO /HF ) — This is a dual-purpose output. In the single device mode, when Expan-sion In (XI ) is grounded, this output acts as an indication of a half-full memory.

After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF ) will be set to LOW

Figure 2. Reset

Figure 3. Asynchronous Write and Read Operation

NOTE:

1. W and R = V IH around the rising edge of RS .

and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF ) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI ) is con-nected to Expansion Out (XO ) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. There will be an XO pulse when the Write pointer reaches the last location of memory, and an additional XO pulse when the Read pointer reaches the last location of memory.

DATA OUTPUTS (Q 0-Q 8) — Q 0-Q 8 are data outputs for 9-bit wide data. These outputs are in a high-impedance condition whenever Read (R ) is in a HIGH state.

HF , FF

t RSC

t RS

t RSS

t RSR

t EFL

t HFH , t FFH

3140 drw 05

0–D 8

Q 0–Q 8

Figure 4. Full FlagTiming From Last Write to First Read

NOTE:

1. EF , FF and HF may change status during Retransmit, but flags will be valid at t RTC .

Figure 6. Retransmit

Figure 5. Empty Flag Timing From Last Read to First Write

DATA OUT

RTC

t RT

t RTS

W ,R

HF , EF , FF

t RTR

FLAG VALID

3140 drw 09

RTF

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.

Figure 9. Half-Full Flag Timing

Figure 10. Expansion Out

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.

3140 drw 11

3140 drw 12

Figure 11. Expansion In

corresponding input control signals of multiple devices. Sta-tus flags (EF , FF and HF ) can be detected from any one device.Figure 13 demonstrates an 18-bit word width by using two IDT7207s. Any word width can be attained by adding addi-tional IDT7207s (Figure 13).

Bidirectional Operation

Applications which require data buffering between two systems (each system capable of Read and Write operations)can be achieved by pairing IDT7207s as shown in Figure 16.Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO.The data is enabled on the bus in (t WEF + t A ) ns after the rising edge of W , called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after t RHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted.

In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W , the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15).

3140 drw 14

OPERATING MODES:

Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information, refer to Tech Note 8: Oper-ating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs.

Single Device Mode

A single IDT7207 may be used when the application requirements are for 32,768 words or less. The IDT7207 is in a Single Device Configuration when the Expansion In (XI )control input is grounded (see Figure 12).

Depth Expansion

The IDT7207 can easily be adapted to applications when the requirements are for greater than 32,768 words. Figure 14demonstrates Depth Expansion using three IDT7207s. Any depth can be attained by adding additional IDT7207s. The IDT7207 operates in the Depth Expansion mode when the following conditions are met:

1.The first device must be designated by grounding the First Load (FL ) control input.

2.All other devices must have FL in the HIGH state.

3.The Expansion Out (XO ) pin of each device must be tied to the Expansion In (XI ) pin of the next device. See Figure 1

4.4.External logic is needed to generate a composite Full Flag (FF ) and Empty Flag (EF ). This requires the ORing of all EF s and ORing of all FF s (i.e. all must be set to generate the correct composite FF or EF ). See Figure 14.

5.The Retransmit (RT ) function and Half-Full Flag (HF ) are not available in the Depth Expansion Mode.For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules.

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the

Figure 12. Block Diagram of 32,768 x 9 FIFO Used in Single Device Mode

NOTE:

1.Flag detection is accomplished by monitoring the FF , EF and HF signals on either (any) device used in the width expansion configuration.

Do not connect any output signals together.

Figure 13. Block Diagram of 32,768 x 18 FIFO Memory Used in Width Expansion Mode

WRITE (W )

FULL FLAG (FF )

RESET (RS )

READ (R )

DATA OUT (Q)EMPTY FLAG (EF )RETRANSMIT (RT )

3140 drw 15

WRITE (W )FULL FLAG (FF )

RESET (RS )

DATA (D)IN READ (R )EMPTY FLAG (EF )RETRANSMIT (RT )

DATA (Q)

OUT 3140 drw 16

TRUTH TABLES

TABLE I – RESET AND RETRANSMIT

TABLE II – RESET AND FIRST LOAD

Figure 14. Block Diagram of 98,304 x 9 FIFO Memory (Depth Expansion)

3140 tbl 101. XI is connected to XO of previous device. See Figure 14.

2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output

3140 tbl 09

1. Pointer will Increment if flag is HIGH.

W RS

FULL

EMPTY

V CC

R Q

Figure 17. Read Data Flow-Through Mode

Figure 16. Bidirectional FIFO Operation

R , W , RS

D 0–D N

D 9-D N D 18-D N

D (N-8)-D N

Q 9–Q 17

Q 0–Q 83140 drw 18

NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 1

Figure 15. Compound FIFO Expansion

SYSTEM A SYSTEM B

DATA R

DATA OUT

3171 drw 20

Figure 18. Write Data Flow-Through Mode

ORDERING INFORMATION

DATA W

DATA

OUT

X Power

XX Speed

X Package

X Process/Blank Commercial (0°C to +70°C)B

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B P D J L Plastic DIP Ceramic DIP

Plastic Leaded Chip Carrier

Leadless Chip Carrier (Military only)152025303550Commercial Only Commercial Only Military Only

Commercial Only XXXX Device 7207

32,768 x 9 FIFO

IDT

L Low Power Access Time (t A ) Speed in ns

3140 drw 22