Data sheet acquired from Harris Semiconductor
SCHS245B
Features
?Buffered Inputs
?Typical Propagation Delay
-4ns at V CC = 5V, T A = 25o C, C L = 50pF ?Exceeds 2kV ESD Protection per MIL-STD-883,Method 3015
?SCR-Latchup-Resistant CMOS Process and Circuit Design ?Speed of Bipolar FAST?/AS/S with Signi?cantly Reduced Power Consumption ?Balanced Propagation Delays
?AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply ?±24mA Output Drive Current -Fanout to 15 FAST? ICs
-Drives 50? Transmission Lines
Description
The ’AC245and ’ACT245are octal-bus transceivers that utilize Advanced CMOS Logic technology.They are non-inverting three-state bidirectional transceiver-buffers intended for two-way transmission from “A”bus to “B”bus or “B”bus to “A”.The logic level present on the direction input (DIR)determines the data direction.When the output enable input (OE)is HIGH,the outputs are in the high-impedance state.
Pinout
CD54AC245, CD54ACT245
(CERDIP)
CD74AC245, CD74ACT245
(PDIP , SOIC, SSOP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.RANGE (o C)PACKAGE CD54AC245F3A -55 to 12520 Ld CERDIP CD74AC245E -55 to 12520 Ld PDIP CD74AC245M -55 to 12520 Ld SOIC CD74AC245SM -55 to 12520 Ld SSOP CD54ACT245F3A -55 to 12520 Ld CERDIP CD74ACT245E -55 to 12520 Ld PDIP CD74ACT245M -55 to 12520 Ld SOIC CD74ACT245SM -55 to 125
20 Ld SSOP
NOTES:
1.When ordering,use the entire part number.Add the suffix 96to obtain the variant in the tape and reel.
2.Wafer and die for this part number is available which meets all
electrical specifications.Please contact your local TI sales office or customer service for ordering information.
1112131415161718201910
9
87654321DIR A0A1A2A3A4A6A5A7
GND V CC B0B1B2OE B3B4B5B6B7
September 1998 - Revised October 2000
CD54/74AC245,CD54/74ACT245
Octal-Bus Transceiver,Three-State, Non-Inverting
[ /Title (CD74AC245,
CD74ACT245)/Sub-ject (Octal-Bus Trans-ceiver,Three-State,Non-Invert-ing)/Autho r ()/Key-words (Har-ris Semi-con-ductor,Advan ced CMOS ,Harris Semi-con-
元器件交易网https://www.wendangku.net/doc/1314513531.html,
Functional Diagram
TRUTH TABLE
CONTROL INPUTS OPERATION
OE DIR L L B Data to A Bus L H A Data to B Bus H
X
Isolation
H = High Level, L = Low Level, X = Irrelevant
To prevent excess currents in the High-Z (isolation)modes,all I/O terminals should be terminated with 10k ? to 1M ? resistors.
181716151311
12142B0B1B2B3B4B5B6B7
OE
DIR 1
19
49
35678A0A1A2A3A4A5A6A7
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, V CC. . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 6V DC Input Diode Current, I IK
For V I < -0.5V or V I > V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, I OK
For V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, I O
For V O > -0.5V or V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC V CC or Ground Current, I CC or I GND (Note 3) . . . . . . . . .±100mA Operating Conditions
Temperature Range, T A . . . . . . . . . . . . . . . . . . . . . .-55o C to 125o C Supply Voltage Range, V CC (Note 4)
AC T ypes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, V I, V O . . . . . . . . . . . . . . . . .0V to V CC Input Rise and Fall Slew Rate, dt/dv
AC T ypes, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . .50ns (Max) AC T ypes, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . .20ns (Max) ACT T ypes, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . .10ns (Max)Thermal Resistance (T ypical, Note 5)θJA (o C/W) E Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
SM Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Maximum Junction T emperature (Plastic Package) . . . . . . . . . .150o C Maximum Storage Temperature Range . . . . . . . . . .-65o C to 150o C Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300o C
CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied.
NOTES:
3.For up to 4 outputs per device, add±25mA for each additional output.
4.Unless otherwise specified, all voltages are referenced to ground.
5.The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Speci?cations
PARAMETER SYMBOL
TEST
CONDITIONS
V CC
(V)
25o C
-40o C TO
85o C
-55o C TO
125o C
UNITS V I(V)I O(mA)MIN MAX MIN MAX MIN MAX
AC TYPES
High Level Input Voltage V IH-- 1.5 1.2- 1.2- 1.2-V
3 2.1- 2.1- 2.1-V
5.5 3.85- 3.85- 3.85-V Low Level Input Voltage V IL-- 1.5-0.3-0.3-0.3V
3-0.9-0.9-0.9V
5.5- 1.65- 1.65- 1.65V High Level Output Voltage V OH V IH or V IL-0.05 1.5 1.4- 1.4- 1.4-V
-0.053 2.9- 2.9- 2.9-V
-0.05 4.5 4.4- 4.4- 4.4-V
-43 2.58- 2.48- 2.4-V
-24 4.5 3.94- 3.8- 3.7-V
-75
(Note 6, 7)
5.5-- 3.85---V
-50
(Note 6, 7)
5.5---- 3.85-V
Low Level Output Voltage
V OL
V IH or V IL
0.05 1.5-0.1-0.1-0.1V 0.053-0.1-0.1-0.1V 0.05 4.5-0.1-0.1-0.1V 123-0.36-0.44-0.5V 24 4.5-0.36-0.44-0.5V 75(Note 6, 7) 5.5--- 1.65--V 50(Note 6, 7)
5.5----- 1.65V Input Leakage Current I I V CC or GND - 5.5-±0.1-±1-±1μA Three-State Leakage Current
I OZ
V IH or V IL V O =V CC or GND - 5.5
-±0.5
-±5
-±10
μA
Quiescent Supply Current MSI I CC
V CC or GND
0 5.5-8-80-160μA
ACT TYPES
High Level Input Voltage V IH -- 4.5 to 5.52-2-2-V Low Level Input Voltage V IL -- 4.5 to 5.5-0.8-0.8-0.8V High Level Output Voltage
V OH
V IH or V IL
-0.05 4.5 4.4- 4.4- 4.4-V -24 4.5 3.94- 3.8- 3.7-V -75(Note 6, 7) 5.5-- 3.85---V -50(Note 6, 7)
5.5---- 3.85-V Low Level Output Voltage
V OL
V IH or V IL
0.05 4.5-0.1-0.1-0.1V 24 4.5-0.36-0.44-0.5V 75(Note 6, 7) 5.5--- 1.65--V 50(Note 6, 7)
5.5----- 1.65V Input Leakage Current I I V CC or GND - 5.5-±0.1-±1-±1μA Three-State or Leakage Current
I OZ
V IH or V IL V O =V CC or GND - 5.5
-±0.5
-±5
-±10
μA
Quiescent Supply Current MSI
I CC V CC or GND 0 5.5-8-80-160μA Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load ?I CC
V CC -2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
NOTES:
6.Test one output at a time for a 1-second maximum duration.Measurement is made by forcing current and measuring voltage to minimize power dissipation.
7.Test verifies a minimum 50? transmission-line-drive capability at 85o C, 75? at 125o C.
DC Electrical Speci?cations
(Continued)
PARAMETER
SYMBOL TEST CONDITIONS
V CC (V)25o C -40o C TO 85o C -55o C TO 125o C UNITS V I (V)I O (mA)MIN MAX MIN MAX MIN MAX
ACT Input Load Table
INPUT UNIT LOAD
An, Bn0.83
OE0.64
DIR0.25
NOTE:Unit load is?I CC limit specified in DC Electrical Specifications
T able, e.g., 2.4mA max at 25o C.
Switching Speci?cations Input t r, t f = 3ns, C L= 50pF (Worst Case)
PARAMETER SYMBOL V CC (V)
-40o C TO 85o C-55o C TO 125o C
UNITS MIN TYP MAX MIN TYP MAX
AC TYPES
Propagation Delay, Data to Output t PLH, t PHL 1.5--96--106ns
3.3
(Note 9)
3.2-10.83-11.9ns
5
(Note 10)
2.2-7.7 2.1-8.5ns
Propagation Delay, Output Disable to Output t PLZ, t PHZ 1.5--159--175ns
3.3
4.7-1
5.9 4.4-17.5ns
5 3.7-12.7 3.5-14ns
Propagation Delay, Output Enable to Output t PZL, t PZH 1.5--159--175ns
3.3 5.6-19 5.3-21ns
5 3.7-12.7 3.5-14ns
Minimum (Valley) V OH During Switching of Other Outputs (Output Under Test Not Switching)
V OHV
See Figure 1
5- 4 at
25o C
-- 4 at
25o C
-V
Maximum (Peak) V OL During Switching of Other Outputs (Output Under Test Not Switching)
V OLP
See Figure 1
5- 1 at
25o C
-- 1 at
25o C
-V
Three-State Output Capacitance C O--15--15-pF Input Capacitance C I---10--10pF Power Dissipation Capacitance C PD
(Note 11)
--57--57-pF ACT TYPES
Propagation Delay, Data to Output t PLH, t PHL5
(Note 10)
2.7-9.1 2.5-10ns
Propagation Delay,
Output Disable to Output
t PLZ, t PHZ5 3.712.7 3.514ns
Propagation Delay,
Output Enable to Output
t PZL, t PZH5 3.813.1 3.614.4ns
Minimum (Valley) V OH During Switching of Other Outputs (Output Under Test Not Switching)
V OHV
See Figure 1
5- 4 at
25o C
-- 4 at
25o C
-V
Maximum (Peak) V OL During Switching of Other Outputs (Output Under Test Not Switching)
V OLP
See Figure 1
5- 1 at
25o C
-- 1 at
25o C
-V
Three-State Output Capacitance C O --15--15-pF Input Capacitance
C I ---10--10pF Power Dissipation Capacitance C P
D (Note 11)
--57
--57
-pF
NOTES:
8.Limits tested 100%
9.3.3V Min is at 3.6V, Max is at 3V.10.5V Min is at 5.5V, Max is at 4.5V.
11.C PD is used to determine the dynamic power consumption per channel.
AC: P D = V CC 2 f i (C PD + C L )
ACT: P D = V CC 2 f i (C PD + C L ) + V CC ?I CC where f i = input frequency, C L = output load capacitance, V CC = supply voltage.
NOTES:
12.Input pulses have the following characteristics: PRR ≤ 1MHz, t r = 3ns, SKEW 1ns.
13.R.F.fixture with 700MHz design rules required.IC should be soldered into test board and bypassed with 0.1μF capacitor.Scope and
probes require 700MHz bandwidth.
FIGURE 1.SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
Switching Speci?cations Input t r , t f = 3ns, C L = 50pF (Worst Case)
(Continued)
PARAMETER
SYMBOL V CC (V)
-40o C TO 85o C
-55o C TO 125o C
UNITS MIN TYP MAX MIN TYP MAX OTHER OUTPUTS
OUTPUT UNDER TEST
V OH V OL
V OHV V OLP V OL
V OH
NOTE:
14.For AC Series only: When V CC = 1.5V, R L = 1k ?.
FIGURE 2.THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
FIGURE 3.PROPAGATION DELAY TIMES
DUT WITH THREE-STATE OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE
GND (t PHZ , t PZH )
OPEN (t PHL , t PLH )OUTPUT
R L C L
50pF
2 V CC (t PLZ , t PZL )(OPEN DRAIN)500?R L
500?
OUT INPUT LEVEL
90%V S 10%
GND
t r = 3ns
t PZL
0.2 V CC
V OL (≠V CC )
0.8 V CC OUTPUTS ENABLED
OUTPUTS DISABLED
V S
V S
OUTPUTS ENABLED
t PLZ
t PHZ
t PZH
OUTPUTS DISABLED
t f = 3ns
OUTPUT:LOW TO OFF
TO LOW
OUTPUT:HIGH TO OFF
TO HIGH
(NOTE 14)
t r = 3ns
INPUT LEVEL An GND
Bn
t PLH t f = 3ns
90%V S 10%V S
t PHL DUT OUTPUT
R L (NOTE)OUTPUT LOAD
500?
C L 50pF
NOTE:For AC Series Only: When V CC = 1.5V , R L = 1k ?.
FIGURE 4.PROPAGATION DELAY TIMES
AC
ACT Input Level
V CC 3V Input Switching Voltage, V S 0.5 V CC 1.5V Output Switching Voltage, V S
0.5 V CC
0.5 V CC
PACKAGING INFORMATION
Orderable Device Status(1)Package
Type Package
Drawing
Pins Package
Qty
Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)
CD54AC245F3A ACTIVE CDIP J201TBD A42SNPB N/A for Pkg Type CD54ACT245F3A ACTIVE CDIP J201TBD A42SNPB N/A for Pkg Type CD74AC245E ACTIVE PDIP N2020Pb-Free
(RoHS)
CU NIPDAU N/A for Pkg Type
CD74AC245EE4ACTIVE PDIP N2020Pb-Free
(RoHS)
CU NIPDAU N/A for Pkg Type
CD74AC245M ACTIVE SOIC DW2025Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245M96ACTIVE SOIC DW202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245M96E4ACTIVE SOIC DW202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245M96G4ACTIVE SOIC DW202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245ME4ACTIVE SOIC DW2025Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245MG4ACTIVE SOIC DW2025Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245SM OBSOLETE SSOP DB20Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245SM96ACTIVE SSOP DB202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245SM96E4ACTIVE SSOP DB202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74AC245SM96G4ACTIVE SSOP DB202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245E ACTIVE PDIP N2020Pb-Free
(RoHS)
CU NIPDAU N/A for Pkg Type
CD74ACT245EE4ACTIVE PDIP N2020Pb-Free
(RoHS)
CU NIPDAU N/A for Pkg Type
CD74ACT245M ACTIVE SOIC DW2025Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245M96ACTIVE SOIC DW202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245M96E4ACTIVE SOIC DW202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245M96G4ACTIVE SOIC DW202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245ME4ACTIVE SOIC DW2025Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245MG4ACTIVE SOIC DW2025Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245SM OBSOLETE SSOP DB20Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245SM96ACTIVE SSOP DB202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245SM96E4ACTIVE SSOP DB202000Green(RoHS&
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CD74ACT245SM96G4ACTIVE SSOP DB202000Green(RoHS&CU NIPDAU Level-1-260C-UNLIM
Orderable Device Status(1)Package
Type Package
Drawing
Pins Package
Qty
Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)
no Sb/Br)
(1)The marketing status values are defined as follows:
ACTIVE:Product device recommended for new designs.
LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.
NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.
PREVIEW:Device has been announced but is not in production.Samples may or may not be available.
OBSOLETE:TI has discontinued the production of the device.
(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check https://www.wendangku.net/doc/1314513531.html,/productcontent for the latest availability information and additional product content details.
TBD:The Pb-Free/Green conversion plan has not been defined.
Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.
Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)
(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Type Package Drawing Pins SPQ
Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)
P1(mm)W (mm)Pin1Quadrant CD74AC245M96SOIC DW 202000330.024.410.813.0 2.712.024.0Q1CD74AC245SM96SSOP DB 202000330.016.48.27.5 2.512.016.0Q1CD74ACT245M96SOIC DW 202000330.024.410.813.0 2.712.024.0Q1CD74ACT245SM96
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD74AC245M96SOIC DW202000346.0346.041.0 CD74AC245SM96SSOP DB202000346.0346.033.0 CD74ACT245M96SOIC DW202000346.0346.041.0 CD74ACT245SM96SSOP DB202000346.0346.033.0
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