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NCP5890MUTXG;中文规格书,Datasheet资料

NCP5890

Light Management IC Dedicated for LCD Backlighting and Multi-LED Fun Light Applications

The NCP5890 is part of the Light Management IC (LMIC) family. It is a fully programmable subsystem that manages multiple illumination functions integrated into the silicon.

Features

?34 V Output Voltage Capability

?Include Three Independent PWM to Control LED Segments ?2.7 to 5.5 V Input V oltage Range

?90% Peak Efficiency with 4.7 m H / 150 m W Inductor ?Gradual Dimming Built?in

?Integrated Ambient Light Sensing Adjusts Backlight Contrast ?Built?in I2C Address Extension

?Tight 1% I?LED Tolerance

?True Cut Off Function Minimizes Load Leakage Current in Shutdown

?Ultra Thin 0.5 mm QFN16 Package

?This is a PB?Free Device

Typical Applications

?Portable Back Light & Keyboard

?Digital Cellular Phone Camera Photo Flash

Figure 1. Typical Multiple White LED Application

https://www.wendangku.net/doc/2e5213355.html,

UQFN16

MU SUFFIX

CASE 523AF

MARKING DIAGRAM

(Note: Microdot may be in either location)

5890= Specific Device Code

A= Assembly Location

L= Wafer Lot

Y= Year

W= Work Week

G= Pb?Free Package

5890

ALYW G

?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specification Brochure, BRD8011/D.

Figure 2. Simplified Block Diagram

Figure 3. Basic NCP5890 Structure

PIN DESCRIPTIONS

PIN Name Type Description

1SCL INPUT,

DIGITAL This pin carries the I2C clock to control the DC/DC converter and is used to set up the output cur-rent and the photo sensor. The SCL clock is associated with the SDA signal.

2SDA INPUT,

DIGITAL This pin carries the data provided by the I2C protocol. The content of the SDA byte is used to pro-gram the mode of operation and to set up the output current.

3I2CADR INPUT,

DIGITAL This pin is used to select the I2C address of the NCP5890:

I2CADR = Low 3 address = %0111 0010 = $72

I2CADR = High 3 address = %0111 0100 = $74

In order to avoid any risk during the operation, the digital levels are intended to be hardwired prior to power up the system.

4VSB POWER,

OUTPUT This pin provides a switched voltage, derived from the Vbat supply, to bias the external photo sense. The current capability of this voltage is 2 mA.

The VSB switch output is open when the Shutdown mode has been engaged.

5AMBS INPUT,

ANALOG This pin senses the voltage developed across the external Photo Bias resistor. Since this is a very high impedance input, care must be observed to minimize the leakage current and the noise that may influence the photo sense analog function. The bias parameters associated with the AMBS pin are reloaded when the chip resumes from Shutdown to Normal operation.

6I PK INPUT,

ANALOG This pin provides the inductor peak current during normal operation. In no case shall the voltage at I PK pin be forced either higher or lower than the 1144 mV provided by the internal reference.

7I REF INPUT,

ANALOG This pin provides the reference current, based on the internal band?gap voltage reference, to con-trol the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the LED biases. An external current source can be used to bias this pin to dim the light coming out of the LED.

In no case shall the voltage at I REF pin be forced either higher or lower than the 1144 mV provided by the internal reference.

8AGND POWER This pin is the GROUND signal for the analog and digital blocks and must be connected to the sys-

tem ground. A ground plane is strongly recommended.

9FB INPUT,

ANALOG This pin is the current sense of the series arranged LED. The built?in current mirror will automatic-ally adapt the voltage drop across this pin (typically 400 mV).

10PWM3INPUT,

ANALOG This pin provides a PWM control of the LED connected between PWM3?FB. The PWM is pro-grammed by the I2C port and preset to zero upon power ON.

11PWM2INPUT,

ANALOG This pin provides a PWM control of the LED connected between PWM2. The PWM is programmed by the I2C port and preset to zero upon power ON.

12PWM1INPUT,

ANALOG This pin provides a PWM control of the LED connected between PWM1. The PWM is programmed by the I2C port and preset to zero upon power ON.

13Lx POWER The external inductor shall be connected between this pin (drain of the internal Power switch) and

Vbat. The voltage is internally clamped at 34V under worst case conditions. The external Schottky

diode shall be connected as close as possible to this pin. See Note 1 for ESR recommendations. 14PGND POWER This pin is the GROUND reference for the DC/DC converter and the output current control. The pin

must be connected to the system ground, a ground plane is strongly recommended.

15VBAT INPUT,

POWER Input Battery voltage to supply the analog , the digital blocks and the main Power switch driver. The pin must be decoupled to ground by a 10 m F ceramic capacitor.

16Vos INPUT,

POWER This pin senses the output voltage supplied by the DC/DC converter. The Vos pin must be by-passed by 1.0 m F/50 V ceramic capacitor located as close as possible to the pin to properly bypass the output voltage to ground. The circuit will not operate without such bypass capacitor connected to the Vos pin.

The output voltage is internally clamped to 34 V maximum in the event of a no load situation. NOTE: Due to the very fast dV/dt transient developed during the operation, using a low pass filter is strongly recommended as depicted in the schematic diagram Figure 1.

https://www.wendangku.net/doc/2e5213355.html,ing low ESR ceramic capacitor and low DCR inductor is mandatory to optimize the DC/DC efficiency

MAXIMUM RATINGS (Note 2)

Symbol Rating Value Unit V BAT Power Supply?0.3 < V < 7.0V V LX Output Switching Voltage34V

SCL, SDA Digital Input Voltage

Digital Input Current ?0.3 < V < V BAT

ESD Human Body Model: R = 1500 W, C = 100 pF (Note 3) Machine Model

200

P D R q jc R q ja UQFN16 package ? Power Dissipation @ T A = +85°C (Note 4)

LLGA16 package? Thermal Resistance Junction to Case

LLGA16 package? Thermal Resistance Junction to Air

300

130

°C/W

T A Operating Ambient T emperature Range?40 to +85°C

T J Operating Junction T emperature Range?40 to +125°C T Jmax Maximum Junction T emperature+150°C T stg Storage T emperature Range?65 to + 150°C Latch?up current maximum rating per JEDEC standard: JESD78.±100mA

2.Maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip whatever the operating

temperature may be.

3.This device series contains ESD protection and exceeds the following tests:

Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22?A114

Machine Model (MM) ±200 V per JEDEC standard: JESD22?A115

4.The maximum package power dissipation limit must not be exceeded.

5.Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J?STD?020A.

POWER SUPPLY SECTION: (Typical values are referenced to T a = +25°C, Min & Max values are referenced ?40°C to +85°C ambient temperature, unless otherwise noted),operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.

Pin Symbol Rating Min Typ Max Unit 15V bat Power Supply 2.7 5.5V 15V UVLO Power Supply Input Voltage (See Figure 22) 2.0 2.2 2.4V 15V UVLOHY Under Voltage Hysterisis, negative going slope150270mV 13I out Continuous load DC current, Vout pin

@ 3.0 V < Vbat < 5.5 V, Cout = 1.0 m F

25mA 13Isw Output Leakage Current (Lx pin) @ Iout = 0, Vout = 35 V200nA Vout Output Voltage Compliance (OVP)303234V

Vout HY OVP Output Voltage Hysterisis 1.0 1.8V

T start DC/DC Start time (Cout = 1.0 m F) 3.0 V < Vbat = nominal < 5.5 V from last

ACK bit to full load operation

600m s

15I stdb Stand By Current, Vbat = 3.6 V, Iout = 0 mA

@SCL = SDA = H (no port activity)

1.0m A

15I op Operating Current, @ Iout = 0 mA, Vbat = 3.6 V 2.0mA 13I PK Maximum Inductor Peak Current @ R = 13 k W?10%855+10%mA 13I TOL Output Current T olerance @Vbat = 3.6V, I LED = 10 mA

?25°C < T A < 85°C

±1% 13Fpwr Boost Operating Frequency (0°C < T A < 85°C) 1.13 1.3 1.47MHz T SD Thermal Shutdown Protection160°C

T SDH Thermal Shutdown Protection Hysteresis30°C

E PWR Efficiency @ Vbat = 3.6 V, ESR ≤ 150 m W

Coilcraft = LPO3310?472ML, Cout = 1.0 m F

I?LED = 10 mA, Vf = 2.85 V

I?LED = 25 mA, Vf = 3.4 V (Note 6)75

R DS(on)Power Switch NMOS R DS(on)500m W 6.Note 1: using low DCR inductor with low eddy current losses is mandatory to get the high efficiency operation

ANALOG SECTION: (Typical values are referenced to T A = +25°C, Min & Max values are referenced ?40°C to +85°C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.

Pin Symbol Rating Min Typ Max Unit 7I REF Reference Current @ Vref = 1144 mV (Note 8)1100m A 6I PK Reference Current @ Vref = 1144 mV (Note 8)1100m A k ref Reference Current to ILED peak current ratio250

k pk Reference Current to Inductor peak current ratio9700 7V REF Reference Voltage (Note 8)?3%1144+3%mV 6V REFK Reference Voltage (Note 8)?10%1144+10%mV 9V FB Feedback Voltage @ ILED = 25mA (Note 9)425mV M DCY Boost Operating Maximum Duty Cycle (0°C < T A < 85°C)9094% 9I LKGM Current Mirror Leakage Current200nA 10, 11, 12Fpwm Low Frequency PWM Clock (derived from F pwr/8192)140160185Hz

F LF Low Frequency Clock (derived from F pwr/8192)0.620Hz

4V VSD Photo sense bias supply @ Ibias = 1mA 2.5Vbat V 4R VSD Photo sense bias supply internal impedance30W 4I SDUSD Photo sense leakage current (Note 11)100nA

G AMB0.25Photo sense internal Gain 1/40.25

G AMB0.50Photo sense internal Gain 1/20.5

G AMB01Photo sense internal Gain 11

G AMB02Photo sense internal Gain 22

G AMB04Photo sense internal Gain 44

5V iph Photo sense input voltage (Note 10) 1.5V 10BVpwm2Breakdown Voltage pin 10 to pin 10 (Note 11)9V 11BVpwm2Breakdown Voltage pin 11 to Pin 12 (Note 11)9V 12BVpwm1Breakdown voltage pin 12 to GND (Note 11)9V

7.The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended.

8.The external circuit must not force the I REF or I PK pin voltage either higher or lower than the specified voltage. The reference voltage applies

to both I REF and I PK pins.

9.This parameter guarantees the function for production test purposes.

10.The ambient sense linearity is guaranteed when the voltage at the output of the internal amplifier is limited to 1.5 V. This voltage is equal to the

input voltage times the programmed gain. Beyond this value, the operational amplifier is in the saturation region and the linearity is no longer guaranteed.

11.Parameter guaranteed by design, not tested in production.

DIGITAL PARAMETERS SECTION: (Typical values are referenced to T a = +25°C, Min & Max values are referenced ?40°C to +85°C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.

Pin Symbol Rating Min Typ Max Unit 1F SCK Input I2C clock frequency400kHz 1,2V IH Positive going Input High Voltage Threshold, SCL, SDA signals 1.6V BAT V 1,2V IL Negative going Input High Voltage Threshold, SCL, SDA signals00.4V 2C IN SDA Input Capacitance1015pF 3V IHD I2C address extension Vbat*0.7Vbat+0.3V V 3V ILD I2C address extension00.3V NOTE:Digital inputs undershoot < ? 0.30 V to ground, Digital inputs overshoot < 0.30 V to V BAT

DC/DC OPERATION

The boost converter is based on a PWM structure to generate the output voltage necessary to drive the series arranged LED. The system includes an open load detection to avoid over voltage situation when the LED are disconnected from the V out pin. A built?in circuit prevent high inrush current when the system is powered.

The ILED is regulated by means of a built?in current mirror controlled by the digital content of the ILEDREG register. With a typical 1.3Mhz operation frequency, the converter can run at full power with a tiny 4.7 m H inductor. However, care must be observed, at DCR level, to optimize the total DC/DC conversion efficiency. In particular, the ferrite material shall have limited eddy current losses at high frequency. Depending upon the type of material, the eddy losses in the inductor can range from a low 40mW to a high 250mW under the same bias and load conditions. The ILED current is regulated by the means of internal current mirror connected to the FB pin. The voltage at this pin can vary between a low 100 mV to a 1.5 V maximum, depending upon the ILED current amplitude. Typically, the FB voltage will be 425 mV under normal operation. Table 1. Recommended Inductor Manufacturers

Part Number Manufacturers

LPO3310?472ML COILCRAFT

VLS3010T?4R7MR80TDK

D6 D2 D3 D4

Figure 5. Typical Switching Operation V bat = 3.6 V ILED = 25 mA

Although the total ohmic resistance plays an important role in the losses developed in the converter, the switching losses are key when the operating frequency is beyond a few kilohertz range. To minimize such losses, the internal power NMOS is designed to minimize the dI/dt, thus minimizing the I*V crossing time. As a consequence, the slope of the positive going voltage ?VLX? present at the Lx pin is very fast as well and an overshoot is created since the Schottky rectifier has an intrinsic turn-on time: the voltage keeps going until the diode turns?on, clamping the VLX voltage at the output value. Such a mechanism is depicted in Figure 6. The proposed Schottky, depicted in the schematic Figure 1, is a good alternative to minimize such an overshoot.

On the other hand, the same overshoot is propagated to the V out voltage when the system operates under open load condition. As a consequence, it is strongly recommended to implement a simple filter, built with a small footprint resistor, to makes sure that no any uncontrolled operation of the high sensitive pin Vos will happen under the worst

case conditions: see Figure 1, resistor R5.

Figure 6. Typical Turn On Time of the Schottky Rectifier

I2C Protocol

The standard I2C protocol is used to transfer the data from the MCU to the NCP5890. Leaving aside the Acknowledge bit, the NCP5890 chip does not return data back to the MCU.

The physical address of the NCP5890 can be selected as 0111 001X or 0111 010X (the X being the Read / Write identifier as defined by the I2C specification) depending upon the digital status present at the I2CADR pin:

I2CADR = Low 3 address = %0111 0010 = $72

I2CADR = High 3 address = %0111 0100 = $74

In order to avoid any risk during the operation, the digital level at the I2CADR pin must be hardwired either to GND or to Vbat prior to power up the system.

The first byte of the I2C frame shall be selected address ($72 or $74) when a Write is send to the chip.

To set up a new output current value, a full frame will be sent by the MCU. The frame contains three consecutive bytes and shall fulfill the I2C specifications (see Figure 7):?First byte: I2C address, write 3 $72

(assuming I2CADR = Low)

?Second byte: register selection 3 %0000 XXXX = internal register address

?Third byte: DA TA 3 %XXXX XXXX = function / output current value

An infinite number of register selection / data pair can be send on the I2C port once the physical address has been decoded (see Figure 8). The transmission ends when the STOP signal is send by the SCL/SDA digital code.

Figure 8. Multi Frames I2C Sequence

On the other hand, although the chip does not handle the Read operation, care must be observed since sending a Read command ($73 or $75) is equivalent to a Write command and the selected register will be updated accordingly.

Registers Setup Selection

The Register Selection follows the I2C address of a new frame and must be followed by the DATA Register. The content of the Register Selection byte is not stored into the chip and a new one must be sent for every DATA upload.

The last code $0F is reserved for ON Semiconductor to control the manufacturing test and access to this register is not permitted outside the ON Semiconductor final test facilities. Shutdown and True Cut?off

To shutdown the device the user must write $00 in Register Selection. When in shutdown condition, FB pin is turned in impedance and truly isolates the load from the battery. The NCP5980 is immediately turn on when one of the Register Selection from $01 to $0F is active to point a given DATA Register.

Table 2. Register Selection

Register Functions Register Address Shutdown the chip SDN$00 Select I?LED current setup and immediate LED update ILEDREG[4..0]$01 Select I?LED target Gradual Dimming command UP GDIM?UP[4..0]$02 Select I?LED target Gradual Dimming command DOWN GDIM?DWN[4..0]$03 Set Timing & Start gradual Dimming Sequence TDIM[4..0]$04 Select PWM0 register PWM0[4..0]$05 Select PWM1 register PWM1[4..0]$06 Select PWM2 register PWM2[4..0]$07 Set up Photo sense input stage gain PHGAIN[4..0]$08 Set up Photo Sense I?LED minimum value PHMIN[3..0]$09 Set up Photo Sense timing PHCLK[5..0]$0A RFU$0B RFU$0C RFU$0D RFU$0E Reserved for manufacturing test: do not access FTEST[7..0]$0F ILED Current

The ILED current depends upon the reference current (I REF pin ) and the digital contents of the ILEDREG register. The I2C port is used to program the ILED current by writing to the ILEDREG register. The load current is derived from the 1144mV reference voltage associated to the external resistor connected across I REF pin and Ground (see Figure 9). The maximum ILED current is given by the internal current mirror ratio (multiplier ? k?) equal to 250. In other words, to get a 25mA maximum, with a 100% full range (ILEDREG = $1F), the reference current should be 25mA/250 = 100 m A. This current is used to calculate the resistor connected between the IREF pin and GND: R REF = 1.144 / 100e?6 = 11.44k W.In any case, no voltage shall be forced at I REF pin, either downward or upward.

The tolerance of the external resistor must be 1% or better, with a 100 ppm thermal coefficient, to get the expected overall tolerance.

Figure 9. Basic Reference Current Source

NOTE:

The I REF pin must never be biased by an external voltage higher than 1144 mV.

The ILED current is given by Table 3 as a percentage of the maximum programmed ILED value (100% will give 25mA when Iref = 100 m A).

Table 3. Output Current (%) versus ILED Step Value

Step # ($)

Iout %Step # ($)

Iout %000.0008 1.4010 6.241827.48010.4209 1.70117.521933.03020.490A 2.00129.111A 39.72030.570B 2.421310.921B 47.72040.720C 2.991413.081C 57.47050.870D 3.631515.801D 69.1806 1.020E 4.351618.971E 83.2007

1.17

5.22

22.86

100.00

0.1

110100

2030Figure 10. Typical Iout (%) versus ILED Step Value

STEP

I o u t (%)

5152535

$01 ILEDREG[0..4] I ?LED Peak Current

B6B5B4B3B2B1B0step ???ILED16ILED8ILED4ILED2ILED1RESET

Bits [B7:B5] : RFU

Bits [B4:B0] : ILED peak current setup

分销商库存信息: ONSEMI

NCP5890MUTXG