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INDEX 2

Important:

In this document, the term “register” refers to both

edge-triggered registers and level-sensitive latches unless

stated otherwise.Both types of sequential cells can now be

retimed. However, the pipeline_design and

balance_register commands can be applied to only

edge-triggered registers in the current release.

This chapter discusses fundamental register retiming concepts. A

good understanding of these concepts will help you make the best

use of the Design Compiler register retiming capabilities.

This chapter contains the following sections:

Basic De?nitions and Concepts ?

Forward Retiming ?Backward Retiming

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CONTENTS INDEX ?

Asynchronous Control Inputs of Registers ?

Synchronous Control Inputs of Registers ?

Multiclass Retiming ?

Pipeline and Nonpipeline Circuits ?Reset State Justi?cation

Basic De?nitions and Concepts

T o understand how register retiming works, you need ?rst to

understand certain basic de?nitions and concepts.In particular,you must understand what sequential generic elements (SEQGENs),

control nets,and register classes are.These are important because during retiming, mapped registers are temporarily replaced by SEQGENs according to their classi?cations as determined by their

control nets.

Note:

In this manual, the terms design, cell, leaf cell, hierarchical cell,

combinational cell, and sequential cell are used in the same

sense as in other Synopsys manuals.

Flip-Flops and Registers

Flip-?op,register,synchronous register,asynchronous register,and latch are familiar terms;however,with respect to register retiming as discussed in this manual,these terms have the following specialized usage:

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INDEX ?A ?ip-?op is an element of a technology library (target library)that

has, unlike the combinational cells, a state and a distinguished

clock input. Flip-?ops can be edge triggered or level sensitive.

?A register is technically an instance of an edge-triggered ?ip-?op

in the design. But for the purposes of this manual, since both

edge-triggered ?ip-?ops and level-sensitive latches can be

retimed, the term register will refer to both types of sequential

devices unless stated otherwise.

?A synchronous register is a register that can change its state only

at the active edge of the clock signal.

?An asynchronous register is a register that, in addition to

changing its state on a clock edge, can also change its state

according to the control levels of asynchronous signals, which

are independent of its clock signal.

A latch is an instance of a level-sensitive ?ip-?op in the design.

Register retiming supports designs with latches and retimes them instead of the registers if the -latch option is used.The essential point here to understand is that ?ip-?ops are

technology library elements, while registers and latches are their

design instances.

SEQGENs

A SEQGEN is a generic sequential element that is used by

Synopsys tools to represent registers and latches in a design.

SEQGENs are created during elaboration and are usually mapped

to ?ip-?ops during compilation. Because mapped ?ip-?ops are

temporarily replaced by SEQGENs during register retiming, it is

important that you understand the basic functionality of these

elements.

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INDEX Figure 2-1 shows the pins that are used when the SEQGEN cell

describes a synchronous or asynchronous register.(Additional pins occur when the SEQGEN is operated as a latch.)

Figure 2-1Relevant Pins of the SEQGEN Cell

In register retiming, the operation of SEQGEN cells is as follows:

?The synchronous toggle pin (ST) has an inactive value of 0.

Therefore, the SEQGEN cell will be retimed only if the ST pin is

connected to a constant net with value 0.

?The clock (CLK) pin is always connected to the clock net of the

design.

?The synchronous state changes occur at the rising edge of the

clock signal.

?If set to 1,the synchronous load (SL)pin enables the next-state

D input to become the next state.The SL pin should be tied to a

constant 1 net when unused.

The synchronous clear (SC)pin sets the state to 0if active.This

pin preempts the SL input and, to be inactive, must be tied to a

constant 0 net.AC

D SC

SS SL

CLK Q QN AC AS D SC SS SL ST CLK : asynch_clear : asynch_set : next_state : synch_clear : synch_set : synch_load : synch_toggle : clocked_on

EN : enable (clock if operated as latch)AD : asynch_data (data if operated as latch)

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CONTENTS INDEX ?The synchronous set (SS)pin sets the state to 1if active.This pin

preempts the SL input and, to be inactive, must be tied to a

constant 0 net.

?If both SC and SS are active,the constant set as an attribute on

the particular SEQGEN instance becomes the new state.

?The asynchronous inputs AC and AS override all settings of the

synchronous inputs;these pins change the state and output of a

SEQGEN instance, independent of the clock input.

?The AC input sets the Q output to 0if active;the AS input sets the

Q output to 1 if active. Both inputs must be 0 to be inactive.?The EN input replaces the CLK clock pin if the SEQGEN cell

operates as a level-sensitive latch.

The AD pin input replaces the D pin input if the SEQGEN cell

operates as a level-sensitive latch.Control Nets

A control net is a net connected to one of the SL,SC,SS,AC,or AS pins of a SEQGEN instance.The equivalence of control nets plays a crucial role in the movement of registers during retiming.

By de?nition, a set of control nets are equivalent if they meet either

of the following conditions:

?All the nets can be reached from a common source,and between

this common source and the SEQGEN instances, all the nets

have an odd number of inverters or all the nets have an even

number of inverters. (A net with no inverters is regarded as

having an even number of inverters.)

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CONTENTS INDEX ?The control nets are constant and have the same constant values

(0 or 1).

Thus, two nonconstant nets with a common source, one that

includes an odd number of inverters and the other an even number

of inverters,are not equivalent nets.Note that any number of buffers is allowed between the common source and the SEQGEN pin of an equivalent net.

Figure 2-2shows an example of equivalent and nonequivalent https://www.wendangku.net/doc/301072645.html,s n1and n3,which have even number of inverters (0and 2),are equivalent, while net n2, which has an odd number of inverters (1),

is not equivalent to either of them.

Figure 2-2Equivalent Control Net Example

The SEQGEN instances are grouped into register classes according to their connections to control nets.Grouping is necessary because only registers belonging to the same group can be moved together

across a combinational gate without violating the circuit logic.

T wo SEQGEN instances belong to the same register class if the

following conditions are ful?lled:AC

D SC

SS SL

CLK Q QN AC AS D SC SS SL ST

CLK Q QN AC AS D SC SS SL ST CLK Q QN n1n2

n3R1R2R3

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INDEX ?

Their SL pins are connected to equivalent control nets.?Their SC and SS pins are connected to equivalent control nets.

That is, a given control net can be connected to the

corresponding SC or SS pins in the SEQGEN instances or to the

SC pin of one SEQGEN instance and to the SS pin of the other.

Their AC and AS pins are connected to equivalent control nets.

The same conditions hold for the asynchronous pins as for the

synchronous pins.Figure 2-3 shows an example in which registers A and B belong to

the same class.

Figure 2-3Swapping of Control Net for Registers in the Same Class

In Figure 2-2 on page 2-6, if all pins not connected to nets n1, n2,

and n3 are connected to their inactive constants, registers R1 and

R3 belong to the same class, but register R2 belongs to a different

class.

When registers belonging to the same class are moved,it is possible to swap their control nets as needed to accomplish the retiming.This swapping capability is true for both synchronous and asynchronous register pins.AC AS D SC SS SL ST

CLK Q QN AC AS D SC SS SL ST

CLK

Q QN n1n2A B

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CONTENTS INDEX Forward Retiming

T o retime forward across a combinational cell, each net in the

immediate fanin of the cell must be driven by the Q pin of a register,and all these registers must belong to the same class. After the

forward retiming move, the registers in the fanout of the cell belong

to the same class as those in the fanin before the move.

Figure 2-4 shows an example of retiming forward across the

combinational cell g1.

Note:

In this and the following sections, the explicit control nets for

registers are not drawn unless there is a special reason to do so.

and C2).

Figure 2-4

Forward Retiming Example Before the retiming move is executed, all the registers in the

immediate fanin of the g1 cell belong to class C1. Notice that after

the move the three registers have been replaced by two registers

belonging to the same class C1. It is not possible to retime forward

the next slice of registers in the fanin of the g1 cell because not all

these registers belong to the same class.Also,after the ?rst retiming,C1

C1C1C2C2C1C1C1C2C2g1

g3C3C3

C3g1g2

g3Before retiming After retiming

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CONTENTS INDEX it is not possible to retime forward the class C1 register that drives

one of the g2cell inputs because only one input pin of the cell has a register driving it.

If during retiming the maximum number of forward retiming moves

across a cell has been performed, the cell has reached its forward

retiming boundary limit.

Backward Retiming

Rules similar to the forward retiming rules govern backward retiming across a combinational cell is possible. All nets in the fanout of a

combinational cell must fan out to the D pin of the registers, and all

these registers must belong to the same class. After the backward

retiming move, the registers in the fanin of the cell belong to the

same class as those in the fanout before the move.

Figure 2-5 shows how the combinational cell g1 can be retimed

backward after the cell g2has been retimed backward.Note that two backward timing moves have been carried out.

Figure 2-5

Backward Retiming Example C1

C1C1C2C2g1

g3C3C3

C1C1C1C1C2C2g1g2

g3C3C3C3C3Before retiming After retiming g2 and then g1

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INDEX If during retiming the maximum possible number of backward

retiming moves across a cell has been performed, the cell has

reached its backward retiming boundary limit.

Asynchronous Control Inputs of Registers

Before the registers of a circuit can be classi?ed for retiming, all of

them have to be represented by SEQGEN cells. For registers with

typical asynchronous set or clear pins, this is a relatively

straightforward and unambiguous procedure. In Figure 2-6, a

into an equivalent SEQGEN instance.(All inputs of the SEQGEN not shown in the ?gure are connected to a constant net with their inactive value.)

Figure 2-6Cell T ransformation With Asynchronous Clear Input

Synchronous Control Inputs of Registers

A register with typical synchronous control inputs can be

represented with an equivalent SEQGEN instance in two ways:D Q CD

AC D CLK

SEQGEN

CLK

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CONTENTS INDEX ?

The synchronous control pins are directly translated to equivalent SEQGEN pins.?The synchronous control nets are transformed through

combinational decomposition of the register.

Translating Synchronous Input Pins to Equivalent

SEQGEN Pins

As with asynchronous pins,this method carries out a straightforward translation of the register pins to equivalent SEQGEN pins of the

SEQGEN cell.Figure 2-7 shows an example of a register with an

active-low synchronous reset signal and an active-high synchronous enable signal. That is, the RST pin has been translated to an

active-low SC pin, and the EN pin has been translated to an

active-high SL pin.

Figure 2-7Cell T ransformation With Synchronous Clear and Enable

Note:

This method of transforming the original registers of a design

leads to multiclass retiming because the resulting SEQGEN

instances will probably not all belong to the same class.D SC SL CLK Q

RST

Q SEQGEN CLK

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INDEX Transforming Synchronous Input Pins Through

Combinational Decomposition

Combinational decomposition transforms synchronous input pins by ?

Using combinational cells to implement the synchronous functionality, and ?Connecting the output of the combinational cells to the D pin of a

SEQGEN cell

Note:

Combinational decomposition can be applied to the synchronous

pins of asynchronous registers.

Figure 2-8 shows the combinational decomposition of the register

example of Figure 2-7.

Figure 2-8T ransformation by Decomposition Example

An advantage of combinational decomposition is that all purely

synchronous registers belong to the same class after they are

transformed to SEQGENs. Consequently, there are no limits to the

number of forward or backward moves possible at multiple input or

output gates due to registers belonging to different classes. Not D

RST

Q D CLK Q SEQGEN EN RST

D CLK 01

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INDEX using decomposition (multiclass retiming)can lead to register class con?icts, which ultimately limit the number of forward or backward

retiming moves possible.

Figure 2-9shows how registers with different enable control nets can be moved forward after decomposition. (To simplify the ?gure, the

clock net is not drawn.) These registers could not be moved after

multiclass retiming.Notice,however,that two D ?ip-?ops remain with the fanouts belonging to synchronous combinational logic and

cannot be forward retimed; the third ?ip-?op is free to move by

forward retiming.

Figure 2-9

Forward Retiming of Decomposed Cells With Load Enable Combinational decomposition can also limit the movability of

registers.Figure 2-10 shows how decomposition applied to a

sequence of two synchronous clear registers leaves the left register without the possibility of a forward move because the newly D Q LE D Q LE

D Q D Q

D Q

Decompose Retime

le1le2

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INDEX introduced AND gate does not have a register at its second port.(The right register is forward retimed through an inverter.)

Alternatively, multiclass retiming allows both registers to move

forward: The right register can be moved across two inverters and

the left register across one buffer.

Figure 2-10Reduced Mobility After Decomposition

Multiclass Retiming

Multiclass retiming can offer signi?cant area savings compared with retiming after decomposition. A multiclass example is shown in

Figure 2-11. The situation is similar to the example in Figure 2-9

except that the two load enable registers belong to the same class

and therefore can be moved across the AND gate,leading to a single https://www.wendangku.net/doc/301072645.html,ing decomposition leads to a higher number of registers and additional cells after retiming.D Q R D Q

R D Q

D Q D Q

D Q D Q R D Q

S Retime (multiclass)

Retime Decompose

No forward move possible

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INDEX Figure 2-11Reduced Area Through Multiclass Retiming

Pipeline and Nonpipeline Circuits

In deciding which retiming method (multiclass or decomposition) to

apply to a design,it is useful to classify circuits or parts of circuits by their topology,as well as by the types,connections,and locations of registers within the design. Circuit topologies can be classi?ed as

pipeline or nonpipeline, as de?ned later in this section.

For pipeline circuits, multiclass retiming is recommended. For

nonpipeline circuits, decomposition or a combination of

decomposition and multiclass retiming works best.

De?ning Pipeline Circuits

Y ou can understand the concept of a pipelined circuit, including

LE D Q

D Q

Decompose

and retime Multiclass

retime

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CONTENTS INDEX Circuit registers can be reached by different paths from the primary data inputs.(A primary data input is an input that does not drive any control pin of a register.) During the transversal of a path, cells are

passed from their input pins to their output pins.

For a particular register, the number of other registers encountered along each path from the primary inputs to the given register can be counted.If this number is independent of the path chosen (that is,the same for every path to the register), each register can be assigned

this number as a register index of the circuit. All registers in such a

circuit that have the same index form a slice .

If all the registers in each slice belong to the same class and if there is the same number of registers on any path from a primary input to a primary output, the circuit is classi?ed as a pipeline . All other

circuits not satisfying this de?nition are de?ned as nonpipelines.

The largest index occurring for the registers in a pipeline plus one is the number of pipeline stages .For example,a pipeline with just one slice of registers has two stages.

Note:

This de?nition of pipeline does not require that registers be

located at the primary outputs or primary inputs.

Figure 2-12and Figure 2-13show examples for pipeline circuits and nonpipeline circuits.

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CONTENTS INDEX Figure 2-12Nonpipeline Circuit Examples

Figure 2-13Pipeline and Nonpipeline Circuit Examples

Reset State Justi?cation

When you move the registers in a circuit,it is not suf?cient to follow only the rules for retiming of a single gate. In addition, it is usually

necessary to preserve an equivalent reset state.

The circuit state is de?ned by the values of all the registers in the

circuit at a given point in time.A circuit and its retimed version have an equivalent state if they produce the same sequences of values at corresponding primary outputs for identical sequences of values at

the corresponding primary inputs.

Not a pipeline Not a pipeline C1C1C1C2C1C1C2

Not a pipeline Pipeline

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CONTENTS INDEX When power is switched on in a circuit, its state is unknown.

Depending on the type of circuit,you might need to have an external reset or set input to reset the registers to a known value. This step

ensures that the circuit has reproducible behavior after the input

becomes active for the ?rst time.

If a circuit is designed this way, by default register retiming ensures

that the reset state of the retimed circuit is equivalent to that of the

original circuit,and that the behavior is identical when a ?nite number of clock cycles has passed after the activation of the reset. If all

registers are properly reset, output sequences should match

immediately.

However, a typical case where the ?rst few output values might not

match is that of a pipelined data path where the registers do not have any set or clear connections.The maximum duration of the mismatch is the number of stages of the pipeline multiplied by the clock period.The computation of the equivalent reset state is called justi?cation .

Justi?cation for registers that have been moved forward across

combinational gates is always possible and does not require

signi?cant amounts of CPU time. Justi?cation for registers moved

backward across combinational gates can be more complicated.

Figure 2-14 shows an example of the dif?culty with backward

justi?cation.

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INDEX Figure 2-14Impossible Backward Justi?cation Example

The numbers inside the register symbols are the given reset values.When the registers are moved to the post-retiming positions,it is not possible to ?nd an equivalent state for the circuit. Register retiming

handles this case by ?nding a position for the registers where an

equivalent state is found that is as close to the optimal position as

possible.

Backward justi?cation also can cost more CPU time than forward

justi?cation.If the circuit to be retimed has a reset but does not need to have an equivalent reset state after retiming, there is a method

available that does not perform justi?cation. This method can be

applied to pipelined data paths, but it is not suitable for controllers.

Y ou can use the -justification_effort option of the

optimize_registers or set_optimize_registers

command to specify the justi?cation effort level during backward

justi?cation. The option can take one of the following values: low,

high,or medium.For more information,see Appendix B,“Command Syntax and Variable Syntax .

Before retiming

After retiming 0

????