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BUK755R2-40B中文资料

BUK75/765R2-40B

TrenchMOS? standard level FET

Rev. 01 — 14 May 2003

Product data

1.Product pro?le

1.1Description

N-channel enhancement mode ?eld-effect power transistor in a plastic package using Philips High-Performance Automotive (HPA) TrenchMOS? technology.Product availability:

BUK755R2-40B in SOT78 (TO-220AB)BUK765R2-40B in SOT404 (D 2-PAK).

1.2Features

1.3Applications

1.4Quick reference data

2.Pinning information

[1]

It is not possible to make connection to pin 2 of the SOT404 package.

s TrenchMOS? technology s Q101 compliant

s 175°C rated

s Standard level compatible.

s Automotive systems

s 12 V loads

s Motors, lamps and solenoids

s General purpose power switching.

s E DS(AL)S ≤494mJ s R DSon =4.4m ?(typ)s I D ≤75A

s P tot ≤203W.

Table 1:Pinning - SOT78 and SOT404, simpli?ed outlines and symbol Pin Description Simpli?ed outline

Symbol

1gate (g)SOT78 (TO-220AB)

SOT404 (D 2-PAK)

2drain (d)[1]

3source (s)mb

mounting base,connected to drain (d)

MBK106

12mb

MBK116

MBB076

3.Limiting values

[1]Current is limited by power dissipation chip rating.[2]Continuous current is limited by package.

Table 2:Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max Unit V DS drain-source voltage (DC)-40V V DGR drain-gate voltage (DC) R GS =20k ?

-40V V GS gate-source voltage (DC)-±20V I D

drain current (DC)

T mb =25°C; V GS =10V;Figure 2and 3

[1]-143A [2]-75A T mb =100°C; V GS =10V;Figure 2

[2]

-75A I DM peak drain current T mb =25°C; pulsed; t p ≤10μs;Figure 3

-573A P tot total power dissipation T mb =25°C;Figure 1

-203W T stg storage temperature ?55+175°C T j junction temperature ?55+175°C Source-drain diode

I DR reverse drain current (DC)T mb =25°C

[1]-143A [2]-75A I DRM

peak reverse drain current

T mb =25°C; pulsed; t p ≤10μs -573A Avalanche ruggedness

E DS(AL)S non-repetitive drain-source avalanche

energy

unclamped inductive load; I D =75A;V DS ≤40V; V GS =10V; R GS =50?;starting T mb =25°C

494

V GS ≥4.5V

Fig 1.Normalized total power dissipation as a function of mounting base temperature.Fig 2.Continuous drain current as a function of

mounting base temperature.

T mb =25°C; I DM single pulse.

Fig 3.Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03na19

040

1200

100

150

200

T mb (°C)

P der (%)

03nj26

050

100

150

100

150

200

T mb (°C)

I D (A)Capped at 75 A due to package

P der P tot

P tot 25C °

()

-----------------------100%

×=03nj24

102

103 10-1

1 10

102

V DS (V)

I D (A)

100 ms

10 ms Limit R DSon = V DS /I D

1 ms

t p = 10 μs

100 μs

Capped at 75 A due to package

4.Thermal characteristics

4.1Transient thermal impedance

Table 3:Thermal characteristics

Symbol Parameter

Conditions Min Typ Max Unit R th(j-mb)thermal resistance from junction to mounting base

Figure 4

--0.74K/W

R th(j-a)

thermal resistance from junction to ambient

SOT78 package vertical in still air

-60-K/W SOT404 package

minimum footprint; mounted on a PCB

-50

-K/W

Fig 4.Transient thermal impedance from junction to mounting base as a function of pulse duration.

03nj25

single shot

0.2

0.10.050.02

10-3

10-2

10-1

1 10-6

10-5

10-4

10-3

10-2

10-1

t p (s)

Z th(j-mb) (K/W)

δ = 0.5

t p

t p T P

δ =

5.Characteristics

Table 4:Characteristics

T j=25°C unless otherwise speci?ed.

Symbol Parameter Conditions Min Typ Max Unit Static characteristics

V(BR)DSS drain-source breakdown

voltage I D=0.25mA; V GS=0V

T j=25°C40--V T j=?55°C36--V

V GS(th)gate-source threshold voltage I D=1mA; V DS=V GS;Figure9

T j=25°C234V

T j=175°C1--V

T j=?55°C-- 4.4V I DSS drain-source leakage current V DS=40V; V GS=0V

T j=25°C-0.021μA

T j=175°C--500μA I GSS gate-source leakage current V GS=±20V; V DS=0V-2100nA

R DSon drain-source on-state

resistance V GS=10V; I D=25A;

Figure7and8

T j=25°C- 4.4 5.2m?T j=175°C--9.9m?

Dynamic characteristics

Q g(tot)total gate charge V GS=10V; V DD=32V;

I D=25A;Figure14-52-nC

Q gs gate-source charge-12-nC Q gd gate-drain (Miller) charge-16-nC

C iss input capacitance V GS=0V; V DS=25V;

f=1MHz;Figure12-28423789pF

C oss output capacitance-711853pF C rss reverse transfer capacitance-296406pF

t d(on)turn-on delay time V DD=30V; R L=1.2?;

V GS=10V; R G=10?-15-ns

t r rise time-51-ns t d(off)turn-off delay time-81-ns t f fall time-56-ns L d internal drain inductance from drain lead 6mm from

package to center of die

- 4.5-nH

from contact screw on

mounting base to center of die

SOT78

- 3.5-nH

from upper edge of drain

mounting base to center of die

SOT404

- 2.5-nH

L s internal source inductance from source lead to source

bond pad

-7.5-nH

Source-drain diode

V SD source-drain (diode forward)voltage

I S =25A; V GS =0V;Figure 15

-0.85 1.2V t rr reverse recovery time I S =20A; dI S /dt =?100A/μs V GS =?10V; V DS =20V

-54-ns Q r

recovered charge

-38

-nC

Table 4:Characteristics …continued T j =25°C unless otherwise speci?ed.Symbol Parameter

Conditions Min Typ Max Unit

T j =25°C; t p =300μs T j =25°C; I D =25A

Fig 5.Output characteristics: drain current as a

function of drain-source voltage;typical values.Fig 6.Drain-source on-state resistance as a function

of gate-source voltage; typical values.

T j =25°C

Fig 7.Drain-source on-state resistance as a function

of drain current; typical values.

Fig 8.Normalized drain-source on-state resistance factor as a function of junction temperature.

03nk19

0100

200

300

4000

V DS (V)

I D (A)8.587.5

76.5

65.5

54.5

20149

9.5

1012

label is V GS (V)

03nk18

185

V GS (V)

R DSon (m ?)

03nk20

100

200

300

400

I D (A)

R DSon (m ?)

678

label is V GS (V)

03aa27

00.5

1.5

2-60

120

180

T j (°C)

a a R

DSon R DSon 25C °()

----------------------------=

I D =1mA; V DS =V GS T j =25°C; V DS =V GS

Fig 9.Gate-source threshold voltage as a function of

junction temperature.Fig 10.Sub-threshold drain current as a function of

gate-source voltage.

T j =25°C; V DS =25V V GS =0V; f =1MHz

Fig 11.Forward transconductance as a function of

drain current; typical values.

Fig 12.Input,output and reverse transfer capacitances

as a function of drain-source voltage; typical values.

03aa32

5-60

120

180

T j (°C)

V GS(th) (V)

max

min

typ

03aa35

10-6

10-5

10-4

10-3

10-2

10-10

V GS (V)

I D (A)max

typ min 03nk16

02040

800

I D (A)

g fs (S)03nk21

1000

2000

3000

4000 10-1

1 10

102

V DS (V)

C (pF)C iss

C oss

C rss

V DS =25V T j =25°C; I D =25A

Fig 13.Transfer characteristics: drain current as a

function of gate-source voltage; typical values.Fig 14.Gate-source voltage as a function of gate

charge; typical values.

V GS =0V

Fig 15.Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.

03nk17

025

1000

V GS (V)

I D (A)T j = 175 °C

T j = 25 °C

03nk15

100

Q G (nC)

V GS (V)

V DD = 14 V

V DD = 32 V

03nk14

025

1000.0

0.3

0.6

0.9

1.2

V SD (V)

I S (A)T j = 175 °C

T j = 25 °C

6.Package outline

REFERENCES

OUTLINE VERSION EUROPEAN PROJECTION

ISSUE DATE IEC

JEDEC EIAJ SOT78

SC-46

3-lead TO-220AB

D 1

123

L 1(1)

b 1

e e

0510 mm

scale

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB

SOT78

DIMENSIONS (mm are the original dimensions)A E A 1

Note

1. Terminals in this zone are not tinned.

L 2

UNIT A 1b 1D 1e p mm

2.54

q Q A b D c L 2max.3.0

3.83.6

15.013.5

3.302.79

3.02.7

2.62.2

0.70.4

15.815.2

0.90.7

1.31.0

4.54.1

1.391.27

6.45.9

10.39.7

L 1(1)E L 00-09-0701-02-16

mounting base

UNIT A REFERENCES

OUTLINE VERSION EUROPEAN PROJECTION

ISSUE DATE IEC

JEDEC

EIAJ

A 1D 1D max.E e L p H D Q c 2.54

2.602.20

15.8014.80

2.902.10

1.601.20

10.309.70

4.504.10

1.401.27

0.850.60

0.640.46

b DIMENSIONS (mm are the original dimensions) SOT404

0 2.5 5 mm

scale

Plastic single-ended surface mounted package (Philips version of D 2-PAK); 3 leads (one lead cropped)

SOT404

e e

D 1

H D

L p

c A 1

mounting base

99-06-2501-02-12

7.Soldering

Dimensions in mm.

Fig 18.Re?ow soldering footprint for SOT404.

handbook, full pagewidth

MSD057

solder lands solder resist occupied area solder paste

10.50

7.40

7.501.50

1.70

10.60 1.201.301.55

5.08

10.850.30

2.15

8.35

2.254.60

0.20

3.00

4.85

7.95

8.158.075

8.275

5.40

1.50

8.Revision history

Table 5:Revision history

Rev Date CPCN Description

0120030514-Product data (9397 750 11233)

9.Data sheet status

[1]Please consult the most recently issued data sheet before initiating or completing a design.

[2]The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL https://www.wendangku.net/doc/3c2386752.html,.

[3]For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

10.De?nitions

Short-form speci?cation —The data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values de?nition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speci?cation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation.

11.Disclaimers

Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Noti?cation (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products,and makes no representations or warranties that these products are free from patent,copyright,or mask work right infringement,unless otherwise speci?ed.

12.Trademarks

TrenchMOS —is a trademark of Koninklijke Philips Electronics N.V.

Level Data sheet status[1]Product status[2][3]De?nition

I Objective data Development This data sheet contains data from the objective speci?cation for product development. Philips

Semiconductors reserves the right to change the speci?cation in any manner without notice.

II Preliminary data Quali?cation This data sheet contains data from the preliminary speci?cation.Supplementary data will be published

at a later date.Philips Semiconductors reserves the right to change the speci?cation without notice,in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speci?cation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design,manufacturing and supply.Relevant

changes will be communicated via a Customer Product/Process Change Noti?cation (CPCN).

Contact information

? Koninklijke Philips Electronics N.V .2003.Printed in The Netherlands

All rights are reserved.Reproduction in whole or in part is prohibited without the prior Contents

1Product pro?le . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4Quick reference data. . . . . . . . . . . . . . . . . . . . . 12Pinning information. . . . . . . . . . . . . . . . . . . . . . 13Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 24Thermal characteristics. . . . . . . . . . . . . . . . . . . 44.1T ransient thermal impedance . . . . . . . . . . . . . . 45Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56Package outline . . . . . . . . . . . . . . . . . . . . . . . . 107Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Revision history. . . . . . . . . . . . . . . . . . . . . . . . 139Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 1410De?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14