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74AHCT30中文资料

DATA SHEET

Product speci?cation

File under Integrated Circuits, IC061999Nov30

INTEGRATED CIRCUITS 74AHC30; 74AHCT30 8-input NAND gate

8-input NAND gate

74AHC30; 74AHCT30

FEATURES

?ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V CDM EIA/JESD22-C101 exceeds 1000V ?Balanced propagation delays

?Inputs accept voltages higher than V CC

?For AHC only: operates with CMOS input levels ?For AHCT only: operates with TTL input levels ?Output capability: standard ?I CC category: SSI

?Specified from ?40to +85°C and ?40to +125°C.DESCRIPTION

The 74AHC/AHCT30 are high-speed Si-gate CMOS

devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no.7A.

The 74AHC/AHCT30 provide the 8-input NAND function.

QUICK REFERENCE DATA

GND =0V; T amb =25°C; t r =t f ≤3.0ns.

Notes

1.C PD is used to determine the dynamic power dissipation (P D in μW).

P D =C PD ×V CC 2×f i +∑(C L ×V CC 2×f o )where:f i =input frequency in MHz;f o =output frequency in MHz;∑(C L ×V CC 2×f o )=sum of outputs;C L =output load capacitance in pF;V CC =supply voltage in Volts.2.The condition is V I =GND to V CC .

SYMBOL PARAMETER

CONDITIONS TYPICAL UNIT AHC AHCT t PHL /t PLH propagation delay

A,B,C,D,E,F ,G,H to Y C L =15pF; V CC =5V

3.6 3.3ns C I input capacitance 3.0 3.0pF C O output capacitance

4.0 4.0pF C PD power dissipation capacitance

C L =50pF; f =1MHz;notes 1and 2

8-input NAND gate74AHC30; 74AHCT30

FUNCTION TABLE

See note1.

Note

1.H=HIGH voltage level;

L=LOW voltage level;

X=don’t care. ORDERING INFORMATION

PINNING INPUTS OUTPUTS

A B C D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H HΗH L

TYPE NUMBER

PACKAGES

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

74AHC30D?40to+125°C14SO plastic SOT108-1 74AHCT30D14SO plastic SOT108-1 74AHC30PW14TSSOP plastic SOT402-1 74AHCT30PW14TSSOP plastic SOT402-1

PIN SYMBOL DESCRIPTION

1A data input

2B data input

3C data input

4D data input

5E data input

6F data input

7GND ground (0V)

8Y data output

9,10and13n.c.not connected

11G data input

12H data input

14V CC DC supply voltage

8-input NAND gate 74AHC30; 74AHCT30

handbook, halfpage

MNA487

1234567

814131211109

A B C D E F GND

n.c.

n.c.G H

n.c.V CC Fig.1 Pin configuration.handbook, halfpage

MNA488

A Y 18

B 2

C 3

D 4

E 5

F 6

G 11H

Fig.2 Functional diagram.

handbook, halfpage

MNA489

1234561112

Fig.3 IEC logic symbol.handbook, halfpage

A C D

G H

MNA490

Fig.4 Logic diagram.

8-input NAND gate

74AHC30; 74AHCT30

RECOMMENDED OPERATING CONDITIONS LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground =0V).Notes

1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.For SO-packages: above 70°C the value of P D derates linearly with 8mW/K.

For TSSOP-packages: above 60°C the value of P D derates linearly with 5.5mW/K.

SYMBOL PARAMETER CONDITIONS

74AHC 74AHCT

UNIT MIN.TYP .MAX.MIN.TYP .MAX.V CC DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5V V I input voltage 0? 5.50? 5.5V V O output voltage 0

?V CC 0?V CC V T amb

operating ambient temperature

see DC and AC characteristics per device ?40+25+85?40+25+85°C ?40+25+125?40+25+125°C t r ,t f (?t/?f)input rise and fall rates

V CC =3.3±0.3V ??100???ns/V

V CC =5±0.5V

SYMBOL PARAMETER

CONDITIONS

MIN.MAX.UNIT V CC DC supply voltage ?0.5+7.0V V I input voltage

?0.5+7.0V I IK DC input diode current V I

??20mA I OK DC output diode current V O V CC +0.5V; note 1?±20mA I O DC output source or sink current ?0.5V

?±25mA I CC DC V CC or GND current ?±75mA T stg storage temperature

?65+150°C P D power dissipation per package

for temperature range from ?40to +125°C; note 2?

500

8-input NAND gate74AHC30; 74AHCT30

DC CHARACTERISTICS

Family 74AHC

Over recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER TEST CONDITIONS T amb(°C)

UNIT OTHER V CC(V)

25?40to+85?40to+125

MIN.TYP.MAX.MIN.MAX.MIN.MAX.

V IH HIGH-level input

voltage 2.0 1.5?? 1.5? 1.5?V

3.0 2.1?? 2.1? 2.1?V 5.5 3.85?? 3.85? 3.85?V

V IL LOW-level input

voltage 2.0??0.5?0.5?0.5V

3.0??0.9?0.9?0.9V 5.5?? 1.65? 1.65? 1.65V

V OH HIGH-level output

voltage V I=V IH or V IL

I O=?50μA 2.0 1.9 2.0? 1.9? 1.9?V I O=?50μA 3.0 2.9 3.0? 2.9? 2.9?V I O=?50μA 4.5 4.4 4.5? 4.4? 4.4?V I O=?4.0mA 3.0 2.58?? 2.48? 2.40?V I O=?8.0mA 4.5 3.94?? 3.8? 3.70?V

V OL LOW-level output

voltage V I=V IH or V IL

I O=50μA 2.0?00.1?0.1?0.1V I O=50μA 3.0?00.1?0.1?0.1V I O=50μA 4.5?00.1?0.1?0.1V I O=4.0mA 3.0??0.36?0.44?0.55V I O=8.0mA 4.5??0.36?0.44?0.55V

I I input leakage

current

V I=V CC or GND 5.5??0.1? 1.0? 2.0μA

I OZ3-state output

OFF current V I=V IH or V IL;

V O=V CC or GND

5.5??±0.25?±2.5?±10.0μA

I CC quiescent supply

current V I=V CC or GND;

I O=0

5.5?? 2.0?20?40μA

C I input capacitance??310?10?10pF

8-input NAND gate74AHC30; 74AHCT30

Family 74AHCT

Over recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER TEST CONDITIONS T amb(°C)

UNIT OTHER V CC(V)

25?40to+85?40to+125

MIN.TYP.MAX.MIN.MAX.MIN.MAX.

V IH HIGH-level input

voltage

4.5to

5.5 2.0?? 2.0? 2.0?V

V IL LOW-level input

voltage

4.5to

5.5??0.8?0.8?0.8V

V OH HIGH-level output

voltage V I=V IH or V IL

I O=?50μA 4.5 4.4 4.5? 4.4? 4.4?V I O=?8.0mA 4.5 3.94?? 3.8? 3.70?V

V OL LOW-level output

voltage V I=V IH or V IL

I O=50μA 4.5?00.1?0.1?0.1V I O=8.0mA 4.5??0.36?0.44?0.55V

I I input leakage

current

V I=V IH or V IL 5.5??0.1? 1.0? 2.0μA

I OZ3-state output

OFF current V I=V IH or V IL;

V O=V CC or GND

per input pin;

other inputs at

V CC or GND;

I O=0

5.5??±0.25?±2.5?±10.0μA

I CC quiescent supply

current V I=V CC or GND;

I O=0

5.5?? 2.0?20?40μA

?I CC additional

quiescent supply

current per input

pin V I=V CC?2.1V;

other inputs at

V CC or GND;

I O=0

4.5to

5.5?? 1.35? 1.5? 1.5mA

C I input capacitance??310?10?10pF

8-input NAND gate

74AHC30; 74AHCT30

AC CHARACTERISTICS Type 74AHC30

GND =0V; t r =t f ≤3.0ns.

Notes

1.Typical values at V CC =3.3V.

2.Typical values at V CC =5.0V.Type 74AHCT30

GND =0V; t r =t f ≤3.0ns.

Note

1.Typical values at V CC =5.0V.

SYMBOL

PARAMETER

TEST CONDITIONS

T amb (°C)UNIT

WAVEFORMS

C L

?40to +85?40to +125MIN.

TYP .

MAX.

MIN.

MAX.

MIN.

MAX.

V CC =3.0to 3.6V;note 1t PHL /t PLH

propagation delay A,B,C,D,E,F ,G,H to Y

see Figs 5and 615pF ?

5.09.5 1.011.0 1.012.0ns 50pF ?

6.7

12.0

1.0

14.5

1.0

15.5

V CC =4.5to 5.5V;note 2t PHL /t PLH

propagation delay A,B,C,D,E,F ,G,H to Y

see Figs 5and 615pF ?

3.6 6.5 1.07.5 1.08.0ns 50pF ?

4.9

8.0

1.0

9.5

1.0

10.5

SYMBOL

PARAMETER

TEST CONDITIONS

T amb (°C)UNIT

WAVEFORMS

C L

?40to +85

?40to +125MIN.

TYP.

MAX.MIN.

MAX.

MIN.MAX.

V CC =4.5to 5.5V;note 1t PHL /t PLH

propagation delay A,B,C,D,E,F ,G,H to Y

see Figs 5and 615pF ?

3.3 6.5 1.07.5 1.08.0ns 50pF ?

4.7

8.5

1.0

9.5

1.0

10.5

8-input NAND gate

74AHC30; 74AHCT30

AC WAVEFORMS

handbook, halfpage

MNA491

t PHL t PLH

V M

A, B, C, D,E, F , G, H input

Y output

Fig.5 The input (A, B, C, D, E, F, G and H) to output (Y) propagation delays.

FAMILY V I INPUT REQUIREMENTS V M INPUT V M OUTPUT AHC GND to V CC 50%V CC 50%V CC AHCT

GND to 3.0V

1.5V

50%V CC

Fig.6 Test circuitry for switching times.

TEST S1t PLH /t PHL open t PLZ /t PZL V CC

t PHZ /t PZH

GND

handbook, full pagewidth

open GND

V CC V CC

V I

V O

MNA183

D.U.T.C L

R T

1000 ?

PULSE GENERATOR

Definitions for test circuit:

C L =load capacitance including jig and probe capacitance (See Chapter “AC characteristics”);R T =termination resistance should be equal to the output impedance Z o of the pulse generator.

8-input NAND gate74AHC30; 74AHCT30 PACKAGE OUTLINES

UNIT

max.A1A2A3b p c D

(1)E(1)(1)

e H E L L p Q Z

vθ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE IEC JEDEC EIAJ

mm inches 1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.38

0.250.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4

SOT108-1

w M

b p

H E

L p

detail X

v M A

(A )3

076E06S MS-012AB

pin 1 index

0.0690.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.35

0.34

0.16

0.15

0.050

1.05

0.041

0.244

0.228

0.028

0.024

0.028

0.012

0.01

0.25

0.010.004

0.039

0.016

95-01-23

97-05-22

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

8-input NAND gate 74AHC30; 74AHCT30

UNIT A 1A 2A 3b p c D (1)E (2)(1)e H E L L p Q Z y w v θ REFERENCES

OUTLINE VERSION EUROPEAN PROJECTION

ISSUE DATE IEC

JEDEC EIAJ

0.150.05

0.950.80

0.300.19

0.20.1

5.14.9

4.54.3

0.65

6.66.2

0.40.3

0.720.38

80o

0.13

0.1

0.2

1.0

DIMENSIONS (mm are the original dimensions)Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.750.50

SOT402-1

MO-153

94-07-1295-04-04

w M

b p

D Z

0.25

148

A 1

A 2

L p Q

detail X

(A )3

H E

E c

v M A

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.1.10

pin 1 index

8-input NAND gate74AHC30; 74AHCT30

SOLDERING

Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in our“Data Handbook IC26; Integrated Circuit Packages”(document order number 939865290011).

There is no soldering method that is ideal for all surface mount IC packages.Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.

Re?ow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles,flux and binding agent)to be applied to the printed-circuit board by screen printing,stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times(preheating,soldering and cooling)vary between 100and200seconds depending on heating method.

Typical reflow peak temperatures range from

215to250°C. The top-surface temperature of the packages should preferable be kept below 230°C. Wave soldering

Conventional single wave soldering is not recommended for surface mount devices(SMDs)or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.If wave soldering is used the following conditions must be observed for optimal results:

?Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

?For packages with leads on two sides and a pitch (e):–larger than or equal to 1.27mm, the footprint longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

–smaller than 1.27mm, the footprint longitudinal axis must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

?For packages with leads on four sides,the footprint must be placed at a45°angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering,the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4seconds at 250°C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end https://www.wendangku.net/doc/395055981.html,e a low voltage(24V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10seconds at up to 300°C.

When using a dedicated tool, all other leads can be soldered in one operation within 2to5seconds between 270and320°C.

8-input NAND gate 74AHC30; 74AHCT30

Suitability of surface mount IC packages for wave and re?ow soldering methods

Notes

1.All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect).For details,refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.2.These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).3.If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.4.Wave soldering is only suitable for LQFP,TQFP and QFP packages with a pitch (e)equal to or larger than 0.8mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm.5.Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e)equal to or larger than 0.65mm;it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5mm.DEFINITIONS LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

PACKAGE

SOLDERING METHOD WAVE

REFLOW (1)

BGA, LFBGA, SQFP , TFBGA

not suitable suitable HBCC, HLQFP , HSQFP , HSOP , HTQFP , HTSSOP , SMS not suitable (2)suitable PLCC (3), SO, SOJ suitable

suitable LQFP , QFP , TQFP not recommended (3)(4)suitable

SSOP , TSSOP , VSO not recommended (5)

suitable

Data sheet status Objective speci?cation This data sheet contains target or goal speci?cations for product development.Preliminary speci?cation This data sheet contains preliminary data; supplementary data may be published later.Product speci?cation This data sheet contains ?nal product speci?cations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speci?cation is not implied. Exposure to limiting values for extended periods may affect device reliability.Application information

Where application information is given, it is advisory and does not form part of the speci?cation.

8-input NAND gate74AHC30; 74AHCT30

NOTES

8-input NAND gate74AHC30; 74AHCT30

NOTES

? Philips Electronics N.V.SCA All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract,is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Internet: https://www.wendangku.net/doc/395055981.html,

1999

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Printed in The Netherlands

245002/01/pp 16 Date of release:1999Nov 30

Document order number: 939775006465