Phase Change Memory Technology for Embedded Non Volatile

Phase Change Memory Technology for Embedded Non Volatile Memory Applications for 90nm and Beyond
R.Annunziata1, P.Zuliani1, M.Borghi1, G. De Sandre1, L.Scotti1, C.Prelini1, M.Tosi2, I.Tortorelli2 and F.Pellizzer2 1. STMicroelectronics, Via C.Olivetti 2, 20041 Agrate Brianza (Milan), Italy 2. Numonyx, Via C.Olivetti 2, 20041 Agrate Brianza (Milan), Italy Tel.: +39-039-6035412, E-mail: roberto.annunziata@https://www.wendangku.net/doc/3812334048.html, Abstract A 90nm embedded PCM technology is presented. For the first time the storage element has been integrated in a 6-ML advanced CMOS platform, exploiting the LV n-mos device as cell selector. Very good cell working window and intrinsic reliability both for storage element and selector MOS have been proven. The full integration of a 4Mb ePCM macrocell with very few additional masks and minimal process tuning confirms this technology as a viable solution for floating gate non-volatile memory replacement in embedded applications. Introduction In the last few years a large effort both from academics and industry side has been focused on Phase Change Memory (PCM) as the most promising candidate for floating gate memories replacement (1). Intrinsic electrical properties of chalcogenide-based PCM devices, like fast programming, good read window, bit alterability, low voltage operation, make them suitable both for stand-alone and embedded applications (Tab.1). Aim of this work is to present a 90nm PCM technology for embedded non-volatile memory applications such as Smart Cards and industrial microcontrollers. A 1T/1R MOS-selected PCM cell with Ge2Sb2Te5 (GST) storage material has been chosen as the best solution in terms of additional masks count and process simplicity. The full integration of a 4Mb ePCM macrocell on advanced 90nm CMOS platform has been successfully achieved with solid results in terms of functionality, stability and reliability. ePCM Cell and Process Architecture The process baseline for 90nm ePCM technology is an advanced CMOS platform with 2 gate oxides and 6 copper metal levels (Tab.2). The PCM storage element, integrated in the pre-metal dielectric, is the same developed for 90nm stand-alone technology (2,3). The cell selector is the standard Low Voltage (LV) MOS device (Fig.1,2). This is the most convenient solution for embedded applications, since no dedicated development for selector device is required. Neither additional oxides integration nor specific high voltage devices are needed. Only three additional masks are used for the definition of the memory element, making this solution very effective in terms of technology development and process cost. A competitive cell area (Tab.1) with respect to conventionally available embedded non-volatile memory has been obtained at the 90nm node, with additional advantages at macrocell level given by the low voltage operation. In reading it is possible to limit bit-line (BL) and word-line (WL) voltage swing below standard biasing conditions of LV devices. In programming higher voltages are needed but still within the operating range of Medium Voltage (MV) devices. Cell layout scheme with double MOS selector (Fig.3) allows very regular active area patterning in memory array, resulting in simpler process integration. Advanced CMOS Platform Compatibility Since the PCM module is integrated between the front-end and the back-end of the CMOS process, the compatibility of the memory integration with the advanced logic must be carefully analyzed. A thicker pre-metal dielectric is needed to allocate the PCM element and a stacked contact becomes mandatory everywhere in the circuitry. Moreover, slight modifications in the back-end flow have been introduced to reduce the thermal budget, in order to guarantee GST integrity. Trans-characteristics of typical LV n-MOS (Fig.4) demonstrate very small impact of the PCM process module integration. This is confirmed by the transistor mismatch evaluations (Fig.5) that give comparable results with respect to the CMOS baseline. Timing evaluations on CMOS test vehicles complement the analysis with wider statistical coverage of transistor dynamic characteristics and back-end capacitive effects. Monitor on several lots of SRAM access time and ring oscillator frequency (Fig.6) shows good alignment with the standard CMOS process. Experimental Results The electrical validation of PCM integrated for the first time in 6 metal levels CMOS technology has been carried out both on the analytical memory element and on 4Mbit macrocell. Full assessment of operating range and reliability requirements of LV MOS used as PCM selector has been achieved. To guarantee sufficient driving capability the cell selector, properly sized, must be biased beyond LV MOS safe operating area (Vg ≈ 2.6V). It has been proven that MOS selector can be forced in these extreme working conditions thanks to very fast Set and
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Reset operations (Fig.7) (4). No issues related to thin gate oxide degradation have been observed, with voltages up to 3V on selector gate (unselected BL) and on selector drain (unselected WL). Proper selector sizing for write operation yields high conductance in read conditions. This is particularly convenient to guarantee a very large sensing window (Fig.8). Reset current shown in the programming curve is in line with the 90nm stand-alone technology (2). Extended endurance of PCM cell has been demonstrated on fully integrated devices and the potential impact of 6 metal levels process on cell reliability has been evaluated with positive results (Fig.9). The robustness of ePCM integration is demonstrated by the characterization results of 4Mbit macrocell (Fig.10). Set and Reset current distributions over the whole array are shown in Fig.11. Wide read window of about 25μA, with sharp Reset distribution, confirms the intrinsic conductance difference between Set and Reset states. The 4Mbit macrocell has been used to assess the retention behavior. Accelerated retention tests over 1Gbit data sample, equivalent to 10 years storage at 85°C (2), give an extrinsic single bit defectivity of about 2ppm at read reference level with margin (Fig.12). Such single bit defectivity is fully recoverable by ECC. Conclusions For the first time the PCM process module has been integrated in a 90nm 6-ML advanced CMOS platform, exploiting the LV n-mos device as cell selector. The process architecture and the electrical results from analytical cell and multi-Mbit array have been presented. Very good cell working window and intrinsic reliability (endurance and retention) both for storage element and selector MOS, suitable for consumer range applications have been proven. The integration of a 4Mbit PCM macrocell on advanced CMOS platform with very few additional masks and minimal process tuning confirmed this technology is a viable solution for floating gate non-volatile memory replacement in embedded applications. Acknowledgements The authors would like to acknowledge colleagues in ST and Numonyx Technology Development teams for valuable support and contributions in testing and characterization. References (1) https://www.wendangku.net/doc/3812334048.html,i “Current status of the Phase Change Memory and its Future”, IEDM Tech. Dig., 2003. (2) F.Pellizzer et al., “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications” VLSI 2006. (3) A.Pirovano et al., “Self-Aligned uTrench Phase-Change Memory Cell Architecture for 90nm Technology and Beyond”, Proc. ESSDERC 2007 (4) G. De Sandre et al., “Program Circuit for a Phase Change Memory Array with 2 MB/s Write Throughput for Embedded Applications”, Proc. ESSCIRC 2008
EEPROM
Cell size (λ2) Erase block Erase time (Set) Program time (Reset) Program voltage (V) Writing current/bit Endurance Retention
111 byte 1ms 1ms 15 <1μA 500K 150C
FLASH 27 page 1ms 5μs 10 50μA 100K 150C
ePCM 36 bit 300ns 100ns 4 400μA 1M 85C
Table 1. Embedded NVM cells benchmark at 90nm node. For Flash, page erasable architecture is considered.
Lithography Isolation Gate oxide Gate type Interconnects
90nm 350nm Shallow Trench LV=2.1nm, MV=6.5nm Dual-flavor poly & CoSi2 6 Cu
Table 2. CMOS technology parameters.
Metal1
V0 heater
0
heater WLn
Metal0
SL
WL(n+1)
BL
WL(n+1)
SL
BL
WLn
SL
A
Fig.1 Schematic cross section of the MOS-selected PCM cell. Two transistors in parallel address the same storage element and common source is biased by local interconnect.
A’
Fig.2 Array cross section (Bit Line direction).
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Source Line Word Line Heater pre-contact
F q e c [M z re u n y H ]
10 8 6 4 2
CMOS
ePCM
Ring Oscillator Frequency Lots
Source Line
5.0
Active area
A c s tim [n ] ces e s
4.0
CMOS
ePCM
Fig.3 Schematic layout of the MOS-selected PCM cell. Double MOS selector allows active area patterning in stripes parallel to bit lines.
3.0
2.0
1.0
SRAM access time Lots
1.E-03 1.E-04 1.E-05 Id [A] (SS) 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 0 0.2 0.4 0.6 Vg [V] 0.8 1 1.2 CMOS process ePCM process
500 450 400 300 250 200 150 100 50 0 Id [μA] (linear) 350
Fig.6 Timing evaluations by ring oscillators frequency and SRAM access time. Values are well aligned between lots processed with ePCM and standard CMOS flow.
1.E+06
Rset [Ohm]
1.E+05
1.E+04
Fig.4 Comparison of trans-characteristics of typical LV n-MOS, processed with CMOS and ePCM flow.
1.E+03 0 100 200 300 400 500 600 700 800 900 1000 t set pulse [ns]
0.0040 0.0035 0.0030 CMOS
NMOS
Fig.7 Set level as function of trailing pulse length. Due to fast Set/Reset, the LV mos selector can operate with no issue of thin oxide degradation.
ePCM
60 50
PMOS
σ ( Δ Vt) [V]
0.0025 0.0020 0.0015 0.0010 0.0005 0.0000 Lot1
Iread [μA]
40 30 20 10 0
Lot2
Lot3
Lot4
0
50 100 150 200 250 300 350 400 450 500 550 600 650 700
Ireset [μA]
Fig.5 Threshold voltage mismatch of LV transistors. Very similar results are obtained with CMOS and ePCM flow.
Fig.8 Read current as function of Reset current. Proper selector sizing for write operation guarantees very large sensing window.
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1.E+07
2 ML integrated
Resistance [Ohm] 1.E+06
1.E+05
Reset % of cells
1.E+04
Set
1.E+03 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Cycles
1.E+07
6 ML integrated
Resistance [Ohm] 1.E+06
1.E+05
0
10
20
30
40
50
60
70
Read Current [uA]
1.E+04
1.E+03 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Cycles
Fig.11 4Mb macrocell Reset/Set cumulative distributions. Wide read window is confirmed on large ePCM array.
Fig.9 Analytic cell endurance: no major difference between ePCM integrated with 2 or 6 metal levels.
1.E+09 1.E+08 1.E+07 1.E+06
PreBake 10 yrs at 55C 10 yrs at 85C
# o f c e lls
1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 0 2 4 6 8 10 12 14 16 18 20
2 ppm
Read Current [μA]
Fig.10 4Mbit embedded PCM macrocell. Memory array is evident in the central portion of the picture.
Fig.12 Accelerated retention test, equivalent to 10 years storage at 85°C, performed on ePCM macrocell for a total amount of 1Gbit data sample. Extrinsic defectivity is recovered by ECC.
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