外文资料翻译 --AT89S52单片机简介
外文文献及翻译
A brief introduction of AT89S52
2.Pin Description
2.1 VCC: Supply voltage.
2.2 GND: Ground.
2.3 Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
2.4 Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pulled-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) Because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOBX@DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX@RI),Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
2.6 Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown
running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.
2.8 ALE/PROG: Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program
pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 or SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
2.9 PSEN: Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
2.10 EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
2.11 XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
2.12 XTAL2: Output from the inverting oscillator amplifier.
3.Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.
3.1 Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.
3.2 Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
4.Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except though reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
5.UART
The UART in the AT89S52 operates the same way as the UART in the AT89C51
and AT89C52. For further information on the UART operation, please click on the document link below:
https://www.wendangku.net/doc/3b16751394.html,/dyn/resources/prod_documents/DOC4316.PDF
6.Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’operation, please click on the document link below:
https://www.wendangku.net/doc/3b16751394.html,/dyn/resources/prod_documents/DOC4316.PDF
7.Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
7.1 Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2=1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.
7.2 Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit
located in the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture Mode RCAP2H and RCAP2L are preset by software. If EXEN2=1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In the operating mode, EXF2 does not flag an interrupt.
8.Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation. Modes 1 and 3 Baud Rates=Timer 2 Overflow Rate 16
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2=0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
[]
Modes 1 and 3Oscillator Frequency Baud Rate 3265536RCAP2H,RCAP2L =?- Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
This figure is valid only if RCLK or TCLK=1 in T2CON. Note that a rollover in
TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2=1) as a timer in the baud rate generator mode, TH2 and TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
9.Interrupts
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0,1 and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
10.Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
AT89S52单片机简介
2.引脚功能
2.1 VCC：电源
2.2 GND：接地
2.3 P0：P0口是一个8位开路漏极双向I/O口。作为一个输出端口，每个引脚能驱动8个TTL输入。当对P0端口写“1”时，引脚可被用于高阻抗输入。当访问外部程序和数据存储器时，P0口也可被设定低位地址/数据总线多路复用。在这种模式下，P0具有内部上拉电阻。在 Flash编程时，P0口也接收编码字节；在程序校验时，输出编码字节。程序校验时，外部上拉电阻是必备的。
2.4 P1口：P1口是一个具有内部上拉电阻的8位双向I/O口。P1输出缓冲器能驱动4个TTL输入。对P1引脚写“1”时，它们被内部上拉电阻拉高，并且可用作输入。用作输入时，被外部拉低的P1引脚由于内部上拉电阻的原因，将输出电流（I IL）。另外，P1.0和P1.1可被分别设定为定时器/计数器2的外部计数输入（P1.0/T2）和定时器/计数器2的触发脉冲输入（P1.1/T2EX），如下表所示。
驱动4个TTL输入。对P2引脚写“1”时，它们被内部上拉电阻拉高，并且可用作输入。用作输入时，被外部拉低的P2引脚由于内部上拉电阻的原因，将输出电流（I IL）。在访问外部程序存储器，以及用16位地址读取外部数据存储器（MOVX@DPTR）时，P2口发出高位字节。在这种应用中，发送1时P2口使用很强的内部上拉电阻。在使用8位地址（MOVX@RI）访问外部数据存储器时，P2口输出P2特殊函数寄存器的内容。在Flash编程和校验时，P2口也接收高位地址字节和一些控制信号。
2.6 P3口：P3口是一个具有内部上拉电阻的8位双向I/O口。P3输出缓冲器能驱动4个TTL输入。对P3引脚写“1”时，它们被内部上拉电阻拉高，并且可用作输入。用作输入时，被外部拉低的P3引脚由于内部上拉电阻的原因，将输出电流（I IL）。P3口为Flash编程和校验接收一些控制信号。P3口也提供一些
周期。看门狗终止后，引脚输出98个振荡周期的高电平。特殊函数寄存器AUXR （地址8EH）上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平功能被激活。
2.8 ALE/PROG：地址锁存器选通（ALE）是访问外部存储器时，锁存低位地址的输出脉冲。在Flash编程时，此引脚（PROG）也用作编程脉冲输入。在一般
情况下，ALE以六分之一的固定振荡器频率输出，且可用来作为外部定时器或时钟作用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲是跳跃的。如果需要，通过设置0位或SFR定位8EH，ALE操作将无效。经过该位设置，ALE仅在MOVX或MOVC指令时起作用。否则，ALE将被微弱拉高。如果微控制器在外部执行模式下，设置ALE无效位不生效。
2.9 PSEN：允许程序存储器（PSEN）是外部程序存储器的读选通。当AT89S52从外部程序存储器执行代码时，除了当每次访问外部数据存储器时两个PSEN激活是跳跃的之外，PSEN在每个机器周期被激活两次。
2.10 EA/VPP：可供外部检查。为了使设备接收外部程序存储器0000H至FFFFH 的编码，EA必须接GND。为了执行内部程序，EA应该接VCC。在Flash编程期间，EA引脚也接收12伏可供编程电压。
2.11 XTAL1：振荡器反相放大器和内部时钟发生电路的输入端。
2.12 XTAL2：振荡器反相放大器的输出端。
3.存储器结构
MCS-51设备有单独的程序和数据存储器地址空间。每个外部程序和数据存储器可被寻址直到64K字节。
3.1 程序存储器
如果EA引脚接地，所有程序都从外部存储器取出。对于89S52，如果EA接VCC，地址为0000H～1FFFH的程序从内部存储器取出，地址为2000H～FFFFH 的程序从外部存储器取出。
3.2 数据存储器
AT89S52有256字节片内数据存储器。高128字节占用与特殊功能寄存器相似的地址空间。意思是高128字节与SFR有相同的地址，而物理上不同于SFR。当一条指令访问一个高于7FH的内部地址时，寻址方式指定CPU访问高128字节RAM还是SFR空间。直接寻址方式访问特殊功能寄存器空间的说明。例如，
下面的直接寻址指令访问0A0H（P2口）的特殊功能寄存器。
MOV 0A0H , #data
使用间接寻址方式访问高128字节RAM的说明。例如，下面的间接寻址方式中，R0内容为0A0H，访问的是地址0A0H的数据字节，而不是P2口（它的地址也是0A0H）。
MOV @R0 ，#data
特别注意，堆栈操作也是间接寻址方式，因此高128字节数据RAM也可用于堆栈空间。
4.看门狗定时器（一次性激活重置）
WDT是一种需要软件控制的复位方式。WDT由14位计数器和看门狗定时器复位（WDTRST）SFR构成。WDT在重置情况下无法工作。为了使WDT工作，用户必须往WDTRST寄存器（SFR地址为0A6H）中依次写入01EH和0E1H。当使WDT工作后，在振荡器运行的同时它将增加每个机器周期。WDT停止时刻依赖于外部时钟频率。除了复位（硬件复位或WDT溢出复位），没有办法停止WDT工作。当WDT溢出时，它将在RST引脚驱动一个复位高脉冲输出。5.UART
在AT89S52中UART的操作与AT89C51和AT89C52一样。为了获得更深入的关于UART的信息，可点击如下文献链接：
https://www.wendangku.net/doc/3b16751394.html,/dyn/resources/prod_documents/DOC4316.PDF
6.定时器0和定时器1
在AT89S52中，定时器0和定时器1的操作与AT89C51和AT89C52一样。为了获得更深入的关于定时器的信息，可点击如下文献链接:
https://www.wendangku.net/doc/3b16751394.html,/dyn/resources/prod_documents/DOC4316.PDF
7.定时器2
定时器2是一个16位定时器/计数器，它既可以做定时器又可以做事件计数器。其工作方式由特殊寄存器T2CON中的C/T2位选择。定时器2有三种工作
模式：捕捉方式、自动重载（向上或向下计数）和波特率发生器。工作模式由T2CON中的位选择，如表6-1所示。定时器2由2个8位寄存器组成：TH2和TL2。在定时工作方式中，每个机器周期TL2寄存器都会增长。由于一个机器周期由12个振荡周期构成，所以计数频率就是振荡频率的1/12。
增长的反应。在这种方式下，每个机器周期的S5P2期间采样外部输入。当采样显示一个机器周期采样到高电平，而下一个周期采样到低电平，计数器将增长。在检测到跳变的这个周期的S3P1期间，新的计数值出现在寄存器中。因为识别1至0的跳变必须2个机器周期（24个振荡周期），所以最大的技术频率不高于振荡频率的1/24。为了确保给定的电平在改变前至少被采样一次，电平应该至少
在一个完整的机器周期内保持不变。
7.1捕捉方式
在捕捉模式下，通过T2CON 中的EXEN2来选择两种方式。如果EXEN2=0，定时器2是一个16位定时器或计数器，溢出时对T2CON 的TF2标志置位。该位随即引起中断。如果EXEN2=1，定时器2执行相同的操作，除上述作用外，在外部输入的1至0的跳变也会使得TH2和TL2中的值分别捕捉到RCAP2H 和RCAP2L 中。除此之外，T2EX 的跳变会引起T2CON 中的EXF2置位。EXF2位像TF2一样，会引起中断。
7.2自动重载（向上或向下计数）
当设置于16位自动重载模式下，定时器2可对其编程实现向上或向下计数。这一特点可以通过特殊寄存器T2MOD 中的DCEN （向下计数允许）来实现。通过复位，DCEN 被置为0，以便定时器2改为向上计数。DCEN 设置后，定时器2就可以依靠T2EX 引脚的值向上或向下计数。DCEN=0时，定时器2自动向上计数。该模式下，T2CON 中的EXEN2位可以选择两种方式。如果EXEN2=0，定时器2向上计数到0FFFFH 后置位TF2溢出。该溢出也使得定时器寄存器重新从RCAP2H 和RCAP2L 中加载16位值。定时器工作于捕捉模式时，RCAP2H 和RCAP2L 的值可以由软件预设。如果EXEN2=1，16位重载将被溢出和一个在外部输入T2EX 的1至0跳变其中之一触发。这个跳变也置位EXF2。如果允许，置位TF2和EXF2都会引起中断。如表10-2所示，置位DCEN 允许定时器2向上或向下计数。在这种模式下，T2EX 引脚控制着计数的方向。T2EX 上的一个逻辑1使得定时器2向上计数。定时器将计到0FFFFH 溢出并置位TF2。该溢出也使得RCAP2H 和RCAP2L 中的16位值分别重载到定时器存储器TH2和TL2中。T2EX 上的一个逻辑0使得定时器2向下计数。当TH2和TL2等于RCAP2H 和RCAP2L 中存储的值的时候，计数器下溢。该下溢置位TF2，并引起0FFFFH 被重载到定时器存储器中。当定时器2上溢或下溢时，EXF2被锁死，并用于解决第17位。在这种工作模式下，EXF2不能触发中断。
8.波特率发生器
通过设置T2CON 中的TCLK 和（或）RCLK 可选择定时器2作为波特率发生器。特别注意，如果定时器2作为接收器或传送器且定时器1可用于其它功能，发送和接收的波特率可以不同。设置RCLK 和（或）TCLK 可以使定时器2工作于波特率发生器模式。波特率发生器模式与自动重载模式相似，因此TH2的翻转使得定时器2寄存器重载被软件预置16位值的RCAP2H 和RCAP2L 中的值。模式1和模式3的波特率由定时器2按照如下溢出速率公式决定： Modes 1 and 3 Baud Rates=Timer 2 Overflow Rate 16
定时器可设置成定时器或计数器功能。在多数应用情况下，一般配置成定时方式（CP/T2=0）。定时方式与用于波特率发生器的定时器2有所不同。通常，作为定时器，它在每一机器周期（1/12振荡周期）都会增加。然而，作为波特率发生器，它在每一状态时间（1/2振荡周期）都会增加。波特率计算公式如下：
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Modes 1 and 3Oscillator Frequency Baud Rate 3265536RCAP2H,RCAP2L =?- 其中，（RCAP2H,RCAP2L ）是RCAP2H 和RCAP2L 组成的16位无符号整数。
该计算仅在T2CON中的RCLK或TCLK=1时成立。特别注意，TH2的翻转并不置位TF2也不产生中断。还需特别注意，如果EXEN2置位后，T2EX引脚上1至0跳变将置位EXF2，但不会使（RCAP2H,RCAP2L）重载到（TH2，TL2）中。因此，当定时器2作为波特率发生器时，T2EX也还可以作为一个额外的外部中断。特别注意，当定时器2处于波特率发生器模式作为定时器时（TR2=1），TH2和TL2不应该被读或写。在这种模式下，定时器在每一状态都会增加，读或写的结果就不会准确。寄存器RCAP2可以读但不能写，因为写可能和重载重叠，并造成写和（或）重载错误。在访问定时器2或RCAP2寄存器前，定时器应该被关闭（TR2清0）。
9.中断
AT89S52总共有6个中断源：两个外部中断（INT0和INT1），三个定时中
断（定时器0、1、2）和一个串行端口中断。每个中断源都可以通过置位或清除特殊寄存器IE中的位分别使其有效或无效。IE还包括一个总无效位EA，它能一次使所有中断无效。特别注意，IE.6位是未生效的。用户软件不应给这些位写1，因为它们为AT89系列新产品预留。定时器2的中断可以被寄存器T2CON中的TF2和EXF2的或逻辑触发。当服务程序启动后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2或EXF2激活中断，标志位也必须由软件清0。定时器0和定时器1的标志位TF0和TF1，在计数溢出的那个周期的S5P2被置位。它们的值随即在下一个周期被电路捕捉。然而，定时器2的标志位TF2在S2P2被置位，在同一个定时器溢出周期被电路捕捉下来。
10.振荡器特性
XTAL1和XTAL2分别是一种作为单片的振荡器的反相放大器的输入、输出端。石英晶体或陶瓷共振器都可以被用于其中。为了驱动外部时钟源的装置，XTAL2应该不接，而从XTAL1接入。因为内部时钟电路的输入是通过二分频形成的，所以不需要外部时钟信号占空比的调整需要量，但是最小和最大电压高电平和低电平持续时间说明必须留心。