IS93C46B-3P中文资料

IS93C46B

ISSI

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Copyright ? 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

1,024-BIT SERIAL ELECTRICALLY ERASABLE PROM

JULY 2003

FUNCTIONAL BLOCK DIAGRAM

FEATURES

?Industry-standard Microwire Interface —Non-volatile data storage —Low voltage operation: Vcc = 2.5V to 5.5V

—Full TTL compatible inputs and outputs —Auto increment for efficient data dump ?x16 bit organization

?Hardware and software write protection

—Defaults to write-disabled state at power-up —Software instructions for write-enable/disable ?Enhanced low voltage CMOS E 2PROM technology

?Versatile, easy-to-use Interface —Self-timed programming cycle —Automatic erase-before-write —Programming status indicator —Word and chip erasable

—Chip select enables power savings ?Durable and reliable

—40-year data retention after 1M write cycles —1 million write cycles —Unlimited read cycles — Schmitt-trigger inputs

?Industrial and Automotive Temperature Grade

DESCRIPTION

The IS93C46B is a low-cost 1kb non-volatile,ISSI ? serial EEPROM. It is fabricated using an enhanced CMOS design and process. The IS93C46B contains power-efficient read/write memory, and organization of 64 words of 16 bits.The IS93C46B is fully backward compatible with IS93C46.

An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. A selected x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the two instructions WRITE ALL or ERASE ALL can program the entire array. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/BUSY status by raising chip select (CS). The self-timed write cycle includes an automatic erase-before-write

capability. The device can output any number of consecutive words using a single READ instruction.

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Rev.A IS93C46B

ISSI

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PIN CONFIGURATIONS

8-Pin JEDEC SOIC “G”

8-Pin JEDEC SOIC “GR”

PIN DESCRIPTIONS

CS Chip Select SK Serial Data Clock D IN Serial Data Input D OUT Serial Data Output NC Not Connected Vcc Power GND

Ground

instruction begins with a start bit of the logical “1” or HIGH. Following this are the opcode (2 bits),

address field (6 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clock-speed flexibility. Upon completion of bus

communication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway.

Read (READ)

The READ instruction is the only instruction that outputs serial data on the D OUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical “0” bit precedes the actual 16-bit output data string.) The output on D OUT changes during the low-to-high transitions of SK (see Figure 3).

Low Voltage Read

The IS93C46B has been designed to ensure that data read operations are reliable in low voltage environments.They provide accurate operation with Vcc as low as 2.5V.

Auto Increment Read Operations

In the interest of memory transfer operation applications,the IS93C46B has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location ad-dress. Once the 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continu-ously with CS HIGH until the chip select (CS) control pin is brought LOW . This allows for single instruction data dumps to be executed with a minimum of firmware overhead.

Applications

The IS93C46B is very popular in many high-volume applications which require low-power, low-density storage. Applications using this device include industrial controls, networking, and numerous other consumer electronics.

Endurance and Data Retention

The IS93C46B is designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). It provides 40 years of secure data retention without power after the execution of 1M programming cycles.

Device Operations

The IS93C46B is controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each

1234

8765

CS SK D IN D OUT

VCC NC NC GND

1234

8765

NC VCC CS SK

NC GND D OUT D IN

1234

8765

CS SK D IN D OUT

VCC NC NC GND

(Rotated)

8-Pin DIP, 8-Pin TSSOP

IS93C46B

ISSI

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Write All (WRALL)

The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 250 ns (t CS ), the D OUT pin indicates the READY/BUSY status of the chip (see Figure 6).

Write Disable (WDS)

The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against acci-dental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation.

Erase Register (ERASE)

After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of t CS , will cause D OUT to indicate the READ/BUSY status of the chip: a logical “0” indicates programming is still in progress;a logical “1” indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8).

Erase All (ERAL)

Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical “1” (see Figure 9).

Write Enable (WEN)

The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL,ERASE, and ERAL) can be done. When Vcc is applied,this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.)

Write (WRITE)

The WRITE instruction includes 16 bits of data to be written into the specified register. After the last data bit has been applied to D IN , and before the next rising edge of SK, CS must be brought LOW. If the device is write-enabled, then the falling edge of CS initiates the self-timed programming cycle (see WEN).

If CS is brought HIGH, after a minimum wait of 250 ns (5V operation) after the falling edge of CS (t CS ) D OUT will indicate the READY/BUSY status of the chip. Logical “0”means programming is still in progress; logical “1” means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle,t WP ; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag.

INSTRUCTION SET - IS93C46B

16-bit Organization

Instruction Start Bit

OP Code Address (1)Input Data

READ

110(A 5-A 0)—WEN (Write Enable)10011xxxx —WRITE

101(A 5-A 0)(D 15-D 0) (2)WRALL (Write All Registers)10001xxxx (D 15-D 0) (2)

WDS (Write Disable)10000xxxx —ERASE

111(A 5-A 0)—ERAL (Erase All Registers)

1

00

10xxxx

—

Notes:

1. x = Don't care bit.

2.If input data is not 16 bits exactly, the last 16 bits will be taken as input data.

IS93C46B ISSI?

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit

V GND Voltage with Respect to GND–0.3 to +6.5V

T BIAS Temperature Under Bias (Industrial)–40 to +85°C

T BIAS Temperature Under Bias (Automotive)–40 to +125°C

T STG Storage Temperature–65 to +150°C

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

OPERATING RANGE

Range Ambient Temperature V C C

Commercial0°C to +70°C 2.5V to 5.5V

Industrial–40°C to +85°C 2.5V to 5.5V

Automotive–40°C to +125°C 2.7V to 5.5V or 4.5V to 5.5V

CAPACITANCE

Symbol Parameter Conditions Max.Unit

C IN Input Capacitance V IN = 0V5pF

C OUT Output Capacitance V OUT = 0V5pF

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Rev.A

IS93C46B ISSI?

DC ELECTRICAL CHARACTERISTICS

T A = 0°C to +70°C for Commercial, –40°C to +85°C for Industrial, and –40°C to +125°C for Automotive.

Symbol Parameter Test Conditions Vcc Min.Max.Unit V OL Output LOW Voltage I OL = 100 μA 2.5V to 5.5V—0.2V V OL1Output LOW Voltage I OL = 2.1 mA 4.5V to 5.5V—0.4V V OH Output HIGH Voltage I OH = –100 μA 2.5V to 5.5V V CC – 0.2—V V OH1Output HIGH Voltage I OH = –400 μA 4.5V to 5.5V 2.4—V V IH Input HIGH Voltage 2.5V to 5.5V0.7X V CC V CC+1V

4.5V to

5.5V0.7X V CC V CC+1

V IL Input LOW Voltage 2.5V to 5.5V–0.30.2X V CC V

4.5V to

5.5V–0.30.8

I LI Input Leakage V IN = 0V to V CC (CS, SK,D IN,ORG)0 2.5μA I LO Output Leakage V OUT = 0V to V CC, CS = 0V0 2.5μA N o t e s:

Automotive grade devices in this table are tested with Vcc = 2.7V to 5.5V and 4.5V to 5.5V.

IS93C46B ISSI?

POWER SUPPLY CHARACTERISTICS

T A = 0°C to +70°C for Commercial

Symbol Parameter Test Conditions Vcc Min.Max.Unit

I CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100μA

CMOS input levels 5.0V—500μA

I CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mA

CMOS input levels 5.0V—3mA

I SB Standby C urrent CS = V IH, SK = 0V 2.7V—10μA

5.0V—30μA

POWER SUPPLY CHARACTERISTICS

T A = –40°C to +85°C for Industrial

Symbol Parameter Test Conditions Vcc Min.Max.Unit

I CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100μA

CMOS input levels 5.0V—500μA

I CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mA

CMOS input levels 5.0V—3mA

I SB Standby C urrent CS = V IH, SK = 0V 2.7V—2μA

5.0V—4μA

POWER SUPPLY CHARACTERISTICS

T A = –40°C to +125°C for Automotive

Symbol Parameter Test Conditions Vcc Min.Max.Unit

I CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100μA

CMOS input levels 5.0V—500μA

I CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mA

CMOS input levels 5.0V—3mA

I SB Standby C urrent CS = V IH, SK = 0V 2.7V—3μA

5.0V—8μA

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Rev.A

IS93C46B ISSI?

AC ELECTRICAL CHARACTERISTICS

T A = T A = 0°C to +70°C for Commercial, –40°C to +85°C for Industrial

Symbol Parameter Test Conditions Vcc Min.Max.Unit

f SK SK Clock Frequency 2.5V to 5.5V01Mhz

2.7V to 5.5V01Mhz

4.5V to

5.5V02Mhz

t SKH SK HIGH Time 2.5V to 5.5V500—ns

2.7V to 5.5V350—ns

4.5V to

5.5V250—ns

t SKL SK LOW Time 2.5V to 5.5V500—ns

2.7V to 5.5V350—ns

4.5V to

5.5V250—ns

t CS Minimum CS LOW Time 2.5V to 5.5V500—ns

2.7V to 5.5V250—ns

4.5V to

5.5V250—ns

t CSS CS Setup Time Relative to SK 2.5V to 5.5V100—ns

2.7V to 5.5V50—ns

4.5V to

5.5V50—ns

t DIS Din Setup Time Relative to SK 2.5V to 5.5V100—ns

2.7V to 5.5V100—ns

4.5V to

5.5V100—ns

t CSH CS Hold Time Relative to SK 2.5V to 5.5V0—ns

2.7V to 5.5V0—ns

4.5V to

5.5V0—ns

t DIH Din Hold Time Relative to SK 2.5V to 5.5V100—ns

2.7V to 5.5V100—ns

4.5V to

5.5V100—ns

t PD1Output Delay to “1”AC Test 2.5V to 5.5V—400ns

2.7V to 5.5V—350ns

4.5V to

5.5V—250ns

t PD0Output Delay to “0”AC Test 2.5V to 5.5V—400ns

2.7V to 5.5V—350ns

4.5V to

5.5V—250ns

t SV CS to Status Valid AC Test 2.5V to 5.5V—400ns

2.7V to 5.5V—250ns

4.5V to

5.5V—250ns

t DF CS to Dout in 3-state AC Test, CS=VIL 2.5V to 5.5V—200ns

2.7V to 5.5V—200ns

4.5V to

5.5V—100ns

t WP Write Cycle Time 2.5V to 5.5V—10ms

2.7V to 5.5V—10ms

4.5V to

5.5V—5ms

N o t e s:

1. C L = 100pF

IS93C46B ISSI?

AC ELECTRICAL CHARACTERISTICS

T A = –40°C to +125°C for Automotive

Symbol Parameter Test Conditions Vcc Min.Max.Unit

f SK SK Clock Frequency 2.7V to 5.5V01Mhz

4.5V to

5.5V02Mhz

t SKH SK HIGH Time 2.7V to 5.5V500—ns

4.5V to

5.5V250—ns

t SKL SK LOW Time 2.7V to 5.5V500—ns

4.5V to

5.5V250—ns

t CS Minimum CS LOW Time 2.7V to 5.5V250—ns

4.5V to

5.5V250—ns

t CSS CS Setup Time Relative to SK 2.7V to 5.5V100—ns

4.5V to

5.5V50—ns

t DIS Din Setup Time Relative to SK 2.7V to 5.5V100—ns

4.5V to

5.5V100—ns

t CSH CS Hold Time Relative to SK 2.7V to 5.5V0—ns

4.5V to

5.5V0—ns

t DIH Din Hold Time Relative to SK 2.7V to 5.5V100—ns

4.5V to

5.5V100—ns

t PD1Output Delay to “1”AC Test 2.7V to 5.5V—400ns

4.5V to

5.5V—250ns

t PD0Output Delay to “0”AC Test 2.7V to 5.5V—400ns

4.5V to

5.5V—250ns

t SV CS to Status Valid AC Test 2.7V to 5.5V—250ns

4.5V to

5.5V—250ns

t DF CS to Dout in 3-state AC Test, CS=VIL 2.7V to 5.5V—200ns

4.5V to

5.5V—100ns

t WP Write Cycle Time 2.7V to 5.5V—10ms

4.5V to

5.5V—5ms

N o t e s:

1. C L = 100pF

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Rev.A

IS93C46B ISSI?AC WAVEFORMS

FIGURE 2. SYNCHRONOUS DATA TIMING

Notes:

To determine address bits An-A0 and data bits Dm-Do, see Instruction Set.

IS93C46B ISSI?AC WAVEFORMS

FIGURE 4. WRITE ENABLE (WEN) TIMING

Notes:

1. After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status

(D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.

2. To determine address bits A n-A0 and data bits D m-D0, see Instruction Set.

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Rev.A

IS93C46B ISSI?AC WAVEFORMS

FIGURE 6. WRITE ALL (WRALL) TIMING

IS93C46B ISSI?AC WAVEFORMS

FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING

Note for Figures 8 and 9:

After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status (D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.

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Rev.A

IS93C46B ISSI?

ORDERING INFORMATION

Commercial: 0oC to +70oC

Speed Voltage Range Order Part No.Package

1Mhz * 2.5V to 5.5V IS93C46B-3P300-mil Plastic DIP

IS93C46B-3G SOIC (rotated) JEDEC

IS93C46B-3GR SOIC JEDEC

IS93C46B-3Z169-mil TSSOP

ORDERING INFORMATION

Industrial Range: -40oC to +85oC

Speed Voltage Range Order Part No.Package

1Mhz * 2.5V to 5.5V IS93C46B-3PI300-mil Plastic DIP

IS93C46B-3GI SOIC (rotated) JEDEC

IS93C46B-3GRI SOIC JEDEC

IS93C46B-3ZI169-mil TSSOP

ORDERING INFORMATION

Automotive Range: -40oC to +125oC

Speed Voltage Range Order Part No.Package

1Mhz * 2.7V to 5.5V IS93C46B-3PA300-mil Plastic DIP

IS93C46B-3GRA SOIC JEDEC

* The specification allows for higher speed. Please see the AC Charateristics for more information.