当前位置：文档库 › P4C1049-55L36C中文资料

P4C1049-55L36C中文资料

Document # SRAM128 REV OR

P4C1049/P4C1049L HIGH SPEED 512K x 8STATIC CMOS RAM

High Speed (Equal Access and Cycle Times)— 15/20/25 ns (Commercial)— 20/25/35 ns (Industrial)

— 20/25/35/45/55/70 ns (Military)Low Power

Single 5V±10% Power Supply

Easy Memory Expansion Using CE and OE Inputs

Common Data I/O Three-State Outputs

PIN CONFIGURATIONS

1519B

Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages

—36-Pin SOJ (400 mil)—36-Pin FLATPACK

—36-Pin LCC (452 mil x 920 mil)

FEATURES

DESCRIPTION

The P4C1049 is a 4 Megabit high-speed CMOS static RAM organized as 512Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply.

Access times as fast as 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1049is a member of a family of PACE RAM? products offer-

ing fast access times.

SOLDER-SEAL FLATPACK (FS-4)

SOJ (J9)

The P4C1049 device provides asynchronous operation with matching access and cycle times. Memory loca-tions are specified on address pins A 0 to A 18. Reading is accomplished by device selection (CE) and output en-abling (OE ) while write enable (WE ) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the

data input/output pins. The input/output pins stay in the

HIGH Z state when either CE

or OE is HIGH or WE is LOW.

LCC (L11)

P4C1049

P4C1049MAXIMUM RATINGS (1)

Symbol Parameter Value Unit V CC

Power Supply Pin with –0.5 to +7 V

Respect to GND Terminal Voltage with –0.5 to V TERM Respect to GND V CC +0.5V (up to 7.0V)

T A

Operating Temperature

–55 to +125

°C

Symbol Parameter Value Unit T BIAS Temperature Under –55 to +125°C Bias

T STG Storage Temperature –65 to +150

°C P T Power Dissipation 1.0W I OUT

DC Output Current

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

I SB

Standby Power Supply Current (TTL Input Levels)CE ≥ V IH Mil.

V CC = Max, Ind./Com’l.f = Max., Outputs Open

______

4540

1510

______

CE ≥ V HC Mil.

V CC = Max, Ind./Com’l.f = 0, Outputs Open V IN ≤ V LC or V IN ≥ V HC

Standby Power Supply Current

(CMOS Input Levels)

I SB1

Industrial

Grade(2)Ambient Temperature

GND V CC

0V 0V

5.0V ± 10%5.0V ± 10%

0V 5.0V ± 10%–55°C to +125°C Military

Symbol C IN C OUT

Parameter Input Capacitance

Output Capacitance Conditions V IN = 0V

V OUT = 0V

Unit pF pF

CAPACITANCES (4)

V CC = 5.0V, T A = 25°C, f = 1.0MHz Symbol DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage (2)V IH V IL V HC V LC I LI

I LO

Parameter

Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Leakage Current

Test Conditions

V CC = Max. Mil.V IN = GND to V CC Ind./Com’l.V CC = Max., Mil.

CE = V IH , Ind./Com’l.V OUT = GND to V CC

Min 2.2

–0.3(3)

V CC –0.2–0.3(3)

–10–5–10–5

Max

V CC +0.30.8V CC +0.30.2+10+5+10+5

https://www.wendangku.net/doc/4c2778065.html,mercial –40°C to +85°C 0°C to +70°C

Unit

V V V V μA

μA mA

V OL Output Low Voltage

(TTL Load)

I OL = +8 mA, V CC = Min.0.4

V Output High Voltage (TTL Load)

V OH

I OH = –4 mA, V CC = Min. 2.4V

Output Leakage Current

P4C1049L ______

40n/a

10n/a

______

Min 2.2

–0.3(3)V CC –0.2–0.3(3)

–5n/a –5n/a Max

V CC +0.30.8V CC +0.30.2+5n/a +5n/a

0.4

2.4N/A = Not Applicable

*V CC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = V IL , OE = V IH .

I CC

Symbol

Parameter

Temperature Range Dynamic Operating Current*

Commercial

Industrial Military

–15N/A

–20–25–35–45–55–70Unit N/A mA mA mA

POWER DISSIPATION CHARACTERISTICS VS. SPEED

N/A N/A N/A N/A 220N/A 185190180N/A 185175N/A DATA RETENTION CHARACTERISTICS (P4C1049L Military Temperature Only)

Symbol V DR I CCDR t CDR t R ?

Parameter

V CC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time

Test Conditons CE

≥ V CC –0.2V,V IN ≥ V CC –0.2V or V IN ≤ 0.2V

Min 3.0

0t RC §

Typ.*V CC = 3.0V Max V CC = 3.0V

Unit 23V

mA ns ns

*T A = +25°C

§t RC = Read Cycle Time

This parameter is guaranteed but not tested.

DATA RETENTION WAVEFORM

165

170

200

195

185

175

P4C1049

AC ELECTRICAL CHARACTERISTICS—READ CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)(2)

Sym.t RC t AA t AC t OH t LZ t HZ t OE t OLZ t OHZ t PU t PD

Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change

Chip Enable to Output in

Low Z

Chip Disable to Output in High Z

Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time

Chip Disable to Power Down Time

Output Enable Low to Data Valid

Min Max

Min Max Min Max Min Max Min Max Min Max Min Max -20

-25

-35

-45

-55

-70

-15Unit 15

151587715

33002020

2533002525

1110

3533003535

1515

4533004545

2020

5533005555

2525

7033007070

3030

3070ns

ns ns ns ns

ns ns ns

ns ns

TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)

TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)

Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification

is not implied. Exposure to MAXIMUM rating conditions for extended

periods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feet per

minute of air flow.

3.Transient inputs with V

IL and I

not more negative than –2.0V and

–100mA, respectively, are permissible for pulse widths up to 20 ns.4.This parameter is sampled and not 100% tested.

5.WE is HIGH for READ cycle.

6.CE is LOW and OE is LOW for READ cycle.

7.ADDRESS must be valid prior to, or coincident with CE transition LOW.

8.Transition is measured ± 200 mV from steady state voltage prior to

change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested.

9.Read Cycle Time is measured from the last valid address to the first

transitioning address.

P4C1049

-35

AC CHARACTERISTICS—WRITE CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)(2)

Sym.t WC t CW t AS t WP t AH t DW t DH Parameter Write Cycle Time

Chip Enable Time to End of Write

Address Set-up Time Write Pulse Width Address Hold Time Date Hold Time

Data Valid to End of Write Min Max

Min Max Min Max Min Max Min Max Min Max Min Max -20

-25

-45

-55

-70

-15Unit 15120

140

0160

0220

0250

0300

0350

12091401118160132220015302502035350254040030ns ns ns ns ns ns ns ns

t AW Address Valid to End of Write

121400Write Enable to Output in High Z

t WZ 810

1115182530ns Output Active from End of Write

t OW

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)

Notes:

10.CE and WE must be LOW for WRITE cycle.

11.OE is LOW for this WRITE cycle to show t WZ and t OW .

12.If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state

13.Write Cycle Time is measured from the last valid address to the first

transitioning address.

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)

(10)

P4C1049

Input Pulse Levels GND to 3.0V

Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V

Output Load

See Figures 1 and 2

AC TEST CONDITIONS

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P4C1049, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 μF high frequency capacitor is also required between V CC and ground. To avoid

signal reflections, proper termination must be used; for example, a 50?test environment should be terminated into a 50? load with 1.73V (Thevenin Voltage) at the comparator input, and a 116? resistor must be used in series with D OUT to match 166? (Thevenin Resistance).

Write

Active Read TRUTH TABLE

Mode Standby Standby D OUT Disabled Standby Power I/O W E O E CE High Z High Z D OUT High Z

X X H H L

X X H L X

H L L L

Standby Active Active

High Z X

ORDERING INFORMATION

P4C1049

SOLDER SEAL FLATPACK

SOJ SMALL OUTLINE IC PACKAGE

RECTANGULAR LEADLESS CHIP CARRIER

P4C1049

REVISIONS

DOCUMENT NUMBER:SRAM128

DOCUMENT TITLE:P4C1049 / P4C1049L HIGH SPEED 512K x 8 STATIC CMOS RAM

REV.ISSUE

DATE

ORIG. OF

CHANGE

DESCRIPTION OF CHANGE

OR Oct-05JDB New Data Sheet