LM3S1636-IQC50-A2T,LM3S1636-IQC50-A2, 规格书,Datasheet 资料
TEXAS INSTRUMENTS-PRODUCTION DATA
Stellaris?LM3S1636Microcontroller
DATA SHEET
Copyright?2007-2012 DS-LM3S1636-12986.2532
Copyright
Copyright?2007-2012Texas Instruments Incorporated All rights reserved.Stellaris and StellarisWare?are registered trademarks of Texas Instruments Incorporated.ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited.Other names and brands may be claimed as the property of others.
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
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https://www.wendangku.net/doc/4112329141.html,/stellaris
https://www.wendangku.net/doc/4112329141.html,/sc/technical-support/product-information-centers.htm
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller
Table of Contents
Revision History (23)
About This Document (29)
Audience (29)
About This Manual (29)
Related Documents (29)
Documentation Conventions (30)
1Architectural Overview (32)
1.1Product Features (32)
1.2Target Applications (40)
1.3High-Level Block Diagram (40)
1.4Functional Overview (42)
1.4.1ARM Cortex?-M3 (42)
1.4.2Motor Control Peripherals (43)
1.4.3Analog Peripherals (43)
1.4.4Serial Communications Peripherals (44)
1.4.5System Peripherals (45)
1.4.6Memory Peripherals (46)
1.4.7Additional Features (47)
1.4.8Hardware Details (47)
2The Cortex-M3Processor (48)
2.1Block Diagram (49)
2.2Overview (50)
2.2.1System-Level Interface (50)
2.2.2Integrated Configurable Debug (50)
2.2.3Trace Port Interface Unit(TPIU) (51)
2.2.4Cortex-M3System Component Details (51)
2.3Programming Model (52)
2.3.1Processor Mode and Privilege Levels for Software Execution (52)
2.3.2Stacks (52)
2.3.3Register Map (53)
2.3.4Register Descriptions (54)
2.3.5Exceptions and Interrupts (67)
2.3.6Data Types (67)
2.4Memory Model (67)
2.4.1Memory Regions,Types and Attributes (69)
2.4.2Memory System Ordering of Memory Accesses (69)
2.4.3Behavior of Memory Accesses (69)
2.4.4Software Ordering of Memory Accesses (70)
2.4.5Bit-Banding (71)
2.4.6Data Storage (73)
2.4.7Synchronization Primitives (74)
2.5Exception Model (75)
2.5.1Exception States (76)
2.5.2Exception Types (76)
2.5.3Exception Handlers (79)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
2.5.4Vector Table (79)
2.5.5Exception Priorities (80)
2.5.6Interrupt Priority Grouping (81)
2.5.7Exception Entry and Return (81)
2.6Fault Handling (83)
2.6.1Fault Types (84)
2.6.2Fault Escalation and Hard Faults (84)
2.6.3Fault Status Registers and Fault Address Registers (85)
2.6.4Lockup (85)
2.7Power Management (85)
2.7.1Entering Sleep Modes (86)
2.7.2Wake Up from Sleep Mode (86)
2.8Instruction Set Summary (87)
3Cortex-M3Peripherals (90)
3.1Functional Description (90)
3.1.1System Timer(SysTick) (90)
3.1.2Nested Vectored Interrupt Controller(NVIC) (91)
3.1.3System Control Block(SCB) (93)
3.1.4Memory Protection Unit(MPU) (93)
3.2Register Map (98)
3.3System Timer(SysTick)Register Descriptions (100)
3.4NVIC Register Descriptions (104)
3.5System Control Block(SCB)Register Descriptions (117)
3.6Memory Protection Unit(MPU)Register Descriptions (144)
4JTAG Interface (154)
4.1Block Diagram (155)
4.2Signal Description (155)
4.3Functional Description (156)
4.3.1JTAG Interface Pins (156)
4.3.2JTAG TAP Controller (157)
4.3.3Shift Registers (158)
4.3.4Operational Considerations (158)
4.4Initialization and Configuration (161)
4.5Register Descriptions (161)
4.5.1Instruction Register(IR) (161)
4.5.2Data Registers (164)
5System Control (166)
5.1Signal Description (166)
5.2Functional Description (166)
5.2.1Device Identification (166)
5.2.2Reset Control (166)
5.2.3Power Control (170)
5.2.4Clock Control (171)
5.2.5System Control (177)
5.3Initialization and Configuration (178)
5.4Register Map (178)
5.5Register Descriptions (180)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller 6Hibernation Module (233)
6.1Block Diagram (234)
6.2Signal Description (234)
6.3Functional Description (235)
6.3.1Register Access Timing (235)
6.3.2Clock Source (235)
6.3.3Battery Management (236)
6.3.4Real-Time Clock (237)
6.3.5Battery-Backed Memory (237)
6.3.6Power Control (237)
6.3.7Initiating Hibernate (238)
6.3.8Interrupts and Status (238)
6.4Initialization and Configuration (238)
6.4.1Initialization (239)
6.4.2RTC Match Functionality(No Hibernation) (239)
6.4.3RTC Match/Wake-Up from Hibernation (239)
6.4.4External Wake-Up from Hibernation (240)
6.4.5RTC/External Wake-Up from Hibernation (240)
6.5Register Map (240)
6.6Register Descriptions (241)
7Internal Memory (254)
7.1Block Diagram (254)
7.2Functional Description (254)
7.2.1SRAM Memory (254)
7.2.2Flash Memory (255)
7.3Flash Memory Initialization and Configuration (256)
7.3.1Flash Programming (256)
7.3.2Nonvolatile Register Programming (257)
7.4Register Map (258)
7.5Flash Register Descriptions(Flash Control Offset) (259)
7.6Flash Register Descriptions(System Control Offset) (267)
8General-Purpose Input/Outputs(GPIOs) (280)
8.1Signal Description (280)
8.2Functional Description (284)
8.2.1Data Control (285)
8.2.2Interrupt Control (286)
8.2.3Mode Control (287)
8.2.4Commit Control (287)
8.2.5Pad Control (287)
8.2.6Identification (288)
8.3Initialization and Configuration (288)
8.4Register Map (289)
8.5Register Descriptions (291)
9General-Purpose Timers (326)
9.1Block Diagram (327)
9.2Signal Description (328)
9.3Functional Description (328)
9.3.1GPTM Reset Conditions (328)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
9.3.232-Bit Timer Operating Modes (328)
9.3.316-Bit Timer Operating Modes (330)
9.4Initialization and Configuration (333)
9.4.132-Bit One-Shot/Periodic Timer Mode (334)
9.4.232-Bit Real-Time Clock(RTC)Mode (334)
9.4.316-Bit One-Shot/Periodic Timer Mode (334)
9.4.416-Bit Input Edge Count Mode (335)
9.4.516-Bit Input Edge Timing Mode (335)
9.4.616-Bit PWM Mode (336)
9.5Register Map (336)
9.6Register Descriptions (337)
10Watchdog Timer (362)
10.1Block Diagram (363)
10.2Functional Description (363)
10.3Initialization and Configuration (364)
10.4Register Map (364)
10.5Register Descriptions (365)
11Analog-to-Digital Converter(ADC) (386)
11.1Block Diagram (386)
11.2Signal Description (387)
11.3Functional Description (387)
11.3.1Sample Sequencers (388)
11.3.2Module Control (388)
11.3.3Hardware Sample Averaging Circuit (389)
11.3.4Analog-to-Digital Converter (389)
11.3.5Differential Sampling (390)
11.3.6Test Modes (392)
11.3.7Internal Temperature Sensor (392)
11.4Initialization and Configuration (393)
11.4.1Module Initialization (393)
11.4.2Sample Sequencer Configuration (393)
11.5Register Map (394)
11.6Register Descriptions (395)
12Universal Asynchronous Receivers/Transmitters(UARTs) (423)
12.1Block Diagram (424)
12.2Signal Description (424)
12.3Functional Description (425)
12.3.1Transmit/Receive Logic (425)
12.3.2Baud-Rate Generation (425)
12.3.3Data Transmission (426)
12.3.4Serial IR(SIR) (427)
12.3.5FIFO Operation (428)
12.3.6Interrupts (428)
12.3.7Loopback Operation (429)
12.3.8IrDA SIR block (429)
12.4Initialization and Configuration (429)
12.5Register Map (430)
12.6Register Descriptions (431)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller 13Synchronous Serial Interface(SSI) (465)
13.1Block Diagram (465)
13.2Signal Description (466)
13.3Functional Description (466)
13.3.1Bit Rate Generation (466)
13.3.2FIFO Operation (467)
13.3.3Interrupts (467)
13.3.4Frame Formats (467)
13.4Initialization and Configuration (475)
13.5Register Map (476)
13.6Register Descriptions (477)
14Inter-Integrated Circuit(I2C)Interface (503)
14.1Block Diagram (504)
14.2Signal Description (504)
14.3Functional Description (504)
14.3.1I2C Bus Functional Overview (505)
14.3.2Available Speed Modes (507)
14.3.3Interrupts (508)
14.3.4Loopback Operation (508)
14.3.5Command Sequence Flow Charts (508)
14.4Initialization and Configuration (516)
14.5Register Map (517)
14.6Register Descriptions(I2C Master) (518)
14.7Register Descriptions(I2C Slave) (531)
15Analog Comparators (540)
15.1Block Diagram (541)
15.2Signal Description (541)
15.3Functional Description (542)
15.3.1Internal Reference Programming (542)
15.4Initialization and Configuration (543)
15.5Register Map (544)
15.6Register Descriptions (544)
16Pulse Width Modulator(PWM) (552)
16.1Block Diagram (553)
16.2Signal Description (554)
16.3Functional Description (554)
16.3.1PWM Timer (554)
16.3.2PWM Comparators (555)
16.3.3PWM Signal Generator (556)
16.3.4Dead-Band Generator (557)
16.3.5Interrupt/ADC-Trigger Selector (557)
16.3.6Synchronization Methods (557)
16.3.7Fault Conditions (558)
16.3.8Output Control Block (558)
16.4Initialization and Configuration (558)
16.5Register Map (559)
16.6Register Descriptions (561)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
17Pin Diagram (591)
18Signal Tables (592)
18.1Signals by Pin Number (592)
18.2Signals by Signal Name (596)
18.3Signals by Function,Except for GPIO (600)
18.4GPIO Pins and Alternate Functions (604)
18.5Connections for Unused Signals (606)
19Operating Characteristics (607)
20Electrical Characteristics (608)
20.1DC Characteristics (608)
20.1.1Maximum Ratings (608)
20.1.2Recommended DC Operating Conditions (608)
20.1.3On-Chip Low Drop-Out(LDO)Regulator Characteristics (609)
20.1.4GPIO Module Characteristics (609)
20.1.5Power Specifications (609)
20.1.6Flash Memory Characteristics (611)
20.1.7Hibernation (611)
20.2AC Characteristics (611)
20.2.1Load Conditions (611)
20.2.2Clocks (612)
20.2.3JTAG and Boundary Scan (613)
20.2.4Reset (615)
20.2.5Sleep Modes (616)
20.2.6Hibernation Module (616)
20.2.7General-Purpose I/O(GPIO) (617)
20.2.8Analog-to-Digital Converter (618)
20.2.9Synchronous Serial Interface(SSI) (619)
20.2.10Inter-Integrated Circuit(I2C)Interface (620)
20.2.11Analog Comparator (621)
A Serial Flash Loader (622)
A.1Serial Flash Loader (622)
A.2Interfaces (622)
A.2.1UART (622)
A.2.2SSI (622)
A.3Packet Handling (623)
A.3.1Packet Format (623)
A.3.2Sending Packets (623)
A.3.3Receiving Packets (623)
A.4Commands (624)
A.4.1COMMAND_PING(0X20) (624)
A.4.2COMMAND_GET_STATUS(0x23) (624)
A.4.3COMMAND_DOWNLOAD(0x21) (624)
A.4.4COMMAND_SEND_DATA(0x24) (625)
A.4.5COMMAND_RUN(0x22) (625)
A.4.6COMMAND_RESET(0x25) (625)
B Register Quick Reference (627)
C Ordering and Contact Information (649)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller C.1Ordering Information (649)
C.2Part Markings (649)
C.3Kits (650)
C.4Support Information (650)
D Package Information (651)
D.1100-Pin LQFP Package (651)
D.1.1Package Dimensions (651)
D.1.2Tray Dimensions (653)
D.1.3Tape and Reel Dimensions (653)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
List of Figures
Figure1-1.Stellaris LM3S1636Microcontroller High-Level Block Diagram (41)
Figure2-1.CPU Block Diagram (50)
Figure2-2.TPIU Block Diagram (51)
Figure2-3.Cortex-M3Register Set (53)
Figure2-4.Bit-Band Mapping (73)
Figure2-5.Data Storage (74)
Figure2-6.Vector Table (80)
Figure2-7.Exception Stack Frame (82)
Figure3-1.SRD Use Example (96)
Figure4-1.JTAG Module Block Diagram (155)
Figure4-2.Test Access Port State Machine (158)
Figure4-3.IDCODE Register Format (164)
Figure4-4.BYPASS Register Format (164)
Figure4-5.Boundary Scan Register Format (165)
Figure5-1.Basic RST Configuration (168)
Figure5-2.External Circuitry to Extend Power-On Reset (169)
Figure5-3.Reset Circuit Controlled by Switch (169)
Figure5-4.Power Architecture (171)
Figure5-5.Main Clock Tree (174)
Figure6-1.Hibernation Module Block Diagram (234)
Figure6-2.Clock Source Using Crystal (236)
Figure6-3.Clock Source Using Dedicated Oscillator (236)
Figure7-1.Flash Block Diagram (254)
Figure8-1.GPIO Port Block Diagram (285)
Figure8-2.GPIODATA Write Example (286)
Figure8-3.GPIODATA Read Example (286)
Figure9-1.GPTM Module Block Diagram (327)
Figure9-2.16-Bit Input Edge Count Mode Example (331)
Figure9-3.16-Bit Input Edge Time Mode Example (332)
Figure9-4.16-Bit PWM Mode Example (333)
Figure10-1.WDT Module Block Diagram (363)
Figure11-1.ADC Module Block Diagram (387)
Figure11-2.Differential Sampling Range,V IN_ODD=1.5V (391)
Figure11-3.Differential Sampling Range,V IN_ODD=0.75V (391)
Figure11-4.Differential Sampling Range,V IN_ODD=2.25V (392)
Figure11-5.Internal Temperature Sensor Characteristic (393)
Figure12-1.UART Module Block Diagram (424)
Figure12-2.UART Character Frame (425)
Figure12-3.IrDA Data Modulation (427)
Figure13-1.SSI Module Block Diagram (465)
Figure13-2.TI Synchronous Serial Frame Format(Single Transfer) (468)
Figure13-3.TI Synchronous Serial Frame Format(Continuous Transfer) (469)
Figure13-4.Freescale SPI Format(Single Transfer)with SPO=0and SPH=0 (469)
Figure13-5.Freescale SPI Format(Continuous Transfer)with SPO=0and SPH=0 (470)
Figure13-6.Freescale SPI Frame Format with SPO=0and SPH=1 (471)
Figure13-7.Freescale SPI Frame Format(Single Transfer)with SPO=1and SPH=0 (471)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller Figure13-8.Freescale SPI Frame Format(Continuous Transfer)with SPO=1and SPH=0 (472)
Figure13-9.Freescale SPI Frame Format with SPO=1and SPH=1 (473)
Figure13-10.MICROWIRE Frame Format(Single Frame) (473)
Figure13-11.MICROWIRE Frame Format(Continuous Transfer) (474)
Figure13-12.MICROWIRE Frame Format,SSIFss Input Setup and Hold Requirements (475)
Figure14-1.I2C Block Diagram (504)
Figure14-2.I2C Bus Configuration (505)
Figure14-3.START and STOP Conditions (505)
https://www.wendangku.net/doc/4112329141.html,plete Data Transfer with a7-Bit Address (506)
Figure14-5.R/S Bit in First Byte (506)
Figure14-6.Data Validity During Bit Transfer on the I2C Bus (506)
Figure14-7.Master Single SEND (510)
Figure14-8.Master Single RECEIVE (511)
Figure14-9.Master Burst SEND (512)
Figure14-10.Master Burst RECEIVE (513)
Figure14-11.Master Burst RECEIVE after Burst SEND (514)
Figure14-12.Master Burst SEND after Burst RECEIVE (515)
Figure14-13.Slave Command Sequence (516)
Figure15-1.Analog Comparator Module Block Diagram (541)
Figure15-2.Structure of Comparator Unit (542)
https://www.wendangku.net/doc/4112329141.html,parator Internal Reference Structure (543)
Figure16-1.PWM Unit Diagram (553)
Figure16-2.PWM Module Block Diagram (554)
Figure16-3.PWM Count-Down Mode (555)
Figure16-4.PWM Count-Up/Down Mode (556)
Figure16-5.PWM Generation Example In Count-Up/Down Mode (556)
Figure16-6.PWM Dead-Band Generator (557)
Figure17-1.100-Pin LQFP Package Pin Diagram (591)
Figure20-1.Load Conditions (611)
Figure20-2.JTAG Test Clock Input Timing (614)
Figure20-3.JTAG Test Access Port(TAP)Timing (614)
Figure20-4.JTAG TRST Timing (614)
Figure20-5.External Reset Timing(RST) (615)
Figure20-6.Power-On Reset Timing (615)
Figure20-7.Brown-Out Reset Timing (616)
Figure20-8.Software Reset Timing (616)
Figure20-9.Watchdog Reset Timing (616)
Figure20-10.Hibernation Module Timing (617)
Figure20-11.ADC Input Equivalency Diagram (618)
Figure20-12.SSI Timing for TI Frame Format(FRF=01),Single Transfer Timing
Measurement (619)
Figure20-13.SSI Timing for MICROWIRE Frame Format(FRF=10),Single Transfer (620)
Figure20-14.SSI Timing for SPI Frame Format(FRF=00),with SPH=1 (620)
Figure20-15.I2C Timing (621)
Figure D-1.Stellaris LM3S1636100-Pin LQFP Package Dimensions (651)
Figure D-2.100-Pin LQFP Tray Dimensions (653)
Figure D-3.100-Pin LQFP Tape and Reel Dimensions (654)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
List of Tables
Table1.Revision History (23)
Table2.Documentation Conventions (30)
Table2-1.Summary of Processor Mode,Privilege Level,and Stack Use (53)
Table2-2.Processor Register Map (54)
Table2-3.PSR Register Combinations (59)
Table2-4.Memory Map (67)
Table2-5.Memory Access Behavior (69)
Table2-6.SRAM Memory Bit-Banding Regions (71)
Table2-7.Peripheral Memory Bit-Banding Regions (72)
Table2-8.Exception Types (77)
Table2-9.Interrupts (78)
Table2-10.Exception Return Behavior (83)
Table2-11.Faults (84)
Table2-12.Fault Status and Fault Address Registers (85)
Table2-13.Cortex-M3Instruction Summary (87)
Table3-1.Core Peripheral Register Regions (90)
Table3-2.Memory Attributes Summary (93)
Table3-3.TEX,S,C,and B Bit Field Encoding (96)
Table3-4.Cache Policy for Memory Attribute Encoding (97)
Table3-5.AP Bit Field Encoding (97)
Table3-6.Memory Region Attributes for Stellaris Microcontrollers (97)
Table3-7.Peripherals Register Map (98)
Table3-8.Interrupt Priority Levels (123)
Table3-9.Example SIZE Field Values (151)
Table4-1.JTAG_SWD_SWO Signals(100LQFP) (155)
Table4-2.JTAG Port Pins Reset State (156)
Table4-3.JTAG Instruction Register Commands (162)
Table5-1.System Control&Clocks Signals(100LQFP) (166)
Table5-2.Reset Sources (167)
Table5-3.Clock Source Options (172)
Table5-4.Possible System Clock Frequencies Using the SYSDIV Field (175)
Table5-5.Examples of Possible System Clock Frequencies Using the SYSDIV2Field (175)
Table5-6.System Control Register Map (179)
Table5-7.RCC2Fields that Override RCC fields (194)
Table6-1.Hibernate Signals(100LQFP) (234)
Table6-2.Hibernation Module Register Map (240)
Table7-1.Flash Protection Policy Combinations (255)
https://www.wendangku.net/doc/4112329141.html,er-Programmable Flash Memory Resident Registers (258)
Table7-3.Flash Register Map (258)
Table8-1.GPIO Pins With Non-Zero Reset Values (281)
Table8-2.GPIO Pins and Alternate Functions(100LQFP) (281)
Table8-3.GPIO Signals(100LQFP) (282)
Table8-4.GPIO Pad Configuration Examples (288)
Table8-5.GPIO Interrupt Configuration Example (288)
Table8-6.GPIO Register Map (290)
Table9-1.Available CCP Pins (327)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller Table9-2.General-Purpose Timers Signals(100LQFP) (328)
Table9-3.16-Bit Timer With Prescaler Configurations (330)
Table9-4.Timers Register Map (337)
Table10-1.Watchdog Timer Register Map (364)
Table11-1.ADC Signals(100LQFP) (387)
Table11-2.Samples and FIFO Depth of Sequencers (388)
Table11-3.Differential Sampling Pairs (390)
Table11-4.ADC Register Map (394)
Table12-1.UART Signals(100LQFP) (424)
Table12-2.UART Register Map (430)
Table13-1.SSI Signals(100LQFP) (466)
Table13-2.SSI Register Map (476)
Table14-1.I2C Signals(100LQFP) (504)
Table14-2.Examples of I2C Master Timer Period versus Speed Mode (507)
Table14-3.Inter-Integrated Circuit(I2C)Interface Register Map (517)
Table14-4.Write Field Decoding for I2CMCS[3:0]Field(Sheet1of3) (522)
Table15-1.Analog Comparators Signals(100LQFP) (541)
Table15-2.Internal Reference Voltage and ACREFCTL Field Values (543)
Table15-3.Analog Comparators Register Map (544)
Table16-1.PWM Signals(100LQFP) (554)
Table16-2.PWM Register Map (559)
Table18-1.Signals by Pin Number (592)
Table18-2.Signals by Signal Name (596)
Table18-3.Signals by Function,Except for GPIO (600)
Table18-4.GPIO Pins and Alternate Functions (604)
Table18-5.Connections for Unused Signals(100-pin LQFP) (606)
Table19-1.Temperature Characteristics (607)
Table19-2.Thermal Characteristics (607)
Table19-3.ESD Absolute Maximum Ratings (607)
Table20-1.Maximum Ratings (608)
Table20-2.Recommended DC Operating Conditions (608)
Table20-3.LDO Regulator Characteristics (609)
Table20-4.GPIO Module DC Characteristics (609)
Table20-5.Detailed Power Specifications (610)
Table20-6.Flash Memory Characteristics (611)
Table20-7.Hibernation Module DC Characteristics (611)
Table20-8.Phase Locked Loop(PLL)Characteristics (612)
Table20-9.Actual PLL Frequency (612)
Table20-10.Clock Characteristics (612)
Table20-11.Crystal Characteristics (613)
Table20-12.System Clock Characteristics with ADC Operation (613)
Table20-13.JTAG Characteristics (613)
Table20-14.Reset Characteristics (615)
Table20-15.Sleep Modes AC Characteristics (616)
Table20-16.Hibernation Module AC Characteristics (617)
Table20-17.GPIO Characteristics (617)
Table20-18.ADC Characteristics (618)
Table20-19.ADC Module Internal Reference Characteristics (619)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
Table20-20.SSI Characteristics (619)
Table20-21.I2C Characteristics (620)
Table20-22.Analog Comparator Characteristics (621)
Table20-23.Analog Comparator Voltage Reference Characteristics (621)
Table C-1.Part Ordering Information (649)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller
List of Registers
The Cortex-M3Processor (48)
Register1:Cortex General-Purpose Register0(R0) (55)
Register2:Cortex General-Purpose Register1(R1) (55)
Register3:Cortex General-Purpose Register2(R2) (55)
Register4:Cortex General-Purpose Register3(R3) (55)
Register5:Cortex General-Purpose Register4(R4) (55)
Register6:Cortex General-Purpose Register5(R5) (55)
Register7:Cortex General-Purpose Register6(R6) (55)
Register8:Cortex General-Purpose Register7(R7) (55)
Register9:Cortex General-Purpose Register8(R8) (55)
Register10:Cortex General-Purpose Register9(R9) (55)
Register11:Cortex General-Purpose Register10(R10) (55)
Register12:Cortex General-Purpose Register11(R11) (55)
Register13:Cortex General-Purpose Register12(R12) (55)
Register14:Stack Pointer(SP) (56)
Register15:Link Register(LR) (57)
Register16:Program Counter(PC) (58)
Register17:Program Status Register(PSR) (59)
Register18:Priority Mask Register(PRIMASK) (63)
Register19:Fault Mask Register(FAULTMASK) (64)
Register20:Base Priority Mask Register(BASEPRI) (65)
Register21:Control Register(CONTROL) (66)
Cortex-M3Peripherals (90)
Register1:SysTick Control and Status Register(STCTRL),offset0x010 (101)
Register2:SysTick Reload Value Register(STRELOAD),offset0x014 (103)
Register3:SysTick Current Value Register(STCURRENT),offset0x018 (104)
Register4:Interrupt0-31Set Enable(EN0),offset0x100 (105)
Register5:Interrupt32-43Set Enable(EN1),offset0x104 (106)
Register6:Interrupt0-31Clear Enable(DIS0),offset0x180 (107)
Register7:Interrupt32-43Clear Enable(DIS1),offset0x184 (108)
Register8:Interrupt0-31Set Pending(PEND0),offset0x200 (109)
Register9:Interrupt32-43Set Pending(PEND1),offset0x204 (110)
Register10:Interrupt0-31Clear Pending(UNPEND0),offset0x280 (111)
Register11:Interrupt32-43Clear Pending(UNPEND1),offset0x284 (112)
Register12:Interrupt0-31Active Bit(ACTIVE0),offset0x300 (113)
Register13:Interrupt32-43Active Bit(ACTIVE1),offset0x304 (114)
Register14:Interrupt0-3Priority(PRI0),offset0x400 (115)
Register15:Interrupt4-7Priority(PRI1),offset0x404 (115)
Register16:Interrupt8-11Priority(PRI2),offset0x408 (115)
Register17:Interrupt12-15Priority(PRI3),offset0x40C (115)
Register18:Interrupt16-19Priority(PRI4),offset0x410 (115)
Register19:Interrupt20-23Priority(PRI5),offset0x414 (115)
Register20:Interrupt24-27Priority(PRI6),offset0x418 (115)
Register21:Interrupt28-31Priority(PRI7),offset0x41C (115)
Register22:Interrupt32-35Priority(PRI8),offset0x420 (115)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
Register23:Interrupt36-39Priority(PRI9),offset0x424 (115)
Register24:Interrupt40-43Priority(PRI10),offset0x428 (115)
Register25:Software Trigger Interrupt(SWTRIG),offset0xF00 (117)
Register26:CPU ID Base(CPUID),offset0xD00 (118)
Register27:Interrupt Control and State(INTCTRL),offset0xD04 (119)
Register28:Vector Table Offset(VTABLE),offset0xD08 (122)
Register29:Application Interrupt and Reset Control(APINT),offset0xD0C (123)
Register30:System Control(SYSCTRL),offset0xD10 (125)
Register31:Configuration and Control(CFGCTRL),offset0xD14 (127)
Register32:System Handler Priority1(SYSPRI1),offset0xD18 (129)
Register33:System Handler Priority2(SYSPRI2),offset0xD1C (130)
Register34:System Handler Priority3(SYSPRI3),offset0xD20 (131)
Register35:System Handler Control and State(SYSHNDCTRL),offset0xD24 (132)
Register36:Configurable Fault Status(FAULTSTAT),offset0xD28 (136)
Register37:Hard Fault Status(HFAULTSTAT),offset0xD2C (142)
Register38:Memory Management Fault Address(MMADDR),offset0xD34 (143)
Register39:Bus Fault Address(FAULTADDR),offset0xD38 (144)
Register40:MPU Type(MPUTYPE),offset0xD90 (145)
Register41:MPU Control(MPUCTRL),offset0xD94 (146)
Register42:MPU Region Number(MPUNUMBER),offset0xD98 (148)
Register43:MPU Region Base Address(MPUBASE),offset0xD9C (149)
Register44:MPU Region Base Address Alias1(MPUBASE1),offset0xDA4 (149)
Register45:MPU Region Base Address Alias2(MPUBASE2),offset0xDAC (149)
Register46:MPU Region Base Address Alias3(MPUBASE3),offset0xDB4 (149)
Register47:MPU Region Attribute and Size(MPUATTR),offset0xDA0 (151)
Register48:MPU Region Attribute and Size Alias1(MPUATTR1),offset0xDA8 (151)
Register49:MPU Region Attribute and Size Alias2(MPUATTR2),offset0xDB0 (151)
Register50:MPU Region Attribute and Size Alias3(MPUATTR3),offset0xDB8 (151)
System Control (166)
Register1:Device Identification0(DID0),offset0x000 (181)
Register2:Brown-Out Reset Control(PBORCTL),offset0x030 (183)
Register3:LDO Power Control(LDOPCTL),offset0x034 (184)
Register4:Raw Interrupt Status(RIS),offset0x050 (185)
Register5:Interrupt Mask Control(IMC),offset0x054 (186)
Register6:Masked Interrupt Status and Clear(MISC),offset0x058 (187)
Register7:Reset Cause(RESC),offset0x05C (188)
Register8:Run-Mode Clock Configuration(RCC),offset0x060 (189)
Register9:XTAL to PLL Translation(PLLCFG),offset0x064 (193)
Register10:Run-Mode Clock Configuration2(RCC2),offset0x070 (194)
Register11:Deep Sleep Clock Configuration(DSLPCLKCFG),offset0x144 (196)
Register12:Device Identification1(DID1),offset0x004 (197)
Register13:Device Capabilities0(DC0),offset0x008 (199)
Register14:Device Capabilities1(DC1),offset0x010 (200)
Register15:Device Capabilities2(DC2),offset0x014 (202)
Register16:Device Capabilities3(DC3),offset0x018 (204)
Register17:Device Capabilities4(DC4),offset0x01C (206)
Register18:Run Mode Clock Gating Control Register0(RCGC0),offset0x100 (208)
Register19:Sleep Mode Clock Gating Control Register0(SCGC0),offset0x110 (210)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller Register20:Deep Sleep Mode Clock Gating Control Register0(DCGC0),offset0x120 (212)
Register21:Run Mode Clock Gating Control Register1(RCGC1),offset0x104 (214)
Register22:Sleep Mode Clock Gating Control Register1(SCGC1),offset0x114 (217)
Register23:Deep Sleep Mode Clock Gating Control Register1(DCGC1),offset0x124 (220)
Register24:Run Mode Clock Gating Control Register2(RCGC2),offset0x108 (223)
Register25:Sleep Mode Clock Gating Control Register2(SCGC2),offset0x118 (225)
Register26:Deep Sleep Mode Clock Gating Control Register2(DCGC2),offset0x128 (227)
Register27:Software Reset Control0(SRCR0),offset0x040 (229)
Register28:Software Reset Control1(SRCR1),offset0x044 (230)
Register29:Software Reset Control2(SRCR2),offset0x048 (232)
Hibernation Module (233)
Register1:Hibernation RTC Counter(HIBRTCC),offset0x000 (242)
Register2:Hibernation RTC Match0(HIBRTCM0),offset0x004 (243)
Register3:Hibernation RTC Match1(HIBRTCM1),offset0x008 (244)
Register4:Hibernation RTC Load(HIBRTCLD),offset0x00C (245)
Register5:Hibernation Control(HIBCTL),offset0x010 (246)
Register6:Hibernation Interrupt Mask(HIBIM),offset0x014 (248)
Register7:Hibernation Raw Interrupt Status(HIBRIS),offset0x018 (249)
Register8:Hibernation Masked Interrupt Status(HIBMIS),offset0x01C (250)
Register9:Hibernation Interrupt Clear(HIBIC),offset0x020 (251)
Register10:Hibernation RTC Trim(HIBRTCT),offset0x024 (252)
Register11:Hibernation Data(HIBDATA),offset0x030-0x12C (253)
Internal Memory (254)
Register1:Flash Memory Address(FMA),offset0x000 (260)
Register2:Flash Memory Data(FMD),offset0x004 (261)
Register3:Flash Memory Control(FMC),offset0x008 (262)
Register4:Flash Controller Raw Interrupt Status(FCRIS),offset0x00C (264)
Register5:Flash Controller Interrupt Mask(FCIM),offset0x010 (265)
Register6:Flash Controller Masked Interrupt Status and Clear(FCMISC),offset0x014 (266)
Register7:USec Reload(USECRL),offset0x140 (268)
Register8:Flash Memory Protection Read Enable0(FMPRE0),offset0x130and0x200 (269)
Register9:Flash Memory Protection Program Enable0(FMPPE0),offset0x134and0x400 (270)
Register10:User Debug(USER_DBG),offset0x1D0 (271)
Register11:User Register0(USER_REG0),offset0x1E0 (272)
Register12:User Register1(USER_REG1),offset0x1E4 (273)
Register13:Flash Memory Protection Read Enable1(FMPRE1),offset0x204 (274)
Register14:Flash Memory Protection Read Enable2(FMPRE2),offset0x208 (275)
Register15:Flash Memory Protection Read Enable3(FMPRE3),offset0x20C (276)
Register16:Flash Memory Protection Program Enable1(FMPPE1),offset0x404 (277)
Register17:Flash Memory Protection Program Enable2(FMPPE2),offset0x408 (278)
Register18:Flash Memory Protection Program Enable3(FMPPE3),offset0x40C (279)
General-Purpose Input/Outputs(GPIOs) (280)
Register1:GPIO Data(GPIODATA),offset0x000 (292)
Register2:GPIO Direction(GPIODIR),offset0x400 (293)
Register3:GPIO Interrupt Sense(GPIOIS),offset0x404 (294)
Register4:GPIO Interrupt Both Edges(GPIOIBE),offset0x408 (295)
Register5:GPIO Interrupt Event(GPIOIEV),offset0x40C (296)
Register6:GPIO Interrupt Mask(GPIOIM),offset0x410 (297)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
Register7:GPIO Raw Interrupt Status(GPIORIS),offset0x414 (298)
Register8:GPIO Masked Interrupt Status(GPIOMIS),offset0x418 (299)
Register9:GPIO Interrupt Clear(GPIOICR),offset0x41C (300)
Register10:GPIO Alternate Function Select(GPIOAFSEL),offset0x420 (301)
Register11:GPIO2-mA Drive Select(GPIODR2R),offset0x500 (303)
Register12:GPIO4-mA Drive Select(GPIODR4R),offset0x504 (304)
Register13:GPIO8-mA Drive Select(GPIODR8R),offset0x508 (305)
Register14:GPIO Open Drain Select(GPIOODR),offset0x50C (306)
Register15:GPIO Pull-Up Select(GPIOPUR),offset0x510 (307)
Register16:GPIO Pull-Down Select(GPIOPDR),offset0x514 (308)
Register17:GPIO Slew Rate Control Select(GPIOSLR),offset0x518 (309)
Register18:GPIO Digital Enable(GPIODEN),offset0x51C (310)
Register19:GPIO Lock(GPIOLOCK),offset0x520 (311)
Register20:GPIO Commit(GPIOCR),offset0x524 (312)
Register21:GPIO Peripheral Identification4(GPIOPeriphID4),offset0xFD0 (314)
Register22:GPIO Peripheral Identification5(GPIOPeriphID5),offset0xFD4 (315)
Register23:GPIO Peripheral Identification6(GPIOPeriphID6),offset0xFD8 (316)
Register24:GPIO Peripheral Identification7(GPIOPeriphID7),offset0xFDC (317)
Register25:GPIO Peripheral Identification0(GPIOPeriphID0),offset0xFE0 (318)
Register26:GPIO Peripheral Identification1(GPIOPeriphID1),offset0xFE4 (319)
Register27:GPIO Peripheral Identification2(GPIOPeriphID2),offset0xFE8 (320)
Register28:GPIO Peripheral Identification3(GPIOPeriphID3),offset0xFEC (321)
Register29:GPIO PrimeCell Identification0(GPIOPCellID0),offset0xFF0 (322)
Register30:GPIO PrimeCell Identification1(GPIOPCellID1),offset0xFF4 (323)
Register31:GPIO PrimeCell Identification2(GPIOPCellID2),offset0xFF8 (324)
Register32:GPIO PrimeCell Identification3(GPIOPCellID3),offset0xFFC (325)
General-Purpose Timers (326)
Register1:GPTM Configuration(GPTMCFG),offset0x000 (338)
Register2:GPTM TimerA Mode(GPTMTAMR),offset0x004 (339)
Register3:GPTM TimerB Mode(GPTMTBMR),offset0x008 (341)
Register4:GPTM Control(GPTMCTL),offset0x00C (343)
Register5:GPTM Interrupt Mask(GPTMIMR),offset0x018 (346)
Register6:GPTM Raw Interrupt Status(GPTMRIS),offset0x01C (348)
Register7:GPTM Masked Interrupt Status(GPTMMIS),offset0x020 (349)
Register8:GPTM Interrupt Clear(GPTMICR),offset0x024 (350)
Register9:GPTM TimerA Interval Load(GPTMTAILR),offset0x028 (352)
Register10:GPTM TimerB Interval Load(GPTMTBILR),offset0x02C (353)
Register11:GPTM TimerA Match(GPTMTAMATCHR),offset0x030 (354)
Register12:GPTM TimerB Match(GPTMTBMATCHR),offset0x034 (355)
Register13:GPTM TimerA Prescale(GPTMTAPR),offset0x038 (356)
Register14:GPTM TimerB Prescale(GPTMTBPR),offset0x03C (357)
Register15:GPTM TimerA Prescale Match(GPTMTAPMR),offset0x040 (358)
Register16:GPTM TimerB Prescale Match(GPTMTBPMR),offset0x044 (359)
Register17:GPTM TimerA(GPTMTAR),offset0x048 (360)
Register18:GPTM TimerB(GPTMTBR),offset0x04C (361)
Watchdog Timer (362)
Register1:Watchdog Load(WDTLOAD),offset0x000 (366)
Register2:Watchdog Value(WDTVALUE),offset0x004 (367)
OBSOLETE: TI has discontinued production of this device.
Stellaris?LM3S1636Microcontroller Register3:Watchdog Control(WDTCTL),offset0x008 (368)
Register4:Watchdog Interrupt Clear(WDTICR),offset0x00C (369)
Register5:Watchdog Raw Interrupt Status(WDTRIS),offset0x010 (370)
Register6:Watchdog Masked Interrupt Status(WDTMIS),offset0x014 (371)
Register7:Watchdog Test(WDTTEST),offset0x418 (372)
Register8:Watchdog Lock(WDTLOCK),offset0xC00 (373)
Register9:Watchdog Peripheral Identification4(WDTPeriphID4),offset0xFD0 (374)
Register10:Watchdog Peripheral Identification5(WDTPeriphID5),offset0xFD4 (375)
Register11:Watchdog Peripheral Identification6(WDTPeriphID6),offset0xFD8 (376)
Register12:Watchdog Peripheral Identification7(WDTPeriphID7),offset0xFDC (377)
Register13:Watchdog Peripheral Identification0(WDTPeriphID0),offset0xFE0 (378)
Register14:Watchdog Peripheral Identification1(WDTPeriphID1),offset0xFE4 (379)
Register15:Watchdog Peripheral Identification2(WDTPeriphID2),offset0xFE8 (380)
Register16:Watchdog Peripheral Identification3(WDTPeriphID3),offset0xFEC (381)
Register17:Watchdog PrimeCell Identification0(WDTPCellID0),offset0xFF0 (382)
Register18:Watchdog PrimeCell Identification1(WDTPCellID1),offset0xFF4 (383)
Register19:Watchdog PrimeCell Identification2(WDTPCellID2),offset0xFF8 (384)
Register20:Watchdog PrimeCell Identification3(WDTPCellID3),offset0xFFC (385)
Analog-to-Digital Converter(ADC) (386)
Register1:ADC Active Sample Sequencer(ADCACTSS),offset0x000 (396)
Register2:ADC Raw Interrupt Status(ADCRIS),offset0x004 (397)
Register3:ADC Interrupt Mask(ADCIM),offset0x008 (398)
Register4:ADC Interrupt Status and Clear(ADCISC),offset0x00C (399)
Register5:ADC Overflow Status(ADCOSTAT),offset0x010 (400)
Register6:ADC Event Multiplexer Select(ADCEMUX),offset0x014 (401)
Register7:ADC Underflow Status(ADCUSTAT),offset0x018 (405)
Register8:ADC Sample Sequencer Priority(ADCSSPRI),offset0x020 (406)
Register9:ADC Processor Sample Sequence Initiate(ADCPSSI),offset0x028 (408)
Register10:ADC Sample Averaging Control(ADCSAC),offset0x030 (409)
Register11:ADC Sample Sequence Input Multiplexer Select0(ADCSSMUX0),offset0x040 (410)
Register12:ADC Sample Sequence Control0(ADCSSCTL0),offset0x044 (412)
Register13:ADC Sample Sequence Result FIFO0(ADCSSFIFO0),offset0x048 (415)
Register14:ADC Sample Sequence Result FIFO1(ADCSSFIFO1),offset0x068 (415)
Register15:ADC Sample Sequence Result FIFO2(ADCSSFIFO2),offset0x088 (415)
Register16:ADC Sample Sequence Result FIFO3(ADCSSFIFO3),offset0x0A8 (415)
Register17:ADC Sample Sequence FIFO0Status(ADCSSFSTAT0),offset0x04C (416)
Register18:ADC Sample Sequence FIFO1Status(ADCSSFSTAT1),offset0x06C (416)
Register19:ADC Sample Sequence FIFO2Status(ADCSSFSTAT2),offset0x08C (416)
Register20:ADC Sample Sequence FIFO3Status(ADCSSFSTAT3),offset0x0AC (416)
Register21:ADC Sample Sequence Input Multiplexer Select1(ADCSSMUX1),offset0x060 (417)
Register22:ADC Sample Sequence Input Multiplexer Select2(ADCSSMUX2),offset0x080 (417)
Register23:ADC Sample Sequence Control1(ADCSSCTL1),offset0x064 (418)
Register24:ADC Sample Sequence Control2(ADCSSCTL2),offset0x084 (418)
Register25:ADC Sample Sequence Input Multiplexer Select3(ADCSSMUX3),offset0x0A0 (420)
Register26:ADC Sample Sequence Control3(ADCSSCTL3),offset0x0A4 (421)
Register27:ADC Test Mode Loopback(ADCTMLB),offset0x100 (422)
Universal Asynchronous Receivers/Transmitters(UARTs) (423)
Register1:UART Data(UARTDR),offset0x000 (432)
OBSOLETE: TI has discontinued production of this device.
Table of Contents
Register2:UART Receive Status/Error Clear(UARTRSR/UARTECR),offset0x004 (434)
Register3:UART Flag(UARTFR),offset0x018 (436)
Register4:UART IrDA Low-Power Register(UARTILPR),offset0x020 (438)
Register5:UART Integer Baud-Rate Divisor(UARTIBRD),offset0x024 (439)
Register6:UART Fractional Baud-Rate Divisor(UARTFBRD),offset0x028 (440)
Register7:UART Line Control(UARTLCRH),offset0x02C (441)
Register8:UART Control(UARTCTL),offset0x030 (443)
Register9:UART Interrupt FIFO Level Select(UARTIFLS),offset0x034 (445)
Register10:UART Interrupt Mask(UARTIM),offset0x038 (447)
Register11:UART Raw Interrupt Status(UARTRIS),offset0x03C (449)
Register12:UART Masked Interrupt Status(UARTMIS),offset0x040 (450)
Register13:UART Interrupt Clear(UARTICR),offset0x044 (451)
Register14:UART Peripheral Identification4(UARTPeriphID4),offset0xFD0 (453)
Register15:UART Peripheral Identification5(UARTPeriphID5),offset0xFD4 (454)
Register16:UART Peripheral Identification6(UARTPeriphID6),offset0xFD8 (455)
Register17:UART Peripheral Identification7(UARTPeriphID7),offset0xFDC (456)
Register18:UART Peripheral Identification0(UARTPeriphID0),offset0xFE0 (457)
Register19:UART Peripheral Identification1(UARTPeriphID1),offset0xFE4 (458)
Register20:UART Peripheral Identification2(UARTPeriphID2),offset0xFE8 (459)
Register21:UART Peripheral Identification3(UARTPeriphID3),offset0xFEC (460)
Register22:UART PrimeCell Identification0(UARTPCellID0),offset0xFF0 (461)
Register23:UART PrimeCell Identification1(UARTPCellID1),offset0xFF4 (462)
Register24:UART PrimeCell Identification2(UARTPCellID2),offset0xFF8 (463)
Register25:UART PrimeCell Identification3(UARTPCellID3),offset0xFFC (464)
Synchronous Serial Interface(SSI) (465)
Register1:SSI Control0(SSICR0),offset0x000 (478)
Register2:SSI Control1(SSICR1),offset0x004 (480)
Register3:SSI Data(SSIDR),offset0x008 (482)
Register4:SSI Status(SSISR),offset0x00C (483)
Register5:SSI Clock Prescale(SSICPSR),offset0x010 (485)
Register6:SSI Interrupt Mask(SSIIM),offset0x014 (486)
Register7:SSI Raw Interrupt Status(SSIRIS),offset0x018 (488)
Register8:SSI Masked Interrupt Status(SSIMIS),offset0x01C (489)
Register9:SSI Interrupt Clear(SSIICR),offset0x020 (490)
Register10:SSI Peripheral Identification4(SSIPeriphID4),offset0xFD0 (491)
Register11:SSI Peripheral Identification5(SSIPeriphID5),offset0xFD4 (492)
Register12:SSI Peripheral Identification6(SSIPeriphID6),offset0xFD8 (493)
Register13:SSI Peripheral Identification7(SSIPeriphID7),offset0xFDC (494)
Register14:SSI Peripheral Identification0(SSIPeriphID0),offset0xFE0 (495)
Register15:SSI Peripheral Identification1(SSIPeriphID1),offset0xFE4 (496)
Register16:SSI Peripheral Identification2(SSIPeriphID2),offset0xFE8 (497)
Register17:SSI Peripheral Identification3(SSIPeriphID3),offset0xFEC (498)
Register18:SSI PrimeCell Identification0(SSIPCellID0),offset0xFF0 (499)
Register19:SSI PrimeCell Identification1(SSIPCellID1),offset0xFF4 (500)
Register20:SSI PrimeCell Identification2(SSIPCellID2),offset0xFF8 (501)
Register21:SSI PrimeCell Identification3(SSIPCellID3),offset0xFFC (502)
Inter-Integrated Circuit(I2C)Interface (503)
Register1:I2C Master Slave Address(I2CMSA),offset0x000 (519)