镁光 4G 黑片 低成本 BW29F32G08CBABA_BIWIN_L63B_Specification_V1.0

NAND Flash Memory BW29F32G08CBABA

Features

? Multiple-level cell (MLC) technology

? Organization

– Page size x8: 4320 bytes (4096 + 224 bytes) – Block size: 256 pages (1024K + 56K bytes) – Plane size: 2 planes x 2048 blocks per plane – Device size: 32Gb: 4096 blocks;

? Asynchronous I/O performance

– Up to asynchronous timing mode 5

– t RC/t WC: 25ns (MIN)

? Array performance

– Read page: 50μs (MAX)

– Program page: 900μs (TYP)

– Erase block: 3ms (TYP)

? Operating Voltage Range

– VCC: 2.7–3.6V

– VCCQ: 2.7–3.6V

? Advanced Command Set

– Program cache

– Read cache sequential

– Read cache random

– One-time programmable (OTP) mode

– Multi-plane commands

– Multi-LUN operations

– Read unique ID

– Copyback ? First block (block address 00h) is valid when shipped from factory. For minimum required ECC is 12-bit ECC per 540 bytes of data ? RESET (FFh) required as first command after power-on

? Operation status byte provides software method for detecting

– Operation completion

– Pass/fail condition

– Write-protect status

? Copyback operations supported within the plane from which data is read

? Quality and reliability

– Data retention: 10 years

– Endurance: 10,000 PROGRAM/ERASE cycles

? Operating temperature:

– Commercial: 0°C to +70°C

– Industrial (IT): –40°C to +85°C

? Package

– 48-pin TSOP

Other spec refer to Micron datasheet

Part Numbering Information Figure 1: Part Numbering

Note: 1. Pb-free package.

Signal Assignments Signal Assignments

Figure 2: 48-Pin TSOP Type 1 (Top View)

Notes: Each power and ground signal must be connected

Package Dimensions Package Dimensions

Figure 3: 48-Pin TSOP – Type 1 CPL (Package Code: WP)

Note: 1. All dimensions are in millimeters.

Architecture Architecture

These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address.

Data is transferred to or from the NAND Flash memory array, byte by byte, through a data register and a cache register.

The NAND Flash memory array is programmed and read using page-based operations and is erased using block-based operations. During normal page operations, the data and cache registers act as a single register. During cache operations, the data and cache registers operate independently to increase data throughput. The status register reports the status of die (LUN) operations.

Figure 4: NAND Flash Die (LUN) Function Block Diagram