final_f07

EE5323 VLSI Design I (total 40 points)
Final exam: 8am-10am (120 mins), Dec. 18th, 2007 (Open book, open notes, calculators allowed) NAME:
ALL ANSWERS MUST BE ACCOMPANIED BY EXPLANATIONS. PLEASE READ THE ASSUMPTIONS IN EACH QUESTION VERY CAREFULLY! 1. Leakage current (8 pts) Vdd = 1.0 V , Vt = 0.2 V λd = 100 mV / V ( DIBL coefficient ) γ = 100 mV / V ( body effect factor ) S = 100 mV / dec ( sub ? threshold swing ) (a) [4 pts] The virtual ground (Vgnd) voltage is raised from 0V to 0.1V while the virtual Vdd (VVdd) is kept at 1.0V. What is the percentage reduction in sub-threshold leakage current for this inverter?
(b) [4 pts] Conversely, the virtual Vdd (VVdd) is lowered from 1.0V to 0.9V while keeping the virtual ground (Vgnd) at 0V. What is the percentage reduction in sub-threshold leakage current for this inverter?
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2. Circuit design (4 pts) Design a simple digital circuit that has a smaller delay for a rising input than for a falling input. The absolute delay values are not important but should be kept reasonably small.
3. Circuit delay (6 pts)
Consider a ring oscillator that consists of inverter stages with alternating device sizes; i.e. inverters in every other stage are three times larger than the rest inverters. What is the ratio between the period of the given ring oscillator and the period of a normal ring oscillator with identically sized inverters? Assume that tpHL=tpLH for each inverter and γ=1 (Cint=Cgate).
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4. Timing (6 pts)
A chain of registers are used to serially scan data into a microprocessor for testing purposes. (a) [3 pts] What is the single most important timing hazard for the above circuit?
(b) [3 pts] Fix the timing hazard by modifying the circuit.
5. Domino logic (8 pts) For an arbitrary keeper size, a non-stacked domino gate fails when there are more than 8 pull-down branches. Each pull-down device has the same width with different input signals.
(a) [4 pts] Explain the reason for this failure in a couple of sentences.
(b) [4 pts] What is the maximum number of pull-down branches allowed for the domino gate on the far right which has two-stacked NMOS pull-down devices? Assume that devices in the stacks have the same widths. Briefly explain your answer.
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6. Power supply noise (8 pts) Consider a switched-capacitor circuit to regulate AC power supply noise. The three capacitors are switched to a series connection when a supply undershoot is detected and to a parallel connection when an overshoot is detected. (a) [4 pts] Compared to just using the three capacitors in parallel all the time, how much boost in damping charge (i.e. ?Qp/?Qc in the class notes) do we gain by actively switching their configuration? Consider the supply undershoot case (i.e. parallel to series switching) and assume that the supply noise is 5% of the nominal supply voltage.
(b) [4 pts] Which one is more effective in damping the AC supply noise; two switched-capacitors or three switched-capacitors? Consider the supply undershoot case (i.e. parallel to series switching) and assume that the supply noise is 5% of the nominal supply voltage. Give a quantitative answer.
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