ICE3A5565P中文资料
Datasheet, V1.3, 15 Sep 2004
CoolSET?-F3
ICE3A(B)0365/0565/1065/1565 ICE3A(B)2065/2565
ICE3A0565Z/2065Z
ICE3A(B)2065I/3065I/3565I
ICE3A(B)5065I/5565I
ICE3A(B)2065P/3065P/3565P
ICE3A(B)5065P/5565P
Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/CoolMOS?
Power Management & Supply
Edition 2004-09-15
Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München
? Infineon Technologies AG 1999. All Rights Reserved.
Attention please!
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CoolSET?-F3
Revision History: 2004-09-15 Datasheet Previous Version:Page
Subjects (major changes since last revision)
CoolSET?-F3
Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/CoolMOS?
Product Highlights
?Best in class in DIP7, DIP8, TO220, I2Pak packages ?Leadfree for DIP7 and DIP8 packages
?Active Burst Mode to reach the lowest Standby Power Requirements < 100mW
?Protection features (Auto Restart Mode) to increase robustness and safety of the system
?Adjustable Blanking Window for high load jumps to increase system reliability
?Isolated drain package for TO220/I2PAK
?Increased creepage distance for TO220/I2PAK
?Wide power class of products for various applications
Features
?650V avalanche rugged CoolMOS? with built in switchable Startup Cell
?Active Burst Mode for lowest Standby Power @ light load controlled by Feedback signal ?
Fast load jump response in Active Burst Mode ?67/100 kHz fixed switching frequency
?Auto Restart Mode for Overtemperature Detection ?Auto Restart Mode for Overvoltage Detection ?Auto Restart Mode for Overload and Open Loop ?Auto Restart Mode for VCC Undervoltage
?Blanking Window for short duration high current ?User defined Soft Start
?Minimum of external components required ?Max Duty Cycle 72%
?Overall tolerance of Current Limiting < ±5%?Internal PWM Leading Edge Blanking ?
Soft switching for low EMI
Description
The new generation CoolSET?-F3 provides Active Burst Mode to reach the lowest Standby Power Requirements <100mW at no load. As the controller is always active during Active Burst Mode, there is an immediate response on load jumps without any black out in the SMPS. In Active Burst Mode the ripple of the output voltage can be reduced <1%. Furthermore, to increase the robustness and safety of the system, the device enters into Auto Restart Mode in the cases of Overtemperature, VCC Overvoltage, Output Open Loop or Overload and VCC Undervoltage. By means of the internal precise peak current limitation, the dimension of the transformer and the secondary diode can be lowered which leads to more cost efficiency. An adjustable blanking window prevents the IC from entering Auto Restart or Active Burst Mode unintentionally during high load jumps. The CoolSET?-F3 family consists a wide power class range of products for various applications.
Ordering Codes
Type Ordering Code Package V DS F OSC R DSon 1)1)typ @ T=25°C
230VAC ±15%2)
2)
Calculated maximum input power rating at T a =75°C, T j =125°C and without copper area as heat sink.
85-265 VAC 2)
ICE3A0365Q67040-S4666-A101PG-DIP-8-6650V 100kHz 6.4522W 10W ICE3A0565Q67040-S4665-A101PG-DIP-8-6650V 100kHz 4.7025W 12W ICE3A1065Q67040-S4664-A101PG-DIP-8-6650V 100kHz 2.9532W 16W ICE3A1565Q67040-S4663-A101PG-DIP-8-6650V 100kHz 1.7042W 20W ICE3A2065Q67040-S4662-A101PG-DIP-8-6650V 100kHz 0.9257W 28W ICE3A2565Q67040-S4667-A101PG-DIP-8-6650V 100kHz 0.6568W 33W ICE3B0365Q67040-S4636-A102PG-DIP-8-6650V 67kHz 6.4522W 10W ICE3B0565Q67040-S4638-A102PG-DIP-8-6650V 67kHz 4.7025W 12W ICE3B1065Q67040-S4669-A101PG-DIP-8-6650V 67kHz 2.9532W 16W ICE3B1565Q67040-S4670-A101PG-DIP-8-6650V 67kHz 1.7042W 20W ICE3B2065Q67040-S4671-A101PG-DIP-8-6650V 67kHz 0.9257W 28W ICE3B2565
Q67040-S4668-A101
PG-DIP-8-6
650V
67kHz
0.65
68W
33W
Type Ordering Code Package V DS F OSC R DSon 1)1)typ @ T=25°C
230VAC ±15%2)
2)
Calculated maximum input power rating at T a =75°C, T j =125°C and without copper area as heat sink.
85-265 VAC 2)
ICE3A0565Z Q67040-S4706-A101PG-DIP-7-1650V 100kHz 4.7025W 12W ICE3A2065Z
Q67040-S4707-A101
PG-DIP-7-1
650V
100kHz
0.92
57W
28W
Type Ordering Code Package V DS F OSC R DSon1)230VAC ±15%2)85-265 VAC2) ICE3A2065I Q67040-S4696-A101P-TO-220-6-46650V100kHz 3.00102W50W ICE3A3065I Q67040-S4697-A101P-TO-220-6-46650V100kHz 2.10128W62W ICE3A3565I Q67040-S4699-A101P-TO-220-6-46650V100kHz 1.55170W83W ICE3A5065I Q67040-S4702-A101P-TO-220-6-46650V100kHz0.95220W105W ICE3A5565I Q67040-S4704-A101P-TO-220-6-46650V100kHz0.79240W120W ICE3B2065I Q67040-S4686-A101P-TO-220-6-46650V67kHz 3.00102W50W ICE3B3065I Q67040-S4687-A101P-TO-220-6-46650V67kHz 2.10128W62W ICE3B3565I Q67040-S4689-A101P-TO-220-6-46650V67kHz 1.55170W83W ICE3B5065I Q67040-S4692-A101P-TO-220-6-46650V67kHz0.95220W105W ICE3B5565I Q67040-S4694-A101P-TO-220-6-46650V67kHz0.79240W120W ICE3A2065P Q67040-S4698-A101P-TO-220-6-47650V100kHz 3.00102W50W ICE3A3065P Q67040-S4700-A101P-TO-220-6-47650V100kHz 2.10128W62W ICE3A3565P Q67040-S4701-A101P-TO-220-6-47650V100kHz 1.55170W83W ICE3A5065P Q67040-S4703-A101P-TO-220-6-47650V100kHz0.95220W105W ICE3A5565P Q67040-S4705-A101P-TO-220-6-47650V100kHz0.79240W120W ICE3B2065P Q67040-S4688-A101P-TO-220-6-47650V67kHz 3.00102W50W ICE3B3065P Q67040-S4690-A101P-TO-220-6-47650V67kHz 2.10128W62W ICE3B3565P Q67040-S4691-A101P-TO-220-6-47650V67kHz 1.55170W83W ICE3B5065P Q67040-S4693-A101P-TO-220-6-47650V67kHz0.95220W105W ICE3B5565P Q67040-S4695-A101P-TO-220-6-47650V67kHz0.79240W120W
1)typ @ T=25°C
2)Calculated maximum continuous input power in an open frame design at T
=50°C, T j=125°C and R thCA(external heatsink)=2.7K/W
a
Table of Contents Page 1Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2Pin Configuration with PG-DIP-7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3Pin Configuration with P-TO220-6-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.4Pin Configuration with P-TO220-6-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.5Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.4PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.4.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.4.2PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.4.3Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.5Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.5.1Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.5.2Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.6Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.6.1Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.6.2Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.6.2.1Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.6.2.2Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.6.2.3Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.6.3Protection Mode (Auto Restart Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3.1Supply Section 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3.2Supply Section 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3.3Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.3.4PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.3.5Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.3.6Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.3.7CoolMOS? Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1
Pin Configuration and Functionality
1.1
Pin Configuration with PG-DIP-8-6
Figure 1Pin Configuration PG-DIP-8-6(top view)
Note: Pin 4 and 5 are shorted within the DIP 8 package.
1.2Pin Configuration with PG-DIP-7-1
Figure 2Pin Configuration PG-DIP-7-1(top view)
Pin Symbol Function 1SoftS Soft-Start 2FB Feedback
3CS Current Sense/
650V 1) Depl-CoolMOS? Source 1)
at T j = 110°C
4Drain 650V 1) Depl-CoolMOS? Drain 5Drain
650V 1) Depl-CoolMOS? Drain 6n.c.Not Connected
7VCC Controller Supply Voltage 8
GND
Controller Ground
Pin Symbol Function 1SoftS Soft-Start 2FB Feedback
3CS Current Sense/
650V 1) Depl-CoolMOS? Source 1)
at T j = 110°C
4n.c.Not connected
5Drain 650V 1) Depl-CoolMOS? Drain ---7VCC Controller Supply Voltage 8
GND
Controller Ground
Figure 3Pin Configuration P-TO220-6-46(top view)
1.4Pin Configuration with P-TO220-6-47
Figure 4Pin Configuration P-TO220-6-47(top view)
1.3Pin Configuration with P-TO220-6-46Pin Symbol Function
1Drain 650V 1)
Depl-CoolMOS? Drain 3CS Current Sense/
650V 1) Depl-CoolMOS? Source 4GND Controller Ground 5VCC Controller Supply Voltage 6SoftS Soft-Start 7
FB
Feedback
1)
at T j = 110°C
Pin Symbol Function
1Drain 650V 1)
Depl-CoolMOS? Drain 1)
at T j = 110°C
3CS Current Sense/
650V 1) Depl-CoolMOS? Source 4GND Controller Ground 5VCC Controller Supply Voltage 6SoftS Soft-Start 7
FB
Feedback
1.5Pin Functionality
SoftS (Soft Start & Auto Restart Control)
The SoftS pin combines the functions of Soft Start during Start Up and error detection for Auto Restart Mode. These functions are implemented and can be adjusted by means of an external capacitor at SoftS to ground. This capacitor also provides an adjustable blanking window for high load jumps, before the IC enters into Auto Restart Mode.
FB (Feedback)
The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWM-Comparator to control the duty cycle. The FB-Signal controls in case of light load the Active Burst Mode of the controller.
CS (Current Sense)
The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the integrated Depl-CoolMOS?. If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWM-Comparator to realize the Current Mode.
Drain (Drain of integrated Depl-CoolMOS?)
Pin Drain is the connection to the Drain of the internal Depl-CoolMOS TM.
VCC (Power supply)
The VCC pin is the positive supply of the IC. The operating range is between 8.5V and 21V.
GND (Ground)
The GND pin is the ground of the controller.
CoolSET?-F3
Representative Blockdiagram 2Representative Blockdiagram
Figure 5Representative Blockdiagram
3Functional Description
All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.
3.1Introduction
CoolSET?-F3 is the further development of the CoolSET?-F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions. A new fully integrated Standby Power
concept is implemented into the IC in order to keep the
application design easy. Compared to CoolSET?-F2 no further external parts are needed to achieve the lowest Standby Power. An intelligent Active Burst Mode is used for this Standby Mode. After entering this
mode there is still a full control of the power conversion
by the secondary side via the same optocoupler that is
used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on V out is minimized. V out is further on well controlled in this
mode.
The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count.
Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 15V is exceeded. This Startup Cell is part of the integrated Depl-CoolMOS?. The
external startup resistor is no longer necessary as this
Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically.
The Soft-Start capacitor is also used for providing an adjustable blanking window for high load jumps. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window.
An Auto Restart Mode is implemented in the IC to
reduce the average power conversion in the event of
malfunction or unsafe operating condition in the SMPS
system. This feature increases the system’s
robustness and safety which would otherwise lead to a
destruction of the SMPS. Once the malfunction is
removed, normal operation is automatically initiated
after the next Start Up Phase.
The internal precise peak current limitation reduces the
costs for the transformer and the secondary diode. The influence of the change in the input voltage on the power limitation can be avoided together with the integrated Propagation Delay Compensation.
Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or the secondary diode.
3.2Power Management
Figure 6Power Management
The Undervoltage Lockout monitors the external supply voltage V VCC . When the SMPS is plugged to the
main line the internal Startup Cell is biased and starts to charge the external capacitor C VCC which is connected to the VCC pin. This VCC charge current which is provided by the Startup Cell from the Drain pin is 1.05mA. When V VCC exceeds the on-threshold
V CCon =15V the internal voltage reference and bias circuit are switched on. Then the Startup Cell is
switched off by the Undervoltage Lockout and therefore
no power losses present due to the connection of the
Startup Cell to the Drain voltage. To avoid uncontrolled
ringing at switch-on a hysteresis is implemented. The
switch-off of the controller can only take place after
Active Mode was entered and V VCC falls below 8.5V.
The maximum current consumption before the controller is activated is about 160μA.
When V VCC falls below the off-threshold V CCoff =8.5V the internal reference is switched off and the Power Down reset let T1 discharging the soft-start capacitor C SoftS at
pin SoftS. Thus it is ensured that at every startup cycle the voltage ramp at pin SoftS starts at zero.
The internal Voltage Reference is switched off if Auto Restart Mode is entered. The current consumption is
then reduced to 300μA.
Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require disconnecting the SMPS from the AC line
When Active Burst Mode is entered, the internal Bias is switched off in order to reduce the current consumption to below 1.05mA while keeping the Voltage Reference active as this is necessary in this mode.
3.3Startup Phase
Figure 7Soft Start
At the beginning of the Startup Phase, the IC provides a Soft Start duration whereby it controls the maximum primary current by means of a duty cycle limitation. A signal V SoftS which is generated by the external capacitor C Softs in combination with the internal pull up resistor R SoftS, determines the duty cycle until V SoftS exceeds 4V.
When the Soft Start begins, C SoftS is immediately charged up to approx. 1V by T2. Therefore the Soft Start Phase takes place between 1V and 4V. Above V SoftsS = 4V there is no longer duty cycle limitation DC max which is controlled by comparator C7 since comparator C2 blocks the gate G7 (see Figure 6). This maximum charge current in the very first stage when V SoftS is below 1V, is limited to 1.32mA.
Figure 8Startup Phase
By means of this extra charge stage, there is no delay in the beginning of the Startup Phase when there is still no switching. Furthermore Soft Start is finished at 4V to have faster the maximum power capability. The duty cycles DC1 and DC2 are depending on the mains and the primary inductance of the transformer. The limitation of the primary current by DC2 is related to V SoftS = 4V. But DC1 is related to a maximum primary current which is limited by the internal Current Limiting with CS = 1V. Therefore the maximum Startup Phase is divided into a Soft Start Phase until t1 and a phase from t1 until t2 where maximum power is provided if demanded by the FB signal.
3.4PWM Section
Figure 9PWM Section
3.4.1Oscillator
The oscillator generates a fixed frequency. The switching frequency of ICE3Axx65x is f OSC = 100kHz and for ICE3Bxx65x f OSC = 67kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of D max=0.72. 3.4.2PWM-Latch FF1
The oscillator clock output provides a set pulse to the PWM-Latch when initiating the external Power Switch conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator or the Current-Limit comparator. In case of resetting, the driver is shut down immediately.3.4.3Gate Driver
Figure 10Gate Driver
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the internal CoolMOS? threshold. This is achieved by a slope control of the rising edge at the driver’s output (see Figure 10).
Figure 11Gate Rising Slope
Thus the leading switch on spike is minimized. When the integrated CoolMOS? is switched off, the falling shape of the driver is slowed down when reaching 2V to prevent an overshoot below ground. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During powerup when VCC is below the undervoltage lockout threshold V VCCoff, the output of the Gate Driver is low to disable power transfer to the seconding side.
3.5
Current Limiting
Figure 12
Current Limiting Block
There is a cycle by cycle Current Limiting realized by the Current-Limit comparator C10 to provide an overcurrent detection. The source current of the external Power Switch is sensed via an external sense resistor R Sense . By means of R Sense the source current is transformed to a sense voltage V Sense which is fed into the pin CS. If the voltage V Sense exceeds the internal threshold voltage V csth the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down without delay of the Power Switch in case of Current Limiting. The influence of the AC input voltage on the maximum output power can thereby be avoided.
To prevent the Current Limiting from distortions caused by leading edge spikes a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. Once activated the current limiting is thereby reduced to 0.257V. This voltage level determines the power level when the Active Burst Mode is left if there is a higher power demand.
Figure 13
Leading Edge Blanking
Each time when the external Power Switch is switched on, a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. This spike can cause the gate drive to switch off unintentionally. To avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of t LEB = 220ns. During this time, the gate drive will not be switched off.
3.5.2Propagation Delay Compensation
In case of overcurrent detection, the switch-off of the external Power Switch is delayed due to the propagation delay of the circuit. This delay causes an overshoot of the peak current I peak which depends on the ratio of dI/dt of the peak current (see Figure 13).
Figure 14
Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to limit the overshoot dependency on dI/dt of the rising primary current. That means the propagation delay time between exceeding the current sense threshold V csth and the switch off of the external Power Switch is compensated over temperature within a wide range.
Current Limiting is now possible in a very accurate way.
E.g. I peak = 0.5A with R Sense = 2. Without Propagation Delay Compensation the current sense threshold is set to a static voltage level V csth=1V. A current ramp of
dI/dt = 0.4A/μs, that means dV Sense/dt = 0.8V/μs, and a propagation delay time of i.e. t Propagation Delay =180ns leads then to an I peak overshoot of 12%. By means of propagation delay compensation the overshoot is only about 2% (see Figure 14).
Figure 15Overcurrent Shutdown
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage V csth (see Figure 15). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.
Figure 16Dynamic Voltage Threshold V csth 3.6Control Unit
The Control Unit contains the functions for Active Burst Mode and Auto Restart Mode. The Active Burst Mode and the Auto Restart Mode are combined with an Adjustable Blanking Window which is depending on the external Soft Start capacitor. By means of this Adjustable Blanking Window, the IC avoids entering into these two modes accidentally. Furthermore it also provides a certain time whereby the overload detection is delayed. This delay is useful for applications which normally works with a low current and occasionally require a short duration of high current.
3.6.1Adjustable Blanking Window
Figure 17Adjustable Blanking Window
V SoftS is clamped at 4.4V by the closed switch S1 after the SMPS is settled. If overload occurs V FB is exceeding 4.8V. Auto Restart Mode can’t be entered as the gate G5 is still blocked by the comparator C3. But after V FB has exceeded 4.8V the switch S1 is opened
via the gate G2. The external Soft Start capacitor can now be charged further by the integrated pull up resistor R SoftS. The comparator C3 releases the gates G5 and G6 once V Softs has exceeded 5.4V. Therefore there is no entering of Auto Restart Mode possible during this charging time of the external capacitor C SoftS. The same procedure happens to the external Soft Start capacitor if a low load condition is detected by comparator C5 when V FB is falling below 1.32V. Only after V SoftS has exceeded 5.4V and V FB is still below 1.32V Active Burst Mode is entered.
3.6.2Active Burst Mode
The controller provides Active Burst Mode for low load conditions at V OUT. Active Burst Mode increases significantly the efficiency at light load conditions while supporting a low ripple on V OUT and fast response on load jumps. During Active Burst Mode which is controlled only by the FB signal the IC is always active and can therefore immediately response on fast changes at the FB signal. The Startup Cell is kept switched off to avoid increased power losses for the self supply.
Figure 18Active Burst Mode The Active Burst Mode is located in the Control Unit. Figure 17 shows the related components.
3.6.2.1Entering Active Burst Mode
The FB signal is always observed by the comparator C5 if the voltage level falls below 1.32V. In that case the switch S1 is released which allows the capacitor C SoftS to be charged starting from the clamped voltage level at 4.4V in normal operating mode. If V SoftS exceeds 5.4V the comparator C3 releases the gate G6 to enter the Active Burst Mode. The time window that is generated by combining the FB and SoftS signals with gate G6 avoids a sudden entering of the Active Burst Mode due to large load jumps. This time window can be adjusted by the external capacitor C SoftS.
After entering Active Burst Mode a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC down to approx. 1.05mA. In this Off State Phase the IC is no longer self supplied so that therefore C VCC has to provide the VCC current (see Figure 18). Furthermore gate G11 is then released to start the next burst cycle once V FB has 3.4V exceeded.
It has to be ensured by the application that the VCC remains above the Undervoltage Lockout Level of 8.5V to avoid that the Startup Cell is accidentally switched on. Otherwise power losses are significantly increased. The minimum VCC level during Active Burst Mode is depending on the load conditions and the application. The lowest VCC level is reached at no load conditions at V OUT.
3.6.2.2Working in Active Burst Mode
After entering the Active Burst Mode the FB voltage rises as V OUT starts to decrease due to the inactive PWM section. Comparator C6a observes the FB signal if the voltage level 4V is exceeded. In that case the internal circuit is again activated by the internal Bias to start with switching. As now in Active Burst Mode the gate G10 is released the current limit is only 0.257V to reduce the conduction losses and to avoid audible noise. If the load at V OUT is still below the starting level for the Active Burst Mode the FB signal decreases down to 3.4V. At this level C6b deactivates again the internal circuit by switching off the internal Bias. The gate G11 is released as after entering Active Burst Mode the burst flag is set. If working in Active Burst Mode the FB voltage is changing like a saw tooth between 3.4V and 4V (see Figure 18).
3.6.2.3Leaving Active Burst Mode
The FB voltage immediately increases if there is a high load jump. This is observed by comparator C4. As the current limit is ca. 26% during Active Burst Mode a certain load jump is needed that FB can exceed 4.8V. At this time C4 resets the Active Burst Mode which also
blocks C12 by the gate G10. Maximum current can now be provided to stabilize V OUT.
Figure 19Signals in Active Burst Mode 3.6.3Protection Mode (Auto Restart Mode)
In order to increase the SMPS system’s robustness and safety, the IC provides the Auto Restart Mode as a protection feature. The Auto Restart Mode is entered upon detection of the following faults in the system:?VCC Overvoltage
?Overtemperature
?Overload
?Open Loop
?VCC Undervoltage
?Short Optocoupler
Figure 20Auto Restart Mode
The VCC voltage is observed by comparator C1 if 17V is exceeded. The output of C1 is combined with both the output of C11 which checks for SoftS<4.0V, and the output of C4 which checks for FB>4.8V. Therefore the overvoltage detection is can only active during Soft Start Phase(SoftS<4.0V) and when FB signal is outside the operating range > 4.8V. Therefore any small voltage overshoots of V VCC during normal operating cannot trigger the Auto Restart Mode.
In order to ensure system reliability and prevent any false activation, a blanking time is implemented before the IC can enter into the Auto Restart Mode. The output of the VCC overvoltage detection is fed into a spike blanking with a time constant of 8.0μs.
The other fault detection which can result in the Auto Restart Mode and has this 8.0μs blanking time is the Overtemperature detection. This block checks for a junction temperature of higher than 140°C for malfunction operation.
Once the Auto Restart Mode is entered, the internal Voltage Reference is switched off in order to reduce the current consumption of the IC as much as possible. In this mode, the average current consumption is only 300μA as the only working block is the Undervoltage Lockout(UVLO) which controls the Startup Cell by switching on/off at V VCCon/V VCCoff.
As there is no longer a self supply by the auxiliary winding, VCC starts to drop. The UVLO switches on the integrated Startup Cell when VCC falls below 8.5V. It will continue to charge VCC up to 15V whereby it is switched off again and the IC enters into the Start Up Phase.
As long as all fault conditions have been removed, the IC will automatically power up as usual with switching cycle at the GATE output after Soft Start duration. Thus the name Auto Restart Mode.
Other fault detections which are active in normal operation is the sensing for Overload, Open Loop and VCC undervoltage conditions. In the first 2 cases, FB will rise above 4.8V which will be observed by C4. At this time, S1 is released such that V SoftS can rise from its earlier clamp voltage of 4.4V. If V SoftS exceeds 5.4V which is observed by C3, Auto Restart Mode is entered as both inputs of the gate G5 are high.
This charging of the Soft Start capacitor from 4.4V to 5.4V defines a blanking window which prevents the system from entering into Auto Restart Mode un-intentionally during large load jumps. In this event, FB will rise close to 6.5V for a short duration before the loop regulates with FB less than 4.8V. This is the same blanking time window as for the Active Burst Mode and can therefore be adjusted by the external C SoftS.
In the case of VCC undervoltage, ie. VCC falls below 8.5V, the IC will be turn off with the Startup Cell charging VCC as described earlier in this section. Once VCC is charged above 15V, the IC will start a new startup cycle. The same procedure applies when the system is under Short Optocoupler fault condition, as it will lead to VCC undervoltage.
Electrical Characteristics 4Electrical Characteristics
Note:All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1Absolute Maximum Ratings
Note:Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (V CC) is discharged before assembling the application circuit.
Parameter Symbol Limit Values Unit Remarks
min.max.
Drain Source Voltage
ICE3Axx65/xx65I/xx65P
ICE3Bxx65/xx65I/xx65P
V DS-650V T j=110°C
Avalanche energy, repetitive t AR limited by max. T j=150°C1)ICE3x0365E AR1-0.005mJ
ICE3x0565
ICE3A0565Z
E AR2-0.01mJ ICE3x1065E AR3-0.07mJ ICE3x1565E AR4-0.15mJ
ICE3x2065
ICE3A2065Z
E AR5-0.40mJ ICE3x2565E AR6-0.47mJ
ICE3x2065I
ICE3x2065P
E AR7-0.07mJ
ICE3x3065I
ICE3x3065P
E AR8-0.11mJ
ICE3x3565I
ICE3x3565P
E AR9-0.17mJ
ICE3x5065I
ICE3x5065P
E AR10-0.40mJ
ICE3x5565I
ICE3x5565P
E AR11-0.44mJ
CoolSET?-F3
Electrical Characteristics
Avalanche current, repetitive t AR limited by max. T j =150°C
ICE3x0365I AR1-0.3A ICE3x0565ICE3A0565Z
I AR2-0.5A ICE3x1065I AR3- 1.0A ICE3x1565
I AR4
- 1.5A ICE3x2065ICE3A2065Z I AR5- 2.0A ICE3x2565I AR6- 2.5A ICE3x2065I ICE3x2065P I AR7- 2.0A ICE3x3065I ICE3x3065P I AR8- 3.0A ICE3x3565I ICE3x3565P I AR9- 3.5A ICE3x5065I ICE3x5065P I AR10- 5.0A ICE3x5565I ICE3x5565P
I AR11
- 5.5
A
1)
Repetitive avalanche causes additional power losses that can be calculated as P AV =E AR *f
Parameter
Symbol
Limit Values Unit
Remarks
min.
max.