fpga+1602+vhdl
--ADC0804直流采样和显示
--输入电压范围0-5V，显示0-255数位
--**************库定义、包定义********************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--******************实体定义***********************
entity adc0804_new is
port(
reset : in std_logic;--复位输入
clk : in std_logic;--主时钟输入
intr : in std_logic;--AD转换结束输入
data_i : in std_logic_vector(7 downto 0);--数据输入
data_o : out std_logic_vector(7 downto 0);--数码管数据输出
l : out STD_LOGIC_VECTOR(5 downto 0);--输出数码管位选
bell : out std_logic;--蜂鸣器
cs : out std_logic;--使能
wr : out std_logic;--写控制
rd : out std_logic--读控制
);
end adc0804_new;
--******************结构体***********************
architecture Behavioral of adc0804_new is
type state is (start, convert, read1, read2);--状态机定义
signal current_state, next_state : state;--状态定义
signal read_data : std_logic;--读数据寄存器
signal clock : std_logic;--扫描时钟
signal p : integer range 0 to 255;--数据寄存器
signal b0,b1,b2 : integer range 0 to 9;--3位数码管显示数据寄存器
signal cnt : integer range 0 to 3:=0;--扫描寄存器
begin
bell<='0';
--********************显示进程**********************************
process(p,clk)
begin
case p is
when
0|10|20|30|40|50|60|70|80|90|100|110|120|130|140|150|160|170|180|190|200|210|220|230|240|250= >b0<=0;
when
1|11|21|31|41|51|61|71|81|91|101|111|121|131|141|151|161|171|181|191|201|211|221|231|241|251=> b0<=1;
when
2|12|22|32|42|52|62|72|82|92|102|112|122|132|142|152|162|172|182|192|202|212|222|232|242|252= >b0<=2;
when
3|13|23|33|43|53|63|73|83|93|103|113|123|133|143|153|163|173|183|193|203|213|223|233|243|253= >b0<=3;
when
4|14|24|34|44|54|64|74|84|94|104|114|124|134|144|154|164|174|184|194|204|214|224|234|244|254= >b0<=4;
when
5|15|25|35|45|55|65|75|85|95|105|115|125|135|145|155|165|175|185|195|205|215|225|235|245|255= >b0<=5;
when
6|16|26|36|46|56|66|76|86|96|106|116|126|136|146|156|166|176|186|196|206|216|226|236|246=>b0< =6;
when
7|17|27|37|47|57|67|77|87|97|107|117|127|137|147|157|167|177|187|197|207|217|227|237|247=>b0< =7;
when
8|18|28|38|48|58|68|78|88|98|108|118|128|138|148|158|168|178|188|198|208|218|228|238|248=>b0< =8;
when
9|19|29|39|49|59|69|79|89|99|109|119|129|139|149|159|169|179|189|199|209|219|229|239|249=>b0< =9;
when others=>--b0<=10;
end case;
case p is
when
0|1|2|3|4|5|6|7|8|9|100|101|102|103|104|105|106|107|108|109|200|201|202|203|204|205|206|207|208| 209=>b1<=0;
when
10|11|12|13|14|15|16|17|18|19|110|111|112|113|114|115|116|117|118|119|210|211|212|213|214|215|2 16|217|218|219=>b1<=1;
when
20|21|22|23|24|25|26|27|28|29|120|121|122|123|124|125|126|127|128|129|220|221|222|223|224|225| 226|227|228|229=>b1<=2;
when
30|31|32|33|34|35|36|37|38|39|130|131|132|133|134|135|136|137|138|139|230|231|232|233|234|235| 236|237|238|239=>b1<=3;
when
40|41|42|43|44|45|46|47|48|49|140|141|142|143|144|145|146|147|148|149|240|241|242|243|244|245| 246|247|248|249=>b1<=4;
when
50|51|52|53|54|55|56|57|58|59|150|151|152|153|154|155|156|157|158|159|250|251|252|253|254|255 =>b1<=5;
when
60|61|62|63|64|65|66|67|68|69|160|161|162|163|164|165|166|167|168|169=>b1<=6;
when
70|71|72|73|74|75|76|77|78|79|170|171|172|173|174|175|176|177|178|179=>b1<=7;
when
80|81|82|83|84|85|86|87|88|89|180|181|182|183|184|185|186|187|188|189=>b1<=8;
when
90|91|92|93|94|95|96|97|98|99|190|191|192|193|194|195|196|197|198|199=>b1<=9;
when others=>--b0<=10;
end case;
if p<100 then
b2<=0;
elsif p>=100 and p<200 then
b2<=1;
elsif p>=200 then
b2<=2;
end if;
end process;
--**********************分频进程*************************
process(clk)
variable cnt1 : integer range 0 to 100;
variable cnt2 : integer range 0 to 20;
begin
if clk'event and clk='1' then
if cnt1=100 then
cnt1:=0;
if cnt2=20 then
cnt2:=0;
clock<=not clock;
if(cnt=3)then
cnt<=0;
else
cnt<=cnt+1;
end if;
else
cnt2:=cnt2+1;
end if;
else
cnt1:=cnt1+1;
end if;
end if;
end process;
--**************状态驱动进程********************** sync :process(clock,reset)
begin
if(reset = '0') then
current_state <= start;
elsif(clock'event and clock='1') then
current_state <= next_state;
end if;
end process sync;
--***************adc0804驱动进程******************* comb :process(current_state, intr)
begin
case current_state is
when start => --启动状态
next_state <= convert;
cs <= '0';
wr <= '0';
rd <= '1';
read_data <= '0';
when convert =>--初始化
if(intr = '0') then
next_state <= read1;
else
next_state <= convert;
end if;
cs <= '1';
wr <= '1';
rd <= '1';
read_data <= '0';
when read1 =>--读状态1
next_state <= read2;
cs <= '0';
wr <= '1';
rd <= '0';
read_data <= '1';
when read2 =>--读状态2
next_state <= start;
cs <= '1';
wr <= '1';
rd <= '1';
read_data <= '0';
when others =>--其他状态
next_state <= start;
end case;
end process comb;
--****************读取AD数据********************
get_data: process(clock,reset)
begin
if(reset = '0') then
p<=0;
elsif(clock'event and clock='1') then
if(read_data = '1') then
p<=conv_integer(data_i);
end if;
end if;
end process;
--********************显示进程***************************************
process(cnt)
FUNCTION b_to_s7(bcd8421:INTEGER RANGE 0 TO 9) RETURN STD_LOGIC_VECTOR IS
V ARIABLE smg7: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CASE bcd8421 IS --计算输出值
WHEN 0 => smg7:="11111100"; --abcdefgh
WHEN 1 => smg7:="01100000";
WHEN 2 => smg7:="11011010";
WHEN 3 => smg7:="11110010";
WHEN 4 => smg7:="01100110";
WHEN 5 => smg7:="10110110";
WHEN 6 => smg7:="10111110";
WHEN 7 => smg7:="11100000";
WHEN 8 => smg7:="11111110";
WHEN 9 => smg7:="11110110";
WHEN OTHERS=>smg7:="10001110";
END CASE;
RETURN smg7;
END b_to_s7;
begin
case cnt is
when 0 => l<="111110";data_o<=b_to_s7(b0);
when 1 => l<="111101";data_o<=b_to_s7(b1);
when 2 => l<="111011";data_o<=b_to_s7(b2);
when others=>l<="111111";--data_o<=b_to_s7(8);
end case;
end process;
end Behavioral;