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7C420-15中文资料

256/512/1K/2K/4K x 9 Asynchronous FIFO

CY7C419/21/25/29/33

Features

?Asynchronous first-in first-out (FIFO) buffer memories ?256 x 9 (CY7C419)

?512 x 9 (CY7C421)

?1K x 9 (CY7C425)

?2K x 9 (CY7C429)

?4K x 9 (CY7C433)

?Dual-ported RAM cell

?High-speed 50.0-MHz read/write independent of

depth/width

?Low operating power: I CC = 35 mA

?Empty and Full flags (Half Full flag in standalone)?TTL compatible

?Retransmit in standalone

?Expandable in width

?PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP

?Pin compatible and functionally equivalent to IDT7200, IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204

Functional Description

The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories offered in 600-mil wide and 300-mil wide packages. They are, respec-tively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide.Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three ad-ditional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel, thus eliminating the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50.0 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high-impedance state when R is HIGH.

A Half Full (HF) output flag is provided that is valid in the stan-dalone and width expansion configurations. In the depth ex-pansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated.

In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. In-put ESD protection is greater than 2000V and latch-up is pre-vented by careful layout and guard rings.

Maximum Rating

[1]

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature .................................–65°C to +150°C Ambient Temperature with

Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State................................................–0.5V to +7.0V DC Input Voltage............................................–0.5V to +7.0V Power Dissipation..........................................................1.0W Output Current, into Outputs (LOW)............................20 mA Static Discharge Voltage...........................................>2000V (per MIL –STD –883, Method 3015)

Latch-Up Current.....................................................>200 mA

Note:

1.Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up.

RAM ARRAY 256x 9512x 91024x 92048x 94096x 9

Logic Block Diagram

Pin Configurations

4567891011121516

17181920242322211314

25282726Top View

DIP 7C420/1W

D 8D 3D 2D 1D 0XI FF Q 0Q 1Q 2GND

V cc

D 4FL/RT MR EF XO/HF Q 7R PLCC/LCC Top View

Q 3Q 8D 5D 6D 7Q 6Q 5Q 44321323130

14151617181920

56789101112132928272625

232221

FL/RT MR EF XO/HF Q 7D 6Q 6D 7NC READ CONTROL

WRITE CONTROL

WRITE POINTER

RESET LOGIC

EXPANSION LOGIC

DATA INPUTS (D 0–D 8)

THREE-STATE BUFFERS

DATA OUTPUTS

(Q 0–Q 8)

READ POINTER

FLAG LOGIC

EF FF

XO/HF

MR FL/RT

D 2D 1D 0XI FF Q 0Q 1NC Q 2D D W N C V D D 3

c c

5Q Q G N D N C R Q Q 3

C420–1

C420–2

C420–3

7C4197C421/5/97C4337C424/57C428/97C432/37C4192612345678

2423222120191817

910111213141532313029282725

Q 1

XI Q 0D 1D 0NC NC FF D 6

D 5

D 4V C C

W D 8

D 3

D 2

D 7FL/RT NC NC MR EF XO/HF Q 7

C420–4

Top View

TQFP Q 2

Q 3

Q 8

G N D R Q 4

Q 5

Q 6

7C4197C421/5/97C433

Selection Guide

256 x 9

7C419–107C419–15

7C419–307C419–40512 x 9 (600-mil only)7C420–20

7C420–257C420–407C420–65512 x 9

7C421–107C421–157C421–207C421–257C421–307C421–407C421–651K x 9 (600-mil only)7C424–207C424–257C424–307C424–407C424–651K x 9

7C425–107C425–157C425–207C425–25

7C425–307C425–407C425–652K x 9 (600-mil only)7C428–207C428–652K x 9

7C429–10

7C429–157C429–207C429–257C429–307C429–407C429–65

4K x 9 (600-mil only)7C432–257C432–404K x 9

7C433–10

7C433–15

7C433–207C433–257C433–30

7C433–40

7C433–65Frequency (MHz)

504033.328.5252012.5Maximum Access Time (ns)10152025304065I CC1 (mA)

3535

Operating Range

Range Ambient Temperature[2]V CC

Commercial0°C to + 70°C 5V ± 10%

Industrial–40°C to +85°C5V ± 10%

Military–55°C to +125°C 5V ± 10%

Electrical Characteristics Over the Operating Range[3]

7C419–10, 15, 30, 40

7C420/1–10, 15, 20, 25, 30, 40, 65

7C424/5–10, 15, 20, 25, 30, 40, 65

7C428/9–10, 15, 20, 25, 30, 40, 65

7C432/3–10, 15, 20, 25, 30, 40, 65 Parameter Description Test Conditions Min.Max.Unit V OH Output HIGH Voltage V CC = Min., I OH = –2.0 mA 2.4V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA0.4V V IH Input HIGH Voltage Com’l 2.0V CC V

Mil/Ind 2.2V CC

V IL Input LOW Voltage Note 40.8V I IX Input Leakage Current GND < V I < V CC–10+10μA I OZ Output Leakage Current R > V IH, GND < V O < V CC–10+10μA I OS Output Short Circuit Current[5]V CC = Max., V OUT = GND–90mA

Electrical Characteristics Over the Operating Range[3](continued)

7C419–10 7C421–10 7C425–10 7C429–10 7C433–107C419–15

7C421–15

7C425–15

7C429–15

7C433–15

7C420–20

7C421–20

7C424–20

7C425–20

7C428–20

7C429–20

7C433–20

7C420–25

7C421–25

7C424–25

7C425–25

7C429–25

7C432–25

7C433–25

Parameter Description Test Conditions Min.Max.Min.Max.Min.Max.Min.Max.Unit

I CC Operating Current V CC = Max.,

I OUT = 0 mA

f = f MAX Com’l85655550mA Mil/Ind1009080

I CC1Operating Current V CC = Max.,

I OUT = 0 mA

F = 20 MHz

Com’l35353535mA

I SB1Standby Current All Inputs =

V IH https://www.wendangku.net/doc/6616090786.html,’l10101010mA Mil/Ind151515

I SB2Power-Down Current All Inputs >

V CC–0.2V Com’l5555mA Mil/Ind888

Notes:

2.T A is the “instant on” case temperature.

3.See the last page of this specification for Group A subgroup testing information.

4.V IL (Min.) = –2.0V for pulse durations of less than 20 ns.

5.For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.

Electrical Characteristics Over the Operating Range [3] (continued)

7C419–307C421–307C424–307C425–307C429–307C433–30

7C419–407C420–407C421–407C424–407C425–407C429–407C432–407C433–407C420–657C421–657C424–657C425–657C428–657C429–657C433–65Parameter Description Test Conditions Min.

Max.Min.

Max.Units I CC

Operating Current

V CC = Max.,I OUT = 0 mA f = f MAX Com ’l 403535mA

Mil/Ind 757065I CC1

Operating Current

V CC = Max.,I OUT = 0 mA F = 20 MHz Com ’l

mA I SB1Standby Current All Inputs = V IH https://www.wendangku.net/doc/6616090786.html, ’l 101010mA Mil 151515I SB2

Power-Down Current

All Inputs > V CC –0.2V

Com ’l 555mA

Mil

Capacitance [6]

Parameter

Description

Test Conditions

Max.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz,V CC = 4.5V

6pF C OUT

Output Capacitance

Note:

6.Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

3.0V

5V OUTPUT

R1 500?

R2333?

30pF INCLUDING JIGAND SCOPE

GND

90%10%

≤3ns ≤3ns

5V OUTPUT

R1 500?

R2333?

5pF

INCLUDING JIGAND SCOPE

OUTPUT 2V

Equivalent to:

TH é V ENIN EQUIVALENT

(b)

C420–6

C420–7

C420–8

(a)ALL INPUT PULSES 200?

Switching Characteristics Over the Operating Range[7, 8]

7C419–10 7C421–10 7C425–10 7C429–10 7C433–107C419–15

7C421–15

7C425–15

7C429–15

7C433–15

7C420–20

7C421–20

7C424–20

7C425–20

7C428–20

7C429–20

7C433–20

7C420–25

7C421–25

7C424–25

7C425–25

7C429–25

7C432–25

7C433–25

Parameter Description Min.Max.Min.Max.Min.Max.Min.Max.Unit t RC Read Cycle Time20253035ns t A Access Time10152025ns t RR Read Recovery Time10101010ns t PR Read Pulse Width10152025ns t LZR[6,9]Read LOW to Low Z3333ns t DVR[9,10]Data Valid After Read HIGH5555ns t HZR[6,9,10]Read HIGH to High Z15151518ns t WC Write Cycle Time20253035ns t PW Write Pulse Width10152025ns t HWZ[6,9]Write HIGH to Low Z5555ns t WR Write Recovery Time10101010ns t SD Data Set-Up Time681215ns t HD Data Hold Time0000ns t MRSC MR Cycle Time20253035ns t PMR MR Pulse Width10152025ns t RMR MR Recovery Time10101010ns t RPW Read HIGH to MR HIGH10152025ns t WPW Write HIGH to MR HIGH10152025ns t RTC Retransmit Cycle Time20253035ns t PRT Retransmit Pulse Width10152025ns t RTR Retransmit Recovery Time10101010ns Notes:

7.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified I OL/I OH and 30 pF load

capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.

8.See the last page of this specification for Group A subgroup testing information.

9.t HZR transition is measured at +200 mV from V OL and –200 mV from V OH. t DVR transition is measured at the 1.5V level. t HWZ and t LZR transition is measured

at ±100 mV from the steady state.

10.t HZR and t DVR use capacitance loading as in part (b) of AC Test Load and Waveforms.

t EFL MR to EF LOW 20253035ns t HFH MR to HF HIGH 20253035ns t FFH MR to FF HIGH 20253035ns t REF Read LOW to EF LOW 10152025ns t RFF Read HIGH to FF HIGH 10152025ns t WEF Write HIGH to EF HIGH 10152025ns t WFF Write LOW to FF LOW 10152025ns t WHF Write LOW to HF LOW 10152025ns t RHF Read HIGH to HF HIGH 10152025ns t RAE Effective Read from Write HIGH

ns t RPE Effective Read Pulse Width After EF HIGH 10

ns t WAF Effective Write from Read HIGH

ns t WPF Effective Write Pulse Width After FF HIGH 10

ns t XOL Expansion Out LOW Delay from Clock 10152025ns t XOH

Expansion Out HIGH Delay from Clock

Switching Characteristics Over the Operating Range [7, 8] (continued)

7C419–107C421–107C425–107C429–107C433–10

7C419–157C421–157C425–157C429–157C433–157C420–207C421–207C424–207C425–207C428–207C429–207C433–207C420–257C421–257C424–257C425–257C429–257C432–257C433–25Parameter Description

Min.

Max.Min.

Max.Unit

Switching Characteristics Over the Operating Range[7, 8] (continued)

7C419–30

7C421–30 7C424–30 7C425–30

7C429–30

7C433–307C419–40

7C420–40

7C421–40

7C424–40

7C425–40

7C429–40

7C432–40

7C433–40

7C420–65

7C421–65

7C424–65

7C425–65

7C428–65

7C429–65

7C433–65

Parameter Description Min.Max.Min.Max.Min.Max.Unit t RC Read Cycle Time405080ns t A Access Time304065ns t RR Read Recovery Time101015ns t PR Read Pulse Width304065ns t LZR[6,9]Read LOW to Low Z333ns t DVR[9,10]Data Valid After Read HIGH555ns t HZR[6,9,10]Read HIGH to High Z202020ns t WC Write Cycle Time405080ns t PW Write Pulse Width304065ns t HWZ[6,9]Write HIGH to Low Z555ns t WR Write Recovery Time101015ns t SD Data Set-Up Time182030ns t HD Data Hold Time000ns t MRSC MR Cycle Time405080ns t PMR MR Pulse Width304065ns t RMR MR Recovery Time101015ns t RPW Read HIGH to MR HIGH304065ns t WPW Write HIGH to MR HIGH304065ns t RTC Retransmit Cycle Time405080ns t PRT Retransmit Pulse Width304065ns t RTR Retransmit Recovery Time101015ns t EFL MR to EF LOW405080ns t HFH MR to HF HIGH405080ns t FFH MR to FF HIGH405080ns t REF Read LOW to EF LOW303560ns t RFF Read HIGH to FF HIGH303560ns t WEF Write HIGH to EF HIGH303560ns t WFF Write LOW to FF LOW303560ns t WHF Write LOW to HF LOW303560ns t RHF Read HIGH to HF HIGH303560ns t RAE Effective Read from Write HIGH303560ns t RPE Effective Read Pulse Width After EF HIGH304065ns t WAF Effective Write from Read HIGH303560ns t WPF Effective Write Pulse Width After FF HIGH304065ns t XOL Expansion Out LOW Delay from Clock304065ns t XOH Expansion Out HIGH Delay from Clock304065ns

Switching Waveforms

Notes:

11.W and R ≥ V IH around the rising edge of MR.12.t MRSC = t PMR + t RMR .

DATA VALID

DATA VALID DATA VALID

Asynchronous Read and Write

t SD

t HD

t RC

t PR t A t RR

t A

t LZR

t DVR

t HZR

t WC

t PW

t WR

Q 0–Q 8

D 0–D 8

Master Reset

MR R,W

t MRSC

t PMR

t EFL

t HFH

t FFH

t RPW t WPW

t RMR

HALF FULL+1

HALF FULL

t WHF

t RHF

Half-Full Flag

C420–9

C420–10

C420–11

[11]

[12]

Notes:

13.EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at t RTC .14.t RTC = t PRT + t RTR .

Switching Waveforms (continued)

Last Write to First Read Full Flag

Last Read to First Write Empty Flag

C420–12

C420–13

C420–14

LAST WRITE FIRST READ ADDITIONAL READS

FIRST WRITE

VALID

LAST READ

FIRST WRITE

ADDITIONAL WRITES

FIRST READ

VALID

t REF

t WEF

t RTC t PRT

t RTR

t WFF

t RFF

t A

DATA OUT

FL/RT

R,W

Retransmit [13]

[14]

Switching Waveforms (continued)

Empty Flag and Read Data Flow-Through Mode

Full Flag and Write Data Flow-Through Mode

C420–15

C420–16

DATA IN

DATA OUT

DATA IN

DATA OUT

DATA VALID

t RAE

t REF

t WEF

t HWZ

t A

t WAF

t WPF

t WFF t RFF

t SD

t HD

t A

t RPE

Architecture

The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,4096 words of 9 bits each (implemented by an array of du-al-port RAM cells), a read pointer, a write pointer, control sig-nals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags.

Dual-Port RAM

The dual-port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is neces-sary to achieve truly asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment

the read and write pointers is much less than the time that would be required for data propagation through the memory,which would be the case if the memory were implemented using the conventional register array architecture.Resetting the FIFO

Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W) must be HIGH t RPW /t WPW before and t RMR after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state.

Note:

15.Expansion Out of device 1 (XO 1) is connected to Expansion In of device 2 (XI 2).

Switching Waveforms (continued)

Expansion Timing Diagrams

C420–17

XO 1(XI 2)

D 0–D 8

DATA VALID DATA DATA VALID

VALID

t XOL t XOH

t HD

t SD

t HD

t XOL t LZR

t A

t DVR t XOH

t A

t DVR t HZR

XO 1(XI 2)

Q 0–Q 8

WRITE TO LAST PHYSICAL LOCATION OF DEVICE 1

WRITE TO FIRST PHYSICAL LOCATION OF DEVICE 2

READ FROM LAST PHYSICAL LOCATION OF DEVICE 1

READ FROM FIRST PHYSICAL LOCATION OF DEVICE 2

C420–18

t WR

t RR

DATA VALID

[15]

Writing Data to the FIFO

The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (D0–D8) t SD before and t HD after the rising edge of W will be stored sequentially in the FIFO.

The EF LOW-to-HIGH transition occurs t WEF after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW t WHF after the falling edge of W following the FIFO actu-ally being Half Full. Therefore, the HF is active once the FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs t RHF after the rising edge of R when the FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. FF goes LOW t WFF

which the last available location is filled. Internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and a read from a full FIFO.

Reading Data from the FIFO

Data outputs (Q0–Q8) are in a high-impedance condition be-tween read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode.

When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. The rising edge of R causes the data outputs to go to the high-impedance state and remain such until a write is performed. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read t WEF after a valid write.

The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary.

The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and t RTR after retransmit is LOW. With every read cycle after retransmit, pre-viously accessed data as well as not previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also.

Up to the full depth of the FIFO can be repeatedly retransmit-ted.

Standalone/Width Expansion Modes

Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to V CC. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored.

Depth Expansion Mode (see Figure 1)

Depth expansion mode is entered when, during a MR cycle, Expansion Out (XO) of one device is connected to Expansion In (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and pulsed LOW again when the last physical location is read. Only one FIFO is enabled for read and one for write at any given time. All other devices are in standby.

FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created of word widths in increments of 9. When expanding in depth, a composite FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EFs togeth-mode.

Use of the Empty and Full Flags

In order to achieve the maximum frequency, the flags must be valid at the beginning of the next cycle. However, because they can be updated by either edge of the read of write signal, they must be valid by one-half of a cycle. Cypress FIFOs meet this requirement; some competitors’ FIFOs do not.

The reason why the flags are required to be valid by the next cycle is fairly complex. It has to do with the “effective pulse width violation” phenomenon, which can occur at the full and empty boundary conditions, if the flags are not properly used. The empty flag must be used to prevent reading from an empty FIFO and the full flag must be used to prevent writing into a full FIFO.

For example, consider an empty FIFO that is receiving read pulses. Because the FIFO is empty, the read pulses are ig-nored by the FIFO, and nothing happens. Next, a single word is written into the FIFO, with a signal that is asynchronous to the read signal. The (internal) state machine in the FIFO goes from empty to empty+1. However, it does this asynchronously with respect to the read signal, so that it cannot be determined what the effective pulse width of the read signal is, because the state machine does not look at the read signal until it goes to the empty+1 state. In a similar manner, the minimum write pulse width may be violated by attempting to write into a full FIFO, and asynchronously performing a read. The empty and full flags are used to avoid these effective pulse width viola-tions, but in order to do this and operate at the maximum fre-quency, the flag must be valid at the beginning of the next cycle.

Figure 1.Depth Expansion

CY7C419CY7C420/1CY7C424/5CY7C428/9CY7C432/3

FF XI

EMPTY

FULL

V CC

*FIRSTDEVICE

C420–19

CY7C419CY7C420/1CY7C424/5CY7C428/9CY7C432/3

Ordering Information

Speed

(ns)Ordering Code Package

Type Package Type

Operating

Range

10CY7C419–10AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C419–10JC J6532-Lead Plastic Leaded Chip Carrier

CY7C419–10PC P2128-Lead (300-Mil) Molded DIP

CY7C419–10VC V2128-Lead (300-Mil) Molded SOJ

15CY7C419–15AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C419–15JC J6532-Lead Plastic Leaded Chip Carrier

CY7C419–15VC V2128-Lead (300-Mil) Molded SOJ

CY7C419–15JI J6532-Lead Plastic Leaded Chip Carrier Industrial 30CY7C419–30JC J6532-Lead Plastic Leaded Chip Carrier Commercial 40CY7C419–40AC A3232-Pin Thin Plastic Quad Flatpack

CY7C419–40JC J6532-Lead Plastic Leaded Chip Carrier

Ordering Information (continued)

Speed

(ns)Ordering Code Package

Type Package Type

Operating

Range

25CY7C420–25PC P1528-Lead (600-Mil) Molded DIP Commercial 40CY7C420–40PC P1528-Lead (600-Mil) Molded DIP

65CY7C420–65PC P1528-Lead (600-Mil) Molded DIP

Ordering Information (continued)

Speed

(ns)Ordering Code Package

Type Package Type

Operating

Range

10CY7C421–10AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C421–10JC J6532-Lead Plastic Leaded Chip Carrier

CY7C421–10PC P2128-Lead (300-Mil) Molded DIP

CY7C421–10VC V2128-Lead (300-Mil) Molded SOJ

15CY7C421–15AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C421–15JC J6532-Lead Plastic Leaded Chip Carrier

CY7C421–15JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C421–15VI V2128-Lead (300-Mil) Molded SOJ

CY7C421–15DMB D2228-Lead (300-Mil) CerDIP Military

CY7C421–15LMB L5532-Pin Rectangular Leadless Chip Carrier

20CY7C421–20JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C421–20PC P2128-Lead (300-Mil) Molded DIP

CY7C421–20VC V2128-Lead (300-Mil) Molded SOJ

CY7C421–20JI J6532-Lead Plastic Leaded Chip Carrier Industrial 25CY7C421–25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C421–25PC P2128-Lead (300-Mil) Molded DIP

CY7C421–25VC V2128-Lead (300-Mil) Molded SOJ

CY7C421–25JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C421–25PI P2128-Lead (300-Mil) Molded DIP

CY7C421–25DMB D2228-Lead (300-Mil) CerDIP Military

30CY7C421–30JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C421–30PC P2128-Lead (300-Mil) Molded DIP

CY7C421–30JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C421–30DMB D2228-Lead (300-Mil) CerDIP

Military

CY7C421–30LMB

L5532-Pin Rectangular Leadless Chip Carrier 40

CY7C421–40JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C421–40PC P2128-Lead (300-Mil) Molded DIP CY7C421–40VC V2128-Lead (300-Mil) Molded SOJ CY7C421–40JI

J6532-Lead Plastic Leaded Chip Carrier Industrial 65

CY7C421–65JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C421–65PC P2128-Lead (300-Mil) Molded DIP CY7C421–65VC V2128-Lead (300-Mil) Molded SOJ CY7C421–65JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C421–65DMB

D22

28-Lead (300-Mil) CerDIP

Military Ordering Information (continued)

Speed (ns)Ordering Code Package Type Package Type

Operating Range Ordering Information (continued)

Speed (ns)Ordering Code Package Type Package Type

Operating Range 40CY7C424–40PC P1528-Lead (600-Mil) Molded DIP Commercial 65

CY7C424–65PC

P15

28-Lead (600-Mil) Molded DIP

Commercial

Ordering Information (continued)

Speed (ns)Ordering Code Package Type Package Type

Operating Range 10

CY7C425–10AC A3232-Pin Thin Plastic Quad Flatpack Commercial

CY7C425–10JC J6532-Lead Plastic Leaded Chip Carrier CY7C425–10PC P2128-Lead (300-Mil) Molded DIP CY7C425–10VC

V2128-Lead (300-Mil) Molded SOJ 15

CY7C425–15JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C425–15PC P2128-Lead (300-Mil) Molded DIP CY7C425–15DMB D2228-Lead (300-Mil) CerDIP

Military CY7C425–15LMB

L5532-Pin Rectangular Leadless Chip Carrier 20

CY7C425–20JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C425–20PC P2128-Lead (300-Mil) Molded DIP CY7C425–20VC

V2128-Lead (300-Mil) Molded SOJ 25

CY7C425–25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C425–25PC P2128-Lead (300-Mil) Molded DIP CY7C425–25JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C425–25VI V2128-Lead (300-Mil) Molded SOJ CY7C425–25DMB D2228-Lead (300-Mil) CerDIP

Military CY7C425–25LMB

L5532-Pin Rectangular Leadless Chip Carrier 30

CY7C425–30JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C425–30PC P2128-Lead (300-Mil) Molded DIP CY7C425–30VC V2128-Lead (300-Mil) Molded SOJ CY7C425–30VI

V21

28-Lead (300-Mil) Molded SOJ

Industrial

CY7C425–40JC J6532-Lead Plastic Leaded Chip Carrier Commercial

CY7C425–40PC P2128-Lead (300-Mil) Molded DIP CY7C425–40VC V2128-Lead (300-Mil) Molded SOJ CY7C425–40JI

J6532-Lead Plastic Leaded Chip Carrier Industrial 65

CY7C425–65JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C425–65PC

P21

28-Lead (300-Mil) Molded DIP

Ordering Information (continued)

Speed (ns)Ordering Code Package Type Package Type

Operating Range Ordering Information (continued)

Speed (ns)Ordering Code Package Type Package Type

Operating Range 20CY7C428–20PC P1528-Lead (600-Mil) Molded DIP Commercial 25CY7C428–25DMB D1628-Lead (600-Mil) CerDIP Military 65

CY7C428–65PC

P15

28-Lead (600-Mil) Molded DIP

Commercial

Ordering Information (continued)

Speed (ns)Ordering Code Package Type Package Type

Operating Range 10

CY7C429–10AC A3232-Pin Thin Plastic Quad Flatpack Commercial

CY7C429–10JC J6532-Lead Plastic Leaded Chip Carrier CY7C429–10PC

P2128-Lead (300-Mil) Molded DIP 15

CY7C429–15JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C429–15JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C429–15DMB D2228-Lead (300-Mil) CerDIP

Military CY7C429–15LMB

L5532-Pin Rectangular Leadless Chip Carrier 20

CY7C429–20JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C429–20PC P2128-Lead (300-Mil) Molded DIP CY7C429–20VC V2128-Lead (300-Mil) Molded SOJ CY7C429–20DMB

D2228-Lead (300-Mil) CerDIP

Military 25

CY7C429–25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C429–25PC P2128-Lead (300-Mil) Molded DIP CY7C429–25VC V2128-Lead (300-Mil) Molded SOJ CY7C429–25JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C429–25DMB D2228-Lead (300-Mil) CerDIP

Military CY7C429–25LMB

L5532-Pin Rectangular Leadless Chip Carrier 30

CY7C429–30JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C429–30PC P2128-Lead (300-Mil) Molded DIP CY7C429–30VC V2128-Lead (300-Mil) Molded SOJ CY7C429–30DMB

D2228-Lead (300-Mil) CerDIP Military 40

CY7C429–40AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C429–40JC J6532-Lead Plastic Leaded Chip Carrier CY7C429–40PC

P2128-Lead (300-Mil) Molded DIP 65

CY7C429–65JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C429–65PC P2128-Lead (300-Mil) Molded DIP CY7C429–65JI

J65

32-Lead Plastic Leaded Chip Carrier

Industrial

Ordering Information (continued)

Speed

(ns)Ordering Code Package

Name Package Type

Operating

Range

25CY7C432–25PC P1528-Lead (600-Mil) Molded DIP Commercial 40CY7C432–40PC P1528-Lead (600-Mil) Molded DIP Commercial

Ordering Information (continued)

Speed

(ns)Ordering Code Package

Name Package Type

Operating

Range

10CY7C433–10AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C433–10JC J6532-Lead Plastic Leaded Chip Carrier

CY7C433–10PC P2128-Lead (300-Mil) Molded DIP

CY7C433–10VC V2128-Lead (300-Mil) Molded SOJ

15CY7C433–15AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C433–15JC J6532-Lead Plastic Leaded Chip Carrier

CY7C433–15JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C433–15PI P2128-Lead (300-Mil) Molded DIP

CY7C433–15DMB D2228-Lead (300-Mil) CerDIP Military

CY7C433–15LMB L5532-Pin Rectangular Leadless Chip Carrier

20CY7C433–20AC A3232-Pin Thin Plastic Quad Flatpack Commercial CY7C433–20JC J6532-Lead Plastic Leaded Chip Carrier

CY7C433–20PC P2128-Lead (300-Mil) Molded DIP

25CY7C433–25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C433–25PC P2128-Lead (300-Mil) Molded DIP

CY7C433–25VC V2128-Lead (300-Mil) Molded SOJ

CY7C433–25JI J6532-Lead Plastic Leaded Chip Carrier Industrial 30CY7C433–30JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C433–30PC P2128-Lead (300-Mil) Molded DIP

CY7C433–30JI J6532-Lead Plastic Leaded Chip Carrier Industrial CY7C433–30PI P2128-Lead (300-Mil) Molded DIP

CY7C433–30DMB D2228-Lead (300-Mil) CerDIP Military

CY7C433–30LMB L5532-Pin Rectangular Leadless Chip Carrier

40CY7C433–40JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C433–40PC P2128-Lead (300-Mil) Molded DIP

CY7C433–40VC V2128-Lead (300-Mil) Molded SOJ

CY7C433–40JI J6532-Lead Plastic Leaded Chip Carrier Industrial 65CY7C433–65JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C433–65PC P2128-Lead (300-Mil) Molded DIP

MILITARY SPECIFICATIONS Group A Subgroup Testing

DC Characteristics

Parameters Subgroups V OH1, 2, 3

V OL1, 2, 3

V IH1, 2, 3

V IL Max.1, 2, 3

I IX1, 2, 3

I CC1, 2, 3

I CC11, 2, 3

I SB11, 2, 3

I SB21, 2, 3

I OS1, 2, 3Switching Characteristics Parameters Subgroups t RC9, 10, 11

t A9, 10, 11

t RR9, 10, 11

t PR9, 10, 11

t DVR9, 10, 11

t WC9, 10, 11

t PW9, 10, 11

t WR9, 10, 11

t SD9, 10, 11

t HD9, 10, 11

t MRSC9, 10, 11

t PMR9, 10, 11

t RMR9, 10, 11

t RPW9, 10, 11

t WPW9, 10, 11

t RTC9, 10, 11

t PRT9, 10, 11

t RTR9, 10, 11

t EFL9, 10, 11

t HFH9, 10, 11

t FFH9, 10, 11

t REF9, 10, 11

t RFF9, 10, 11

t WEF9, 10, 11

t WFF9, 10, 11

t WHF9, 10, 11

t RHF9, 10, 11

t RAE9, 10, 11

t RPE9, 10, 11

t WAF9, 10, 11

t WPF9, 10, 11

t XOL9, 10, 11

t XOH9, 10, 11

Package Diagrams

Package Diagrams (continued)