High speed USB On-The-Go ULPI transceiver

September 2010Doc ID 14817 Rev 21/44

STULPI01A STULPI01B

High-speed USB on-the-go ULPI transceiver

Features

■USB-IF high speed certified to the Universal Serial Bus specification rev 2.0

■

Meets the requirements of the Universal Serial Bus specification revision 2.0, on-the-go

supplement to the USB 2.0 specification 1.0a and ULPI transceiver specification 1.1■Standard ULPI (UTMI+ low pin interface) 1.1 digital interface

■Fully compliant with ULPI 1.1 register set ■External square wave clock with DVIO

amplitude must be applied to oscillator input XI ■

Supports 480 Mbit/s high-speed, 12 Mbit/s full-speed and 1.5 Mbit/s low-speed modes of operation

■Supports 2.7 V UART mode.

■

Supports session request protocol (SRP) and host negotiation protocol (HNP) for dual-role device features

■Ability to control external charge pump for higher VBUS currents.

■Single supply, +3 V to +4.5 V voltage range ■Integrated dual voltage regulator to supply internal circuits with stable 3.3 V and 1.2 V ■Integrated overcurrent detector

■Integrated HS termination and FS/LS/OTG pull-up/pull-down resistors

■Integrated USB 2.0 “short-circuit withstand” protection

■Power-down mode with very low power consumption for battery-powered devices ■Ideal for system ASICs with built-in USB host, device or OTG cores

■Available in μTFBGA36 RoHS package ■

–40 °C to 85 °C operating temperature range

Applications

■Mobile phones ■PDAs ■MP3 players ■Digital still cameras ■Set-top box

■

Portable navigation devices

Description

The STULPI01 is a high-speed USB 2.0

transceiver compliant with ULPI (UTMI+ low pin interface) and OTG (on-the-go) specifications, providing a complete physical layer solution for any high-speed USB host, device or OTG dual-role core. It allows USB ASICs to interface with the physical layer of the USB through a 12-pin interface. It contains VBUS comparators, an ID line detector, USB differential drivers and

receivers and a complete ULPI register map and interrupt generator. The STULPI01 transceiver is suitable for mobile applications and battery-powered devices because of its low power

consumption, power-down operating mode and minimal die/package dimensions.

https://www.wendangku.net/doc/6218959067.html,

Contents STULPI01A - STULPI01B

Contents

1Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2Bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3Power-on-reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4UTMI + CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5ULPI wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6External charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.7VBUS comparators and VBUS overcurrent (OC) detector . . . . . . . . . . . . 19

6.8VB_REF_FAULT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.9Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.10ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.11USB 2.0 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.12Power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.13Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.13.1ULPI synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.13.26-pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.13.33-pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.14Car kit (UART) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.15Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.16Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.17VIO OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.18Startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.18.1ULPI device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/44Doc ID 14817 Rev 2

STULPI01A - STULPI01B Contents

6.18.2SDR mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.18.3External clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.18.4Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.18.5Interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.18.6Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.18.7High-speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7State transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8ULPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Doc ID 14817 Rev 23/44

List of tables STULPI01A - STULPI01B List of tables

Table 1.Bill of materials - external components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2.Pinout and bump description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4.Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5.Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6.Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7.Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8.High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9.VB_REF_FAULT configuration bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10.Car kit signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11.Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table https://www.wendangku.net/doc/6218959067.html,B state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13.ULPI register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14.Register access legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 15.Vendor and product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 16.Power control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 17.Function control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 18.Interface control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 19.OTG control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table https://www.wendangku.net/doc/6218959067.html,B interrupt enable rising register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table https://www.wendangku.net/doc/6218959067.html,B interrupt enable falling register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table https://www.wendangku.net/doc/6218959067.html,B interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table https://www.wendangku.net/doc/6218959067.html,B interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 24.Setting rules for interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 25.Debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 26.Scratch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 27.Carkit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 28.Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 29.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4/44Doc ID 14817 Rev 2

STULPI01A - STULPI01B List of figures List of figures

Figure 1.Peripheral only, configuration with external clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4.Rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5.Simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6.VB_REF_FAULT pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure https://www.wendangku.net/doc/6218959067.html,B 2.0 PHY block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8.Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9.RESETn behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10.High-speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11.UARTmode entry (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12.UART mode exit (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Doc ID 14817 Rev 25/44

Application diagrams STULPI01A - STULPI01B

6/44Doc ID 14817 Rev 2

1 Application diagrams

AM04944v1

DVIO DVIO DVIO

CLK DIR S TP NXT D[0]...D[7]

RE S ETn C S n / PWRDN

3V 3V 1V2V

VBAT XI Extern a l clock

19.2/26 MHz DVIO a mplit u tde

XO

ID DP DM VBU S

RREF P S Wn

VB_REF_FAULT

5x GND

Table 1.

Bill of materials - external components

Qty

Symbol

Value

Description

1

C F1

0.1 - 1 μF

Filtering capacitor. Suggested components:muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or T aiyo Yuden 25V X5R (TMK107BJ105KA)2

C F4

0.1 - 1 μF

Filtering capacitor. Suggested components:muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or T aiyo Yuden 25V X5R (TMK107BJ105KA)1

C F2

1μF - 1.5 μF

Filtering capacitor. Suggested components:muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or T aiyo Yuden 25V X5R (TMK107BJ105KA)1C F3 1 - 4.7 μF Filtering capacitor. Suggested components:muRata 10 V Y5V (GRM188F51A475ZE20) or T aiyo Yuden 6.3 V X5R (JMK107BJ475KA)1C T 4.7 μF T ank capacitor 1R REF 12 k Ω

Reference resistor ±1%1E1USBULC6-2F31E2ESDA14V2-2BF3

1

R BUS

2.2 k Ω

Series overvoltage protection resistor

STULPI01A - STULPI01B Bump configuration

Doc ID 14817 Rev 27/44

2 Bump configuration

Table 2.

Pinout and bump description

Bump Symbol Type Description

B1D0I/O Data bit [0] (DVIO referred). UART TXD signal. A1D1I/O Data bit [1] (DVIO referred). UART RXD signal.A2D2I/O Data bit [2] (DVIO referred). UART reserved pin.

A3D3I/O Data bit [3] (DVIO referred). UART active-high interrupt indication.A4CLK O Clock out (DVIO referred).A5D4I/O Data bit [4] (DVIO referred).A6D5I/O Data bit [5] (DVIO referred).B6D6I/O Data bit [6] (DVIO referred).C6D7I/O Data bit [7] (DVIO referred).D6STP I ULPI stop signal (DVIO referred).D5NXT O ULPI next signal (DVIO referred).E5DIR O ULPI direction signal (DVIO referred).

C3CSn/PWRDN I Chip select active-low, power-down active-high.C4RESETn I Active-low asynchronous reset.

D1DP I/O Positive data line of the USB. 5 V tolerant.C1DM I/O Negative data line of the USB. 5 V tolerant.

D3ID I ID pin of the USB connector for initial device role selection. 5 V tolerant.F4VBUS I/O

V BUS line of the USB interface, requires an external capacitor of 4.7μF .F1

NC

Not connected.

Bump configuration STULPI01A - STULPI01B

8/44Doc ID 14817 Rev 2

F2NC Not connected.

E2VB_REF_FAULT

I Voltage reference for internal OC detector input or digital input from external OC detector (V 3V3V referred). 5 V tolerant.

D4PSWn O External charge pump control, active low. 5 V tolerant, open drain.F5XI I External clock input (DVIO referred). Crystal terminal (on request).F6XO O Left floating or connect to GND when external clock signal is used. Crystal terminal on request.

F3VBA T PWR

Battery power input for the LDO (3 V – 4.5 V). Bypass V BAT to GND with a 1 μF capacitor.

E33V3V PWR 3.3 V LDO output. Bypass 3V3V to GND with a 1.5 μF capacitor.E61V2V PWR 1.2 V LDO output. Bypass 1V2V to GND with a 1.5 μF capacitor.C2RREF I/O Reference resistor (12 k Ω ±1%).

B2/B3/B5DVIO PWR

Digital I/O supply voltage. Bypass each DVIO to GND with a

100 nF-1 uF capacitor. Balls B2-B5 can share common capacitor.

C5/D2GND PWR Ground.B4/E4/E1

GND

PWR Ground.

Table 2.

Pinout and bump description (continued)

STULPI01A - STULPI01B Maximum ratings

Doc ID 14817 Rev 29/44

3 Maximum ratings

Note:

Absolute maximum ratings are those values above which damage to the device may occur.

Functional operation under these conditions is not implied. All voltages are referenced to GND.Table 3.

Absolute maximum ratings

Symbol Parameter

Value Unit V DVIO Digital I/O supply voltage

-0.3 to +4.0V V 1V2Digital core supply voltage (provided internally by LDO)-0.3 to +1.4V V 3V3Analog supply voltage (provided internally by LDO)-0.3 to +4.0V V BAT Battery supply voltage

-0.3 to +7.0V V DCDIG DC voltage on digital pins (CLK, DIR, STP , NXT , D[0-7], RESETn)-0.3 to +2.0V V DCANA DC voltage on analog pins (XI, XO, PSWn)

-0.3 to +4.0V V DCVBUS DC voltage on 5 V tolerant pins (VBUS,VB_REF_FAULT, DP , DM, ID)-0.3 to +5.5V T STG Storage temperature range

-40 to +125

°C V ESD-HBM

Electrostatic discharge voltage on all pins (according to JESD22-A114-B)

±2.0

kV

Table 4.

Thermal data

Symbol Parameter

Value Unit R thJA Thermal resistance junction-ambient (simulated value as per JEDEC JSD51)113.8°C/W R thJC Thermal resistance junction-case (simulated value as per JEDEC JSD51)47°C/W R thJB

Thermal resistance junction-base (simulated value as per JEDEC JSD51)

66.2

°C/W

Table 5.

Recommended operating conditions

Symbol Parameter

Min.Typ.Max.Unit V BAT Battery supply voltage 3.0 3.6 4.5V V DVIO Digital I/O supply voltage 1.65 1.80

3.6V T A Operating temperature range -40+85°C C T T ank capacitor

1 4.7 6.5μF R REF External reference resistor

11.88

1212.12

k ΩXTAL

External square wave (01A, 01B versions)19.2 or 26

MHz Recommended rise/fall time

4ns

Electrical characteristics STULPI01A - STULPI01B

10/44Doc ID 14817 Rev 2

4 Electrical characteristics

Table 6.

Electrical characteristics

Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to T A = 25 °C, V DVIO = 1.8 V, V BAT = 3.6 V , R REF = 12 k Ω; C T = 4.7 μF)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Power consumption

I BAT

Supply current

Active mode (USB bus idle)15

mA Active mode (FS

transmission, 12 Mb/s traffic)

30

mA

Active mode (HS transmission)

50mA

Suspend mode (not including DP pull-up current, external clock stopped)120μA

UART mode (no transmission)15mA Power down mode 0.42μA VIO OFF mode (DVIO = 0)

0.42μA I DVIO

ULPI bus supply current DVIO

Power down mode 0.110

μA Active mode, 4 pF load

1.8

mA

Logic inputs and outputs C ULPIIN ULPI port I/O capacitance 2.4

3.5

pF V OH High level output voltage (ULPI bus)

I OH = -2 mA V DVIO -0.15

V V OL Low level output voltage (ULPI bus)

I OL = +2 mA

0.15V I OZH_PSWn High level output leakage (PSWn)

V OH_PSWn = 3.3 V power switch disabled

1.0μA V OL_PSWn

Low level output voltage (PSWn)

I OL = +2 mA power switch enabled

0.15

V V IH High level input voltage (ULPI port and RESETn)0.65xV DVIO

V V IL Low level input voltage (ULPI port and RESETn)0.35xV DVIO

V I IH

High level input leakage current

V IH = V DVIO -0.2 V ±1.0

μA

STULPI01A - STULPI01B Electrical characteristics

Doc ID 14817 Rev 211/44

Symbol Parameter

Test conditions

Min.

Typ.

Max.Unit I IL Low level input leakage cur-rent

V IL

= 0.2 V

±1.0

μA V PDH High level input voltage (CSn/PWRDN pin)V BAT = 3.0 V to 4.5 V 1.4

V V PDL Low level input voltage (CSn/PWRDN pin)V BAT = 3.0 V to 4.5 V 0.4V I PDH High level input leakage current (CSn/PWRDN pin)V PD = 1.4 V , V BAT = 4.5 V ±1.0μA I PDL Low level input leakage current (CSn/PWRDN pin)V PD = 0.4 V , V BAT = 4.5 V ±1.0

μA V FAULTH High level input voltage (VB_REF_FAULT pin)Overcurrent_PD bit is set 0.65xV 3V3

V V FAULTL Low level input voltage (VB_REF_FAULT pin)Overcurrent_PD bit is set

0.15xV 3V3

V R IN_VB_REF

VB_REF_FAULT pin input resistance

112

148168

k ΩV XI_HYST_E XT

External clock input

hysteresis XO = ‘0’ @ reset 500

mV V XIH High level input voltage (XI pin)

XO = ‘0’ @ reset 0.65xV DVIO

V V XIL Low level input voltage (XI pin)

XO = ‘0’ @ reset

0.15xV DVIO

V

VBUS V BUS_LKG V BUS leakage voltage No load

200mV R VBUS V BUS input impedance 40

100

k ΩV BUS_VLD

V BUS valid comparator threshold

1 k Ω series resistors 4.4 4.75V

V SESS_VLD Session valid comparator

threshold for both A and B

device Low to high transition 0.8

1.45

2.0V High to low transition

1.25

V

V SESS_END Session end comparator threshold

0.20.8V R VBUS_PU V BUS charge pull-up resistance

6509501150ΩR VBUS_PD

V BUS discharge pull-down resistance

800

1250

1500

Ω

Table 6.

Electrical characteristics (continued)

Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to T A = 25 °C, V DVIO = 1.8 V, V BAT = 3.6 V , R REF = 12 k Ω; C T = 4.7 μF)

Electrical characteristics STULPI01A - STULPI01B

12/44Doc ID 14817 Rev 2

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Overcurrent detector

V OC Over current trip threshold VB_REF_FAULT – VBUS

V OC = VB_REF_FAULT – VBUS

20

45

95

mV

ID I ID_PU ID pin pull-up current V ID = 0V

70

μA R ID_GND ID line short resistance to detect ID GND state 1

k ΩR ID_FLOA T

ID line short resistance to detect ID FLOA T state

100

k Ω

UART mode (2.7 V ± 5 %)V OH_UART High level output voltage (D1,D3)

I OH = -2 mA V DVIO -0.15

V V OL_UART

Low level output voltage (D1,D3)

I OL = +2 mA

0.15

V V IH_UART_D 0High level input voltage

(D0)0.65xV DVIO

V V IL_UART_D0Low level input voltage (D0)0.35xV DVIO

V V OH_DFMS High level output voltage (DP)

I OH = -2 mA

2.16 2.85V V OL_DFMS Low level output voltage (DP)

I OL = +2 mA, Pull-up=10k Ω

-0.100.37V V IH_DTMS High level input voltage (DM)

2.0

3.0V V IL_DTMS

Low level input voltage (DM)

-0.3

0.81

V

Full-speed/low-speed driver

Z DRV Output impedance (acting also as high-speed termination)

40.549.5ΩV OH_DRV High level output voltage R LH = 14.25 k Ω 2.8 3.6V V OL_DRV Low level output voltage R LL = 1.425 k Ω0.00.3V V CRS

Driver crossover voltage

C LOA

D =50 to 600pF (1)

1.3

1.67

2.0

V

High-speed driver V HSOI HS idle level

-1010mV V HSDPJ HS data DP J state level (1)

380440mV V HSDK

HS data DP K state level

-10

10

mV

Table 6.

Electrical characteristics (continued)

Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to T A = 25 °C, V DVIO = 1.8 V, V BAT = 3.6 V , R REF = 12 k Ω; C T = 4.7 μF)

STULPI01A - STULPI01B Electrical characteristics

Doc ID 14817 Rev 213/44

Symbol Parameter

Test conditions Min.Typ.Max.Unit V HSDNJ HS data DN J state level (1)

380440mV V HSDNK HS data DN K state level -1010mV V CHIRPJ Chirp J level (differential voltage)

(1)7001100mV V CHIRPK

Chirp K level (differential voltage

-900

-500

mV

Full-speed/Low-speed receivers

V DI Diff. receiver input sensitivity (V DP -V DM )V CM = 0.8 to 2.5 V 200mV V SE_TH SE receivers switching threshold Low to high transition 0.8 1.6 2.0V High to low transition 0.8 1.1

2.0

V R INP Input resistance PU/PD resistors deactivated

300

k ΩC IN

Input capacitance (1)

5pF ΔCIN

Difference in capacitance between DP and DM input 10%V DT_LKG

Data line leakage voltage

R PU_EXT = 300 k Ω342

mV

High-speed receiver V HSSQ HS squelch detector threshold

100150mV V HSDSC HS disconnect detection threshold

525625mV V HSCM HS data signaling common mode volt. range (1)-50500mV V HSTERM

Termination voltage in HS

(1)

-10

10

mV

Data pull-up/pull-down resistors

R PU Data line pull-up resistance (DP , DM)

1.425k ΩV IHZ FS idle high level voltage

2.7V R PD

Data line pull-down resistance (DP , DM)

14.25

24.8

k Ω

Voltage regulator 3V3V 3.3 V internal power supply

voltage

V BAT = 3.6 V , active mode

3.26 3.4 3.54V 1V2V

1.2 V internal power supply

voltage

V BAT = 3.6 V , active mode

1.187

1.25

1.31

V

1.Guaranteed by design.

Table 6.

Electrical characteristics (continued)

Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to T A = 25 °C, V DVIO = 1.8 V, V BAT = 3.6 V , R REF = 12 k Ω; C T = 4.7 μF)

Electrical characteristics STULPI01A - STULPI01B

14/44Doc ID 14817 Rev 2

Table 7.

Switching characteristics

(Over recommended operating conditions unless otherwise noted. All the typical values are referred to T A = 25 °C, V DVIO = 1.8 V , V BAT = 3.6 V , C T = 4.7 μF)

Symbol Parameter

Test conditions

Min.

Typ.

Max.

Unit

Reset t RESETEXT Width of reset pulse on RESETn pin

10

μs

UART mode

t RISE Switching time (max low to min high)C LOAD = 185 pF 215ns t FALL Switching time (min high to max low)C LOAD = 185 pF 215ns t PD_RX Delay time (50% DM to 50% D1)C L = 10 pF

60ns t PD_TX

Delay time (50% D0 to 50% DP)

60ns t UARTON2V7T urn-on time for TXD line (2V7)UART_2V7 = 1 measured from DIR assertion 2

2.5ms t UARTOFF2V7T urn-off time for TXD line (2V7)UART_2V7 = 1 measured from STP assertion 1μs t UARTON T urn-on time for TXD line UART_2V7 = 0 measured from DIR assertion 60ns t UARTOFF

T urn-off time for TXD line

UART_2V7 = 0 measured from DIR de-assertion

60

ns

Low-speed driver

t LR Data signal rise time C LOAD = 600 pF 75100300ns t LF Data signal fall time C LOAD = 600 pF

75100

300ns RFM LS Rise and fall time matching -2020%DR LS Low-speed data rate 1.49925 1.50075Mb/s

t DDJ1Data jitter to next transition Includes freq. tolerances -2525ns t DDJ2Data jitter for paired transitions Includes freq. tolerances -1414ns t LEOPT

SE0 interval of EOP

1250

1500

ns

Full-speed driver

t FR Data signal rise time C LOAD = 50 pF 420ns t FF Data signal fall time C LOAD = 50 pF

420ns RFM FS Rise and fall time matching -10+10%DR HS Full-speed data rate 11.99412.006Mb/s t DJ1Data jitter to next transition Includes freq. tolerances -3.5 3.5ns t DJ2Data jitter for paired transitions Includes freq. tolerances -44ns t FEOPT

SE0 interval of EOP

160

175

ns

Clock generation constants

t PLL PLL lock time (1)200μs t DLL

DLL lock time

(1)

280

μs

STULPI01A - STULPI01B Electrical characteristics

Doc ID 14817 Rev 215/44

Symbol Parameter

Test conditions

Min.

Typ.

Max.

Unit

High-speed driver

t HSR Data rise time 500ps t HSF

Data fall time

500

ps

Waveform requirements including jitter

Specified by eye pattern

(Figure 3)DR HS

High-speed data rate

479.76

480.24

Mb/s ULPI interface

CLOCK (measured on CLK pin)f START_U Frequency (first transition)(1)

54 6066MHz f STEADY_U Frequency (steady state)59.97 6060.03 MHz D START_U Duty cycle (first transition)405060%D STEADY_U Duty cycle (steady state)

(1)45

50

55

%

T STEADY_U Time to reach steady state

frequency and duty cycle after first transition (1)

1.4 ms

T JITTER_U

Jitter

400

ps

t SCLK60OUT Clock startup time Measured from assertion of STP during suspend, or after release of RESETn pin

250900μs

ULPI control signals (SDR mode) (1)

T SC_U Control in setup time C LOAD = 15 pF

V DVIO = 1.65 - 3.6 V

6.0

ns T HC_U Control in hold time 0.0

ns T DC_U

Control output delay

9.0

ns

ULPI data signals (SDR mode) (1)

T SD_U Data in setup time C LOAD = 15 pF

V DVIO = 1.65 - 3.6 V

6.0ns T HD_U Data in hold time 3.0

ns T DD_U

Data output delay

9.0

ns

1.Guaranteed by design.

Table 7.

Switching characteristics (continued)

(Over recommended operating conditions unless otherwise noted. All the typical values are referred to T A = 25 °C, V DVIO = 1.8 V , V BAT = 3.6 V , C T = 4.7 μF)

Electrical characteristics STULPI01A - STULPI01B

16/44Doc ID 14817 Rev 2

Table 8.High-speed driver eye pattern

Level 1

Level 2Point 1Point 2Point 3Point 4Point 5Point 6Voltage level (DP – DM)525 mV (1)475 mV

–525 mV (1)

–475 mV

0 V 0 V 300 mV 300 mV –300 mV –300 mV Time

(% of unit interval)

5%

95%

35%

65%

35%

65%

1.This value is valid for unit intervals following a transition. For all other intervals the other value is valid.

STULPI01A - STULPI01B Timing diagram

Doc ID 14817 Rev 217/44

5 Timing diagram

Block description STULPI01A - STULPI01B

18/44Doc ID 14817 Rev 2

6 Block description

The STULPI01 integrates a comparator for the VBUS, ID line detector, differential HS data

driver, differential and single-ended receivers, low dropout voltage regulators, and control logic.

The STULPI01 provides a complete solution for connection of a digital USB host/device/OTG controller to a USB bus.

6.1 Oscillator and PLL

An external clock (digital square wave DVIO referred) driven into XI must be used (version

STULPI01A or STULPI01B).

The PLL internally produces all frequencies needed for operation:

●60 MHz clock for the UTMI core and ULPI interface controller ● 1.5 MHz for low-speed USB data ●12 MHz for full-speed USB data ●480 MHz for high-speed USB data

●

Other internal frequencies for data conversion and data recovery

6.2 Voltage reference

This block provides the precise reference voltage needed by internal circuit.

It requires a 12 k Ω +/- 1% resistor connected to the R REF pin.

6.3 Power-on-reset (POR)

The power-on-reset circuit generates a reset pulse upon power-up which is used to initialize

the entire digital logic. Power-on-reset senses the V 3V3V and V 1V2V voltage.

During the power-on-reset pulse, the ULPI pins are in a high impedance state with pull-down/pull-up resistors disabled.

6.4 UTMI + CORE

This is the digital heart of the chip and performs the bit-stuffing, NRZI decoding and serial-to-parallel conversion during receive and the reverse operation during transmit for HS and FS/LS.

6.5 ULPI wrapper

This implements the ULPI related protocol and conversion from UTMI+ to ULPI interface.

This block also implements the interrupt logic and complete ULPI register set.

STULPI01A - STULPI01B Block description

Doc ID 14817 Rev 219/44

6.6 External charge pump

It is possible to use an external charge pump or power switch controlled by the PSWn pin (active low open drain). This functionality is controlled by DrvVbus and DrvVbusExternal ULPI OTG Control register bits.

6.7 V BUS comparators and V BUS overcurrent (OC) detector

These comparators monitor the V BUS voltage.

V BUS valid status signalizes that the voltage is above the V BUS_VLD level (4.4 V). Session valid status signalizes that the V BUS voltage is above the V SESS_VLD level (0.8 to 2.0 V). Session end detector signalizes V BUS voltage is below V SESS_END level.

STULPI01 also implements embedded V BUS over current detector which compares V BUS voltage to external analog 5 V reference signal applied to VB_REF_FAULT pin.

6.8 VB_REF_FAULT pin

V BUS overcurrent conditions can be monitored by either internal or an external OC detector.

The internal OC detector is enabled when over-current_PD bit in the Power Control register (Vendor-specific area) is set to 0b and Use External VBUS Indicator is set to 1b. In this mode, the VB_REF_FAULT pin functions as the input of the analog reference for internal over-current detector.

If the external charge pump is already equipped with an overcurrent detector, its output can be also monitored through VB_REF_FAULT pin, but overcurrent_PD bit must be set to 1b. In this mode VB_REF_FAULT will function as standard digital input pin with 5 V tolerance. Functionality of VB_REF_FAULT pin can be seen in more detail (on Figure 6).

Note:After reset, overcurrent_PD bit is 1b, internal overcurrent detector is disabled.

Block description STULPI01A - STULPI01B

20/44Doc ID 14817 Rev 2

6.9 Voltage regulator

Dual output ultra low dropout voltage regulator provides power supply for analog and digital

internal circuits. An external capacitor on both 3V3V and 1V2V pins is needed for proper operation.

6.10 ID detector

This block provides sensing of status of the ID line. It is capable of detecting whether the pin

is floating or tied to the ground.

6.11 USB 2.0 PHY

The USB 2.0 PHY block provides complete physical layer transceiver for low-speed, full-speed, and high-speed USB operating modes. Analog part of this block deals with

impedances adaptation, controlled voltage swing, and common mode voltage generation and sensing. Digital part consists of serializer and deserializer, transforming serial bit

stream to 8-bit parallel port, and finite state machine implementing the PHY protocol layer, bit stuffing, unstuffing etc.

Table 9.VB_REF_FAULT configuration bit settings

RX CMD VBUS Valid

Use External Vbus Indicator

Overcurrent_PD

Indicator Pass-true

Indicator Complement

VBUSVLD 01X X VBOC

101X VBOC and VBUSVLD

100X neg (FAULT)1110FAULT

1111VBUSVLD and FAULT 1101VBUS_VLD and neg (FAULT)

1

1