AM29LV800DB-70WCC中文资料
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-inally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate,and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Am29L V800D
Data Sheet
Publication Number Am29LV800D_00 Revision A Amendment 4 Issue Date January 21, 2005
For new designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration path. Please refer to the S29AL008D Data Sheet for specifications and ordering information.
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the right to change or discontinue work on this proposed product without notice.Publication Am29LV800D_00 Rev. A Amend. 4 Issue Date: January 21, 2005
Am29LV800D
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory Distinctive Characteristics
■Single power supply operation
—2.7 to 3.6 volt read and write operations for battery-powered applications
■Manufactured on 0.23 μm process technology
—Compatible with 0.32 μm Am29LV800 device
■High performance
—Access times as fast as 70 ns
■Ultra low power consumption (typical values at 5 MHz)
—200 nA Automatic Sleep mode current
—200 nA standby mode current
—7 mA read current
—15 mA program/erase current
■Flexible sector architecture
—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode)
—One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode)
—Supports full chip erase
—Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■Unlock Bypass Program Command —Reduces overall programming time when issuing multiple program command
sequences ■Top or bottom boot block configurations available
■Embedded Algorithms
—Embedded Erase algorithm automatically preprograms and erases the entire chip or any
combination of designated sectors
—Embedded Program algorithm
automatically writes and verifies data at
specified addresses
■Minimum 1 million write cycle guarantee per sector
■20-year data retention at 125°C
—Reliable operation for the life of the system
■Package option
—48-ball FBGA
—48-pin TSOP
—44-pin SO
■Compatibility with JEDEC standards —Pinout and software compatible with single-power supply Flash
—Superior inadvertent write protection
■Data# Polling and toggle bits
—Provides a software method of detecting program or erase operation completion
■Ready/Busy# pin (RY/BY#)
—Provides a hardware method of detecting program or erase cycle completion
■Erase Suspend/Erase Resume
—Suspends an erase operation to read data from, or program data to, a sector that is not being
erased, then resumes the erase operation
■Hardware reset pin (RESET#)
—Hardware method to reset the device to reading array data
For new designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration path. Please refer to the S29AL008D Data Sheet for specifications and ordering information.
General Description
The Am29LV800D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt V CC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.
This device is manufactured using AMD’s 0.23 μm process technology, and offers all the fea-tures and benefits of the Am29LV800B, which was manufactured using 0.32 μm process tech-nology.
The standard device offers access times of 70, 90, and 120 ns, allowing high speed micropro-cessors to operate without wait states. To elim-inate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write func-tions. Internally generated and regulated volt-ages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard micropro-cessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase opera-tions. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster pro-gramming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase c o m m a n d s e q u e n c e.T h i s i n i t i a t e s t h e Embedded Erase algorithm—an internal algo-rithm that automatically preprograms the array (if it is not already programmed) before exe-cuting the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any com-bination of the sectors of memory. This can be achieved in-system or via programming equip-ment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the auto-matic sleep mode. The system can also place the device into the standby mode. Power con-sumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is pro-grammed using hot electron injection.
2Am29LV800D Am29LV800D_00_A4_E January 21, 2005
T able Of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA Package (7)
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Standard Products (8)
Valid Combinations. . . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .10 Table 1. Am29LV800D Device Bus Operations .10 Word/Byte Configuration (10)
Requirements for Reading Array Data (10)
Writing Commands/Command Sequences (11)
Program and Erase Operation Status (11)
Standby Mode (11)
Automatic Sleep Mode (11)
RESET#: Hardware Reset Pin (11)
Output Disable Mode (12)
Table 2. Am29LV800DT Top Boot Block
Sector Addresses (12)
Table 3. Am29LV800DB Bottom Boot Block
Sector Addresses (13)
Autoselect Mode (13)
Table 4. Am29LV800D Autoselect Codes
(High Voltage Method) (14)
Sector Protection/Unprotection (14)
Temporary Sector Unprotect (14)
Figure 1. Temporary Sector Unprotect
Operation (15)
Figure 2. In-System Sector Protect/
Sector Unprotect Algorithms (16)
Hardware Data Protection (17)
Command Definitions. . . . . . . . . . . . . . . . . . . . . . 17 Reading Array Data (17)
Reset Command (17)
Autoselect Command Sequence (18)
Word/Byte Program Command Sequence (18)
Figure 1. Program Operation (19)
Chip Erase Command Sequence (19)
Sector Erase Command Sequence (19)
Erase Suspend/Erase Resume Commands (20)
Figure 1. Erase Operation (21)
Table 5. Am29LV800D Command Definitions ..21 Write Operation Status . . . . . . . . . . . . . . . . . . . . 22 DQ7: Data# Polling (22)
Figure 1. Data# Polling Algorithm (23)
RY/BY#: Ready/Busy# (23)
DQ6: Toggle Bit I (24)
DQ2: Toggle Bit II (24)
Reading Toggle Bits DQ6/DQ2 (24)
DQ5: Exceeded Timing Limits (25)
DQ3: Sector Erase Timer (25)
Figure 1. Toggle Bit Algorithm (25)
Table 6. Write Operation Status ....................26Absolute Maximum Ratings . . . . . . . . . . . . . . . . 27 Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .28 CMOS Compatible (28)
Figure 1. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) (29)
Figure 1. Typical I CC1 vs. Frequency (29)
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 1. Test Setup (30)
Table 7. Test Specifications (30)
Key to Switching Waveforms. . . . . . . . . . . . . . . . 30 Figure 1. Input Waveforms and
Measurement Levels (30)
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read Operations (31)
Figure 1. Read Operations Timings (31)
Hardware Reset (RESET#) (32)
Figure 1. RESET# Timings (32)
Word/Byte Configuration (BYTE#) (33)
Figure 1. BYTE# Timings for Read
Operations (34)
Figure 1. BYTE# Timings for Write
Operations (34)
Erase/Program Operations (35)
Figure 1. Program Operation Timings (36)
Figure 1. Chip/Sector Erase Operation
Timings (37)
Figure 1. Data# Polling Timings (During
Embedded Algorithms) (38)
Figure 1. Toggle Bit Timings (During
Embedded Algorithms) (38)
Figure 1. DQ2 vs. DQ6 (39)
Temporary Sector Unprotect (39)
Figure 1. Temporary Sector Unprotect
Timing Diagram (39)
Figure 1. Sector Protect/Unprotect
Timing Diagram (40)
Alternate CE# Controlled
Erase/Program Operations (41)
Figure 1. Alternate CE# Controlled Write
Operation Timings (42)
Erase and Programming Performance . . . . . . . . .43 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 43 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 43 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . . .44 TS 048—48-Pin Standard TSOP (44)
TSR048—48-Pin Reverse TSOP (45)
FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm (46)
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 47 VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA) 6.15 x 8.15 mm (47)
SO 044—44-Pin Small Outline Package (48)
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .49
January 21, 2005 Am29LV800D_00_A4_E Am29LV800D3
4Am29LV800D Am29LV800D_00_A4_E January 21, 2005
Product Selector Guide
Note: See “AC Characteristics” for full specifications.
Block Diagram
Family Part Number Am29LV800D
Speed Options
Full Voltage Range: V CC = 2.7–3.6 V
-70
-90
-120
Max access time, ns (t ACC )7090120Max CE# access time, ns (t CE )7090120Max OE# access time, ns (t OE )
30
35
50
Input/Output
Buffers X-Decoder
Y-Decoder Chip Enable Output Enable
Erase Voltage Generator
PGM Voltage Generator
Timer
V CC Detector
State Control Command Register
V CC V SS WE#BYTE#
CE#OE#
STB
STB
DQ0–DQ15 (A-1)
Sector Switches RY/BY#
RESET#
Data
Y-Gating
Cell Matrix
A d d r e s s L a t c h
A0–
Am29LV800D_ January 21, 2005 Am29LV800D_00_A4_E Am29LV800D5
6Am29LV800D Am29LV800D_00_A4_E January 21, 2005
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for pro-longed periods of time.
Pin Configuration
A0–A18=19 addresses
DQ0–DQ14=15 data inputs/outputs
DQ15/A-1=DQ15 (data input/output, word
mode),
A-1 (LSB address input, byte
mode)
BYTE#=Selects 8-bit or 16-bit mode
CE#=Chip enable
OE#= Output enable
WE#=Write enable
RESET#=Hardware reset pin, active low
RY/BY#= Ready/Busy# output V CC= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
V SS=Device ground
NC=Pin not connected internally Logic Symbol
19
16 or 8
DQ0–DQ15
(A-1)
A0–A18
CE#
OE#
WE#
RESET
BYTE#RY/BY#
January 21, 2005 Am29LV800D_00_A4_E Am29LV800D7
8Am29LV800D Am29LV800D_00_A4_E January 21, 2005
Ordering Information Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29LV800D
T
-70
E
C
TEMPERATURE RANGE C =Commercial (0°C to +70°C)D Commercial (0°C to +70°C) with Pb-Free Package I =
Industrial (–40°C to +85°C)F =
Industrial (–40°C to +85°C) with Pb-Free Package
PACKAGE TYPE E =48-Pin Thin Small Outline Package (TSOP) Standard Pinout
(TS 048)
F =48-Pin Thin Small Outline Package (TSOP) Reverse Pinout
(TSR048)
S =44-Pin Small Outline Package (SO 044)WB =48-Ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 9 mm package (FBB048)
WC =48-Ball Fine Pitch Ball Grid Array (FBGA)
=0.80 mm pitch, 6.15 x 8.15 mm package (VBK 048)SPEED OPTION
See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29LV800D 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP and SO Packages AM29LV800DT-70, AM29LV800DB-70AM29LV800DT-90, AM29LV800DB-90AM29LV800DT-120, AM29LV800DB-120
EC, EI, ED, EF , FC, FD, FF , FI,
SC, SD, SF , SI EC, EI, ED,EF ,FD, FF ,FC,
FI,SD, SFSC, SI
January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 9
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations for FBGA Packages
Order Number
Package Marking
AM29LV800DT-70,AM29LV800DB-70
WBC WBI WBD
WBF WCC WCI WCD WCF L800DT70V ,L800DB70V
C, I,D,F
AM29LV800DT-90,AM29LV800DB-90
WCC WCI WCD
WCF WBC WBI WBD WBF L800DT90V ,L800DB90V
AM29LV800DT-120,AM29LV800DB-120
WBC
WBI WBD WBF
L800DT12V ,L800DB12V
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1. Am29LV800D Device Bus Operations
Legend:
L = Logic Low = V IL, H = Logic High = V IH, V ID = 12.0 ± 0.5 V, X = Don’t Care, A IN = Address In, D IN = Data In, D OUT = Data Out Notes:
1.Addresses are A18:A0 in word mode (BYTE# = V IH), A18:A-1 in byte mode (BYTE# = V IL).
2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See
the “Sector Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and O E#. The d ata I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 1 for the timing dia-gram. I CC1 in the DC Characteristics table repre-sents the active current specification for reading array data.
Operation CE#OE
#
WE
#
RESET
#
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE
#
= V IH
BYTE#
= V IL
Read L L H H A IN D OUT D OUT DQ8–DQ14 = High-
Z, DQ15 = A-1 Write L H L H A IN D IN D IN
Standby V CC±
0.3 V
X X
V CC±
0.3 V
X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2)L H L V ID Sector Address,
A6 = L, A1 = H,
A0 = L
D IN X X
Sector Unprotect (Note 2)L H L V ID Sector Address,
A6 = H, A1 = H,
A0 = L
D IN X X
Temporary Sector Unprotect X X X V ID A IN D IN D IN High-Z
10Am29LV800D Am29LV800D_00_A4_E January 21, 2005
Writing Commands/Command Sequences To write a command or command sequence
(which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to V IH.
For program operations, the BYTE# pin deter-mines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configu-ration” for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on pro-gramming data to the device using both stan-dard and Unlock Bypass command sequences. An erase operation can erase one sector, mul-tiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or sus-pending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is sepa-rate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more infor-mation.
I CC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics”for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires stan-dard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or pro-gramming, the device draws active current until the operation is completed.
In the DC Characteristics table, I CC3 and I CC4 represents the standby current specification. Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device auto-matically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address a c c es s ti m i ng s p r ov i d e ne w d a ta w h en addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t RP, the device immediately termi-nates any operation in progress, tristates all output pins, and ignores all read/write com-mands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (I CC4). If RESET# is held at V IL but not within V SS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
January 21, 2005 Am29LV800D_00_A4_E Am29LV800D11
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t R E A D Y (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not exe-cuting (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RESET# pin returns to V IH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 1 for the timing diagram.
Output Disable Mode
When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 2. Am29LV800DT Top Boot Block Sector Addresses
Sector A18A17A16A15A14A13A12Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x8)
Address Range
(x16)
Address Range
SA00000X X X64/3200000h–0FFFFh00000h–07FFFh SA10001X X X64/3210000h–1FFFFh08000h–0FFFFh SA20010X X X64/3220000h–2FFFFh10000h–17FFFh SA30011X X X64/3230000h–3FFFFh18000h–1FFFFh SA40100X X X64/3240000h–4FFFFh20000h–27FFFh SA50101X X X64/3250000h–5FFFFh28000h–2FFFFh SA60110X X X64/3260000h–6FFFFh30000h–37FFFh SA70111X X X64/3270000h–7FFFFh38000h–3FFFFh SA81000X X X64/3280000h–8FFFFh40000h–47FFFh SA91001X X X64/3290000h–9FFFFh48000h–4FFFFh SA101010X X X64/32A0000h–AFFFFh50000h–57FFFh SA111011X X X64/32B0000h–BFFFFh58000h–5FFFFh SA121100X X X64/32C0000h–CFFFFh60000h–67FFFh SA131101X X X64/32D0000h–DFFFFh68000h–6FFFFh SA141110X X X64/32E0000h–EFFFFh70000h–77FFFh SA1511110X X32/16F0000h–F7FFFh78000h–7BFFFh SA1611111008/4F8000h–F9FFFh7C000h–7CFFFh SA1711111018/4FA000h–FBFFFh7D000h–7DFFFh SA18111111X16/8FC000h–FFFFFh7E000h–7FFFFh
12Am29LV800D Am29LV800D_00_A4_E January 21, 2005
Table 3. Am29LV800DB Bottom Boot Block Sector Addresses
Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its cor-responding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires V ID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require V ID. See “Com-mand Definitions” for details on using the autoselect mode.
Sector A18A17A16A15A14A13A12Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x8)
Address Range
(x16)
Address Range
SA0000000X16/800000h–03FFFh00000h–01FFFh SA100000108/404000h–05FFFh02000h–02FFFh SA200000118/406000h–07FFFh03000h–03FFFh SA300001X X32/1608000h–0FFFFh04000h–07FFFh SA40001X X X64/3210000h–1FFFFh08000h–0FFFFh SA50010X X X64/3220000h–2FFFFh10000h–17FFFh SA60011X X X64/3230000h–3FFFFh18000h–1FFFFh SA70100X X X64/3240000h–4FFFFh20000h–27FFFh SA80101X X X64/3250000h–5FFFFh28000h–2FFFFh SA90110X X X64/3260000h–6FFFFh30000h–37FFFh SA100111X X X64/3270000h–7FFFFh38000h–3FFFFh SA111000X X X64/3280000h–8FFFFh40000h–47FFFh SA121001X X X64/3290000h–9FFFFh48000h–4FFFFh SA131010X X X64/32A0000h–AFFFFh50000h–57FFFh SA141011X X X64/32B0000h–BFFFFh58000h–5FFFFh SA151100X X X64/32C0000h–CFFFFh60000h–67FFFh SA161101X X X64/32D0000h–DFFFFh68000h–6FFFFh SA171110X X X64/32E0000h–EFFFFh70000h–77FFFh SA181111X X X64/32F0000h–FFFFFh78000h–7FFFFh
January 21, 2005 Am29LV800D_00_A4_E Am29LV800D13
Table 4. Am29LV800D Autoselect Codes (High Voltage Method) L = Logic Low = V IL, H = Logic High = V IH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.
The device is shipped with all sectors unpro-tected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s Express-Flash? Service. Contact an AMD representative for details.
It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.
Sector Protection/unprotection can be imple-mented via two methods.
The primary method requires V ID on the RESET# pin only, and can be implemented either in-system or via programming equip-ment. Figure 2 shows the algorithms and Figure 1 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unpro-tect write cycle.
The alternate method intended only for pro-gramming equipment requires V ID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 20536 contains further details; contact an AMD representative to request a copy.
T emporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is acti-vated by setting the RESET# pin to V ID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V ID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algo-
Description Mode CE#OE#WE
#
A1
8
to
A1
2
A1
1
to
A1
0A9
A8
to
A7A6
A5
to
A2A1A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V ID X L X L L X01h
Device ID:
Am29LV800B (Top Boot Block)Word L L H
X X V ID X L X L H
22h DAh Byte L L H X DAh
Device ID: Am29LV800B (Bottom Boot Block)Word L L H
X X V ID X L X L H
22h5Bh Byte L L H X5Bh
Sector Protection Verification L L H SA X V ID X L X H L
X
01h
(protected)
X
00h
(unprotecte
d)
14Am29LV800D Am29LV800D_00_A4_E January 21, 2005
January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 15
rithm, and Figure 1 shows the timing diagrams, for this feature.
Figure 1. Temporary Sector Unprotect
Operation
START
Perform Erase or Program Operations
RESET# = V IH
Temporary Sector Unprotect Completed
(Note 2)
RESET# = V ID
(Note 1)Notes:
1.All protected sectors unprotected.
2.All previously protected sectors are protected
once again.
Figure 2. In-System Sector Protect/
Sector Unprotect Algorithms
16Am29LV800D Am29LV800D_00_A4_E January 21, 2005
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for command definitions). In addition, the following hardware data protection mea-sures prevent accidental erasure or program-ming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise.
Low V CC Write Inhibit
When V CC is less than V LKO, the device does not accept any write cycles. This protects data during V CC power-up and power-down. The co mm a nd r egis ter a nd a ll inter na l pr o-gram/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than V LKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V IL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept com-mands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 defines the valid reg-ister command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appro-priate timing diagrams in the “AC Characteris-tics” section.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algo-rithm.
After the device accepts an Erase Suspend com-mand, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Sus-pend/Erase Resume Commands” for more infor-mation on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data”in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 1 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, how-ever, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the opera-tion is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).
January 21, 2005 Am29LV800D_00_A4_E Am29LV800D17
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alter-native to that shown in Table 4, which is intended for PROM programmers and requires V ID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unpro-tected. Refer to Tables 2 and 3 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further con-trols or timings. The device automatically pro-vides internally generated program pulses and verifies the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is com-plete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-g r am m e d f r o m a “0”b ac k to a“1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algo-rithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock by pass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode.
A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence con-tains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is pro-grammed in the same manner. This mode dis-penses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 5 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset com-mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 1 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 1 for timing dia-grams.
18Am29LV800D Am29LV800D_00_A4_E January 21, 2005