1/10
June 2001
STP3NC70Z STP3NC70ZFP
N-CHANNEL 700V - 4.1? - 2.5A TO-220/TO-220FP
Zener-Protected PowerMESH?III MOSFET
(1) I SD ≤2.5A, di/dt ≤100A/μs, V DD ≤ V (BR)DSS , T j ≤ T JMAX
(*) Limited by Maximum Temperature allowed
s TYPICAL R DS (on) = 4.1?
s
EXTREMELY HIGH dv/dt AND CAPABILITY GATE TO - SOURCE ZENER DIODES s 100% AVALANCHE TESTED
s VERY LOW GATE INPUT RESISTANCE s
GATE CHARGE MINIMIZED
DESCRIPTION
The third generation of MESH OVERLAY ? Power MOSFETs for very high voltage exhibits unsur-passed on-resistance per unit area while integrat-ing back-to-back Zener diodes between gate and source. Such arrangement gives extra ESD capa-bility with higher ruggedness performance as re-quested by a large variety of single-switch applications.
APPLICATIONS
s SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION s WELDING EQUIPMENT ABSOLUTE MAXIMUM RATINGS
(?)Pulse width limited by safe operating area
TYPE V DSS R DS(on)I D STP3NC70Z STP3NC70ZFP
700V 700V
< 4.7?< 4.7?
2.5 A 2.5 A
Symbol Parameter
Value
Unit STP3NC70Z
STP3NC70ZFP
V DS Drain-source Voltage (V GS = 0)700V V DGR Drain-gate Voltage (R GS = 20 k ?)700V V GS Gate- source Voltage
± 25
V I D Drain Current (continuos) at T C = 25°C 2.5 2.5 (*)A I D Drain Current (continuos) at T C = 100°C 1.6 1.6 (*)A I DM (q )Drain Current (pulsed)1010A P TOT Total Dissipation at T C = 25°C 6535W Derating Factor
0.52
0.28W/°C I GS Gate-source Current (DC)
±50mA V ESD(G-S)Gate source ESD(HBM-C=100pF, R=1.5K ?) 1.5KV dv/dt (1)Peak Diode Recovery voltage slope 3
V/ns V ISO Insulation Withstand Voltage (DC)-2500V T stg Storage Temperature
–65 to 150
°C T j
Max. Operating Junction Temperature
150
°C
STP3NC70Z/STP3NC70ZFP
2/10
THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFF
ON (1)
DYNAMIC
TO-220
TO-220FP Rthj-case Thermal Resistance Junction-case Max 1.92
3.57
°C/W Rthj-amb
Thermal Resistance Junction-ambient Max
62.5°C/W T l
Maximum Lead Temperature For Soldering Purpose
300
°C
Symbol Parameter
Max Value
Unit I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max)
2.5A E AS
Single Pulse Avalanche Energy
(starting T j = 25 °C, I D = I AR , V DD = 50 V)
150
mJ
Symbol Parameter
Test Conditions
Min.Typ.
Max.
Unit V (BR)DSS
Drain-source
Breakdown Voltage
I D = 250 μA, V GS = 0700
V ?BV DSS /?T J Breakdown Voltage Temp.
Coefficient
I D = 1 mA, V GS = 00.8
V/°C I DSS Zero Gate Voltage
Drain Current (V GS = 0)V DS = Max Rating
1μA V DS = Max Rating, T C = 125 °C 50μA I GSS
Gate-body Leakage Current (V DS = 0)
V GS = ±20V
±10
μA
Symbol Parameter
Test Conditions
Min.Typ.Max.Unit V GS(th)Gate Threshold Voltage V DS = V GS , I D = 250μA 3
45V R DS(on)
Static Drain-source On Resistance
V GS = 10V, I D = 1.25 A
4.1
4.7
?
Symbol Parameter
Test Conditions
Min.
Typ.Max.
Unit g fs (1)Forward Transconductance V DS > I D(on) x R DS(on)max, I D =1.25A
2S C iss Input Capacitance V DS = 25V, f = 1 MHz, V GS = 0
530pF C oss Output Capacitance 50pF C rss
Reverse Transfer Capacitance
7
pF
3/10
STP3NC70Z/STP3NC70ZFP
ELECTRICAL CHARACTERISTICS (CONTINUED)SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
GATE-SOURCE ZENER DIODE
Note: 1.Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %.
2.Pulse width limited by safe operating area.
3.?V BV = αT (25°-T) BV GSO (25°)
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to souce. In this respect the 25V Zener voltage is appropiate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.
Symbol Parameter
Test Conditions
Min.
Typ.Max.
Unit t d(on)Turn-on Delay Time V DD = 350 V, I D = 1.25 A R G =4.7? V GS = 10V (see test circuit, Figure 3)14ns t r Rise Time 11ns Q g Total Gate Charge V DD = 560V, I D = 2.5A,V GS = 10V
1724nC Q gs Gate-Source Charge 4nC Q gd
Gate-Drain Charge
7
nC
Symbol Parameter
Test Conditions
Min.
Typ.Max.
Unit t r(Voff)Off-voltage Rise Time
V DD = 560V, I D = 2.5 A, R G =4.7?, V GS = 10V (see test circuit, Figure 5)
16ns t f Fall Time 33ns t c
Cross-over Time
40
ns
Symbol Parameter
Test Conditions
Min.
Typ.
Max.Unit I SD Source-drain Current 2.5A I SDM (2)Source-drain Current (pulsed)10A V SD (1)Forward On Voltage I SD = 2.5 A, V GS = 0 1.6
V t rr Reverse Recovery Time I SD = 2.5 A, di/dt = 100A/μs, V DD = 27V, T j = 150°C (see test circuit, Figure 5)
175ns Q rr Reverse Recovery Charge 0.6μC I RRM
Reverse Recovery Current
7.5
A
Symbol Parameter
Test Conditions
Min.Typ.
Max.
Unit BV GSO Gate-Source Breakdown Voltage
Igs=± 1mA (Open Drain)25
V αT Voltage Thermal Coefficient T=25°C Note(3) 1.310-4/°C Rz
Dynamic Resistance
I D = 50 mA, V GS = 0
90?
STP3NC70Z/STP3NC70ZFP
4/10
Safe Operating Area for TO-220
STP3NC70Z/STP3NC70ZFP Gate Charge vs Gate-source Voltage
5/10
STP3NC70Z/STP3NC70ZFP
Source-drain Diode Forward Characteristics
6/10
7/10
STP3NC70Z/STP3NC70ZFP
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 1:
Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For
Resistive Load
STP3NC70Z/STP3NC70ZFP
8/10
STP3NC70Z/STP3NC70ZFP
9/10
STP3NC70Z/STP3NC70ZFP
10/10Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
? 2000 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
https://www.wendangku.net/doc/7a5623250.html,