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SPARC - Wikipedia, the free encyclopedia

SPARC

Designer

Sun Microsystems (acquired by Oracle Corporation)

Bits

64-bit (32 → 64)

Introduced 1987 (shipments)Version V9 (1993)Design RISC

Type Register-Register Encoding

Fixed

Branching Condition code Endianness Bi (Big → Bi)Page size 8 KiB

Extensions VIS 1.0, 2.0, 3.0Open

Yes

Registers

General purpose 31 (G0 = 0; non-global registers use register windows)

Floating point

32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)

Sun UltraSPARC II Microprocessor

SPARC

From Wikipedia, the free encyclopedia

SPARC (from "s calable p rocessor arc hitecture") is a RISC instruction set architecture (ISA)developed by Sun Microsystems and introduced in mid-1987.

SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Implementations of the original 32-bit SPARC architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems

based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMP and CC-NUMA servers produced by Sun Microsystems, Solbourne and Fujitsu, among others, and designed for 64-bit operation.

SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments,Atmel, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

In March 2006 the complete design of Sun Microsystems' UltraSPARC T1 microprocessor was

released in open-source form at https://www.wendangku.net/doc/874814825.html, (https://www.wendangku.net/doc/874814825.html,/about.html) and named the OpenSPARC T1. In 2007 the design of Sun's UltraSPARC T2 microprocessor was also released in open-source form as OpenSPARC T2.[1]

The most recent commercial iterations of the SPARC processor design are the Fujitsu

Laboratories Ltd.'s "Venus" 128 GFLOP SPARC64 VIIIfx introduced June 2009, which is used in the 8 petaFLOPS Japanese supercomputer "K computer", and the SPARC T4 introduced by Oracle Corporation in September 2011; both are 8 core devices running at 2.0 GHz and over 2.5 GHz respectively.

SPARC64 X was introduced in August 2012.[2]

Contents

1 Features

2 History

3 SPARC microprocessor specifications

4 Operating system support

5 Open source implementations

6 Supercomputers

7 See also

8 References

9 External links

Features

The SPARC architecture was heavily influenced by the earlier RISC designs including the RISC I and II from the University of

California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS

architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 160 general purpose registers. At any point, only 32 of them are immediately visible to software - 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return,this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the

adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.[3][4] 64-bit (addressing and data) were added to the version 9 SPARC specification published in 1994.[5]

In SPARC Version 8, the floating point register file has 16 double precision registers. Each of them can be used as two single

precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers.

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently

little-endian devices, such as those on PCI buses.

History

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to

128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC

Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, IV+ as well as CMT extensions starting with the UltraSPARC T1 implementation:

the VIS 1 and VIS 2 instruction set extensions and the associated GSR register

multiple levels of global registers, controlled by the GL register

Sun’s 64-bit MMU architecture

privileged instructions ALLCLEAN, OTHERW, NORMALW, and INVALW

access to the VER register is now hyperprivileged

the SIR instruction is now hyperprivileged

UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification.

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

In August, 2012, Oracle Corporation made available a new specification, Oracle SPARC Architecture 2011, which besides the overall update of the reference, adds the VIS 3 instructions set extensions to 2007 specification.[6]

The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

The SPARC architecture has been licensed to many companies who have developed and fabricated implementations such as:

Afara Websystems

Bipolar Integrated Technology (BIT) C-Cube

Cypress Semiconductor

Elbrus

Fujitsu and Fujitsu Microelectronics HAL Computer Systems

Hyundai

LSI Logic

Magnum Semiconductor

Meiko Scientific

Metaflow Technologies

Prisma

Ross Technology

Parsé Semiconductor Co.

Scientific Atlanta

Solbourne Computer

Weitek

SPARC microprocessor specifications

This table contains specifications for certain SPARC processors: frequency (megahertz), architecture version, release year, number of threads (threads per core multiplied by the number of cores), fabrication process (micrometers), number of transistors (millions), die size (square millimetres), number of I/O pins, dissipated power (watts), voltage, and cache sizes—data, instruction, L2 and L3 (kibibytes).

Name (codename)Model Frequency

(MHz)

Arch.

version

Year Total

threads[note 1]

Process

(μm)

Transistors

(millions)

Die

size

(mm2)

Pins

Power

(W)

Voltage

(V)

SPARC (various),

including

MB86900[note 2]

14.28–40V71987–19921×1=10.8–1.3~0.1–1.8--

160–

256

----

microSPARC I

(Tsunami)

TI TMS390S1040–50V819921×1=10.80.8225?288 2.55

SuperSPARC I (Viking)TI TMX390Z50 /

Sun STP1020

33–60V819921×1=10.8 3.1--29314.35

SPARClite Fujitsu

MB8683x66–108V8E19921×1=1------

144,

176--

2.5/

3.3V-

5.0V,

2.5V-

3.3V

hyperSPARC

(Colorado 1)

Ross RT620A40–90V819931×1=10.5 1.5------5?

microSPARC II (Swift)Fujitsu

MB86904 / Sun

STP1012

60–125V819941×1=10.5 2.32333215 3.3

hyperSPARC

(Colorado 2)

Ross RT620B90–125V819941×1=10.4 1.5------ 3.3 SuperSPARC II

(Voyager)

Sun STP102175–90V819941×1=10.8 3.1299--16--hyperSPARC

(Colorado 3)

Ross RT620C125–166V819951×1=10.35 1.5------ 3.3

TurboSPARC Fujitsu

MB86907

160–180V819961×1=10.35 3.01324167 3.5

UltraSPARC

(Spitfire)

Sun STP1030143–167V919951×1=10.47 3.831552130[note 3]3.3 UltraSPARC

(Hornet)

Sun STP1030200V919981×1=10.42 5.2265521-- 3.3 hyperSPARC

(Colorado 4)

Ross RT620D180–200V819961×1=10.35 1.7------ 3.3 SPARC64Fujitsu (HAL)101–118V919951×1=10.4--Multichip28650 3.8 SPARC64 II Fujitsu (HAL)141–161V919961×1=10.35--Multichip28664 3.3

SPARC64 III Fujitsu (HAL)

MBCS70301

250–330V919981×1=10.2417.6240---- 2.5

UltraSPARC

IIs

(Blackbird)

Sun STP1031250–400V919971×1=10.35 5.414952125[note 4]2.5 UltraSPARC

IIs (Sapphire-Black)Sun STP1032 /

STP1034

360–480V919991×1=10.25 5.412652121[note 5]1.9

UltraSPARC

IIi (Sabre)

Sun SME1040270–360V919971×1=10.35 5.415658721 1.9 UltraSPARC

IIi

(Sapphire-

Red)

Sun SME1430333–480V919981×1=10.25 5.4--58721[note 6]1.9

UltraSPARC

IIe

(Hummingbird)

Sun SME1701400–500V919991×1=10.18 Al----37013[note 7]1.5-1.7

UltraSPARC

IIi (IIe+)

(Phantom)

Sun SME1532550–650V920001×1=10.18 Cu----37017.6 1.7

SPARC64 GP Fujitsu

SFCB81147

400–563V920001×1=10.1830.2217---- 1.8 SPARC64 GP--600–810V9--1×1=10.1530.2------ 1.5

SPARC64 IV Fujitsu

MBCS80523

450–810V920001×1=10.13----------

UltraSPARC

III (Cheetah)

Sun SME1050600V9 / JPS120011×1=10.18 Al29330136853 1.6 UltraSPARC

III (Cheetah)

Sun SME1052750–900V9 / JPS120011×1=10.13 Al29--1368-- 1.6 UltraSPARC

III Cu

(Cheetah+)

Sun SME10561002–1200V9 / JPS120011×1=10.13 Cu29232136880[note 8]1.6

UltraSPARC

IIIi

(Jalape?o)

Sun SME16031064–1593V9 / JPS120031×1=10.1387.520695952 1.3

SPARC64 V

(Zeus)

Fujitsu1100–1350V9 / JPS120031×1=10.1319028926940 1.2

SPARC64 V+

(Olympus-B)

Fujitsu1650–2160V9 / JPS120041×1=10.09400297279651

UltraSPARC IV

(Jaguar)

Sun SME11671050–1350V9 / JPS120041×2=20.13663561368108 1.35

UltraSPARC

IV+ (Panther)

Sun SME1167A1500–2100V9 / JPS120051×2=20.09295336136890 1.1

UltraSPARC T1 (Niagara)Sun SME19051000–1400

V9 / UA

2005

20054×8=320.09300340193372 1.3

SPARC64 VI

(Olympus-C)

Fujitsu2150–2400V9 / JPS120072×2=40.09540422--120--

UltraSPARC T2 (Niagara 2)Sun SME1908A1000–1600

V9 / UA

2007

20078×8=640.065503342183195 1.1–1.5

UltraSPARC T2

Plus (Victoria Falls)Sun SME1910A1200–1600

V9 / UA

2007

20088×8=640.0655033421831--

SPARC64 VII

(Jupiter)[7]

Fujitsu2400–2880V9 / JPS120082×4=80.065600445--150--UltraSPARC

"RK"

(Rock)[8]Sun SME18322300V9 / --canceled[9]2×16=320.065?3962326??

SPARC64

VIIIfx

(Venus)[10][11]

Fujitsu2000V9 / JPS120091x8=80.045760513127158?

SPARC T3

(Rainbow Falls)Oracle/Sun1650

V9 / UA

_?_

20108×16=1280.040[12]????371?139?

SPARC64 VII+

(Jupiter-E or

M3)[13][14]

Fujitsu2667-3000V9 / JPS120102x4=80.065---160-MCST-4R MCST (Russia)750-1000V920101x4=40.09150115-151 SPARC T4

(Yosemite Falls)[15]Oracle2850-3000

V9 /

OSA2011?

20118×8=640.04855403?240?

SPARC64 IXfx[16][17]Fujitsu1850

V9 /

JPS1?

20121x16=160.0418704841442110?

SPARC64 X Fujitsu????-3000V9 / JPS20122x16=320.028*******.51500??

Name (codename)Model

Frequency

(MHz)

Arch.

version

Year

Total

threads[note 1]

Process

(μm)

Transistors

(millions)

Die size

(mm2)

Pins

Power

(W)

Voltage

(V)

Notes:

1. ^ a b Threads per core × number of cores

2. ^ Various SPARC V7 implementations were produced by Fujitsu, LSI Logic, Weitek, Texas Instruments and Cypress. A SPARC V7 processor generally

consisted of several discrete chips, usually comprising an integer unit (IU), a floating-point unit (FPU), a memory management unit (MMU) and cache memory.

3. ^ @167 MHz

4. ^ @250 MHz

5. ^ @400 MHz

6. ^ @440 MHz

7. ^ max@500 MHz

8. ^ @900 MHz

Operating system support

SPARC machines have generally used Sun's SunOS, Solaris or OpenSolaris, but other operating systems such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux have also been used.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,[18] but it was later cancelled.

Open source implementations

Three fully open source implementations of the SPARC architecture exist:

LEON, a 32-bit, SPARC Version 8 implementation, designed especially for space use. Source code is written in VHDL, and licensed under the GPL.

OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses.

Binary programs are licensed under a binary software license agreement.

S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC v9 core capable of 4 way SMT. Like the T1, the source code is licensed under the GPL.

OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses.

Binary programs are licensed under a binary Software License Agreement.

A fully open source simulator for the SPARC architecture also exists:

RAMP Gold (https://www.wendangku.net/doc/874814825.html,/gold) , a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of Systemverilog, and licensed under the BSD licenses. Supercomputers

As of June 2011, only two supercomputers (#1 and #73) using SPARC microprocessors are included in the world's top 500 fastest supercomputers according to the TOP500 list.[19]

Fujitsu's K computer ranked #1 in TOP500 - June 2011 and November 2011 lists. It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the TOP500 at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any other supercomputer system.[19] It also ranked #6 in Green500 - June 2011 list, with a score of 824.56 MFLOPS/W.[20] In the November 2012 release of

TOP500, the K computer ranked #3, using by far the most power of the top three.[21] It ranked #85 on the corresponding Green500 release.[22]

Tianhe-1A (TOP500 #8 as of November 2012[21]) has a number of nodes with FeiTeng-1000 SPARC-based processors developed in China (based on OpenSPARC). However, those processors did not contribute to the LINPACK score.[23][24]

On Dec. 2, 2010, Oracle unveiled the SPARC SuperCluster with T3-2, T3-4 and M5000 servers.[25] The configuration with T3-4 servers was

claimed to surpass the HP Integrity Superdome and the IBM Power 780 server, reaching speeds of 30,249,688 tpmC.[26]

博客的发展及演变

博客的发展及演变学院：历史文化学院专业：文化产业管理班级：1201班姓名：聂康康学号：1205024107

摘要：无论是在国外还是国内，博客和博客文化正以“润物细无声”的方式深刻影响着人们的生活。博客是个人性和公共性的结合体。博客精神的核心并不是自娱自乐，也不仅是个人表达自由，准确地说，博客体现的是一种利他的共享精神，为他人提供帮助。个人日记和个人网站主要表现的还是“小我”，而博客表现的是“大我”。两者也许形式上很接近，但内在有着本质的差异。关键词：博客、互联网博客已经成为互联网文化不可分割的一部分。如今网民几乎都会阅读博客，无论是传统新闻媒介的“官方”新闻博客、与自己爱好兴趣相关的话题性博客或是纯娱乐博客，几乎每一个人都会有一两个特别钟爱的博客。但以前并不是这样。与互联网本身相比，博客的历史并不算长。博客真正兴起并成为互联网风景的重要组成，是在最近五到十年。美国人工智能专家乔恩·巴杰（Jorn Barger）1997年12月在其网站上首次使用了weblog一词；2002年，博客开始引入中国，数量不足1万人；2002年7月，blog的中文“博客”由方兴东、王俊秀正式命名；2002年8月，方兴东、王俊秀开通博客中国（blogchina）

网站；2004年以来，博客主页（weblog或blog）——一种采用简便的软件生成个人主页、能够按照时间顺序不断更新、实现个人信息的历时积累和传播的互联网个人出版方式，在我国进入迅猛发展时期。博客（blogger）概念解释为网络出版（Web Publishing）、发表和张贴（Post-这个字当名词用时就是指张贴的文章）文章，是个急速成长的网络活动，现在甚至出现了一个用来指称这种网络出版和发表文章的专有名词——Weblog或Blog。 Blogger即指撰写Blog的人。Blogger在很多时候也被翻译成为“博客”一词，而撰写Blog这种行为，有时候也被翻译成“博客”。因而，中文“博客”一词，既可作为名词，分别指代两种意思Blog （网志）和Blogger（撰写网志的人），也可作为动词，意思为撰写网志这种行为，只是在不同的场合分别表示不同的意思罢了。 Blog是一个网页，通常由简短且经常更新的帖子（Post，作为动词，表示张贴的意思，作为名字，指张贴的文章）构成，这些帖子一般是按照年份和日期倒序排列的。而作为Blog的内容，它可以是你纯粹个人的想法和心得，包括你对时事新闻、国家大事的个人看法，或者你对一日三餐、服饰打扮的精心料理等，也可以是在基于某一主题的情况下或是在某一共同领域内由一群人集体创作的内容。它并不等同于“网络日记”。作为网络日记是带有很明显的私人性质的，而Blog则是私人性和公共性的有效结合，它绝不仅仅是纯粹个人思想的表达和日常琐事的记录，它所提供的内容可以用来进行交流和为他人提供帮助，是可以包容整个互联网的，具有极高的共享精神和价值。

未来5年所有行业的发展趋势

未来5年所有行业的发展趋势核心：预测未来5年所有16个行业的发展趋势！互联网最有价值的不是自己在产生很多新东西，而是对已有行业的潜力再次挖掘，用互联网的思维去重新提升传统行业。那么从这个角度去观察，互联网影响传统行业的特点有几点：第一，打破信息的不对称性格局，竭尽所能透明一切信息。第二，对产生的大数据进行整合利用，使得资源利用最大化。第三，互联网的群蜂意志拥有自我调节机制。我把人类群体思维模式称之为群蜂意志，你可以想象一个人类群体大脑记忆库的建立：最初的时候各个神经记忆节点的搜索路径是尚未建立的，当我们需要反复使用的时候就慢慢形成强的连接，在互联网诞生之前这些连接记忆节点的路径是微弱的，强连接是极少的，但是互联网出现之后这些路径瞬间全部亮起，所有记忆节点都可以在瞬间连接。这样就给了人类做整体未来决策有了超越以往的前所未有的体系支撑，基于这样的记忆模式，人类将重新改写各个行业，以及人类未来。以下是对各行业的盘点，涉及面较多，有些部分笔者观察尚浅，还望多包涵。 1.零售业传统零售业对于消费者来说最大的弊端在于信息的不对称性。在《无价》

一书中，心理实验表明外行人员对于某个行业的产品定价是心里根本没有底的，只需要抛出锚定价格，消费者就会被乖乖的牵着鼻子走。而C2C,B2C却完全打破这样的格局，将世界变平坦，将一件商品的真正定价变得透明。大大降低了消费者的信息获取成本。让每一个人都知道这件商品的真正价格区间，使得区域性价格垄断不再成为可能，消费者不再蒙在鼓里。不仅如此，电子商务还制造了大量用户评论UGC。这些UGC真正意义上制造了互联网的信任机制。而这种良性循环，是传统零售业不可能拥有的优势。预测未来的零售业, 第一，会变成线下与线上的结合，价格同步。第二，同质化的强调功能性的产品将越来越没有竞争力，而那些拥有一流用户体验的产品会脱引而出。第三，配合互联网大数据，将进行个性化整合推送(现在亚马逊就已经将首页改版为个性化推送主页)。 2.批发业传统批发业有极大的地域限制，一个想在北京开家小礼品店的店主需要大老远的跑到浙江去进货，不仅要面对长途跋涉并且还需要面对信任问题。所以对于进货者来说，每次批发实际上都是一次风险。当阿里的B2B 出现之后，这种风险被降到最低。一方面，小店主不需要长途跋涉去亲自检查货品，只需要让对方邮递样品即可。另一方面，阿里建立的信任问责制度，使得信任的建立不需要数次的见面才能对此人有很可靠的把

谷歌发展史

谷歌发展史 1，谷歌上线公司成立肯定是谷歌搜索历史上最重大的里程碑事件。1997年到1998年间，谷歌联合创始人拉里·佩奇（Larry Page）和谢尔盖·布林（Sergey Brin）开始在美国加州门罗帕克的一间车库内筹备公司。成立数天后，公司注册了https://www.wendangku.net/doc/874814825.html,域名。这项服务背后的概念，也就是“无穷大”（googol）这个单词，显示出公司要用一种建设性的方式，组织万维网上无穷的信息，从而帮助用户找需要的答案。 2，在雅虎的帮助下，踏出成功的第一步

2000年之前，谷歌尚未成为搜索行业的主流。行业领头羊的地位属于1994年成立的老牌搜索引擎雅虎。也正是这家公司用一笔搜索合作交易让谷歌崭露头角——雅虎放弃了Inktomi，通过布林和佩奇的服务支持自己的原生搜索结果。真正有意思的是这桩交易15年后的结果。两家公司最终出现了很多纠纷，其中就涉及到技术专利。2004年时，谷歌与雅虎和解了了专利纠纷，通过雅虎子公司Overture Services，谷歌向雅虎发行了270万股A类普通股。谷歌的广告产品AdWords 由此建立。 3，自助式的盈利搜索模式

在过去，Lycos AskJeeves、Excite等搜索引擎通过直显广告获得收入。这种广告模式在90年代末非常受欢迎，但一段时间后便没人再点击了。搜索公司和广告主遇到了收入难题。谷歌在2000年推出了AdWords产品。这个产品的模式在当时看起来十分新奇——品牌不用再和广告机构沟通广告上的事宜，而可以自行管理，节省了时间、精力与成本。更有吸引力的是，AdWords中有一项个性化的尝试，广告可以按照搜索查询的内容创建，而不再是随机出现。此外，谷歌还使用竞价模式，提高了收入：出价越高，顾客的文字广告的位置就越靠上。雅虎与微软马上效仿这种做法。这种广告在谷歌收入中占比非常大——在2012年广告总营收中是425亿美元。 4，微软加雅虎大于谷歌？由于对谷歌在搜索引擎的统治地位感到不满，雅虎和微软在2010年形成联盟，用微软的技术负责雅虎的搜索算法和付费搜索平台。同时，雅虎也变成了两家公司的“独家合作销售”，向两家公司的付费搜索广告主出售广告。这桩交易影响巨大，需要得到美欧监管机构的批准，而这两地的监管者最终在2010年初放行了这桩交易。合作的效果究竟如何并不是很清楚，但雅虎在2012年4月1日起将合作延长了12个月。不过，当玛丽莎·梅耶尔（Marissa Mayer）执掌雅虎后，她曾表示，这份协议并没有带来承诺的市场份额与营收。雅虎在今年早些时候与谷歌签订了“全球性的、非排他的内容关联广告交易”，证明它还是更喜欢谷歌多一点，也表明微软-雅虎合作正式终结。对不起了，微软。 5，我的网站为什么排名低？

BBS的发展史

什么是BBS？ BBS的英文全称是Bulletin Board System，翻译为中文就是“电子公告板”。BBS最早是用来公布股市价格等类信息的，当时BBS连文件传输的功能都没有，而且只能在苹果计算机上运行。早期的BBS与一般街头和校园内的公告板性质相同，只不过是通过电脑来传播或获得消息而已。一直到个人计算机开始普及之后，有些人尝试将苹果计算机上的BBS转移到个人计算机上，BBS才开始渐渐普及开来。近些年来，由于爱好者们的努力，BBS的功能得到了很大的扩充。目前，通过BBS系统可随时取得各种最新的信息；也可以通过BBS系统来和别人讨论计算机软件、硬件、Internet、多媒体、程序设计以及生物学、医学等等各种有趣的话题；还可以利用BBS系统来发布一些“征友”、“廉价转让”、“招聘人才”及“求职应聘”等启事；更可以召集亲朋好友到聊天室内高谈阔论……这个精彩的天地就在你我的身旁，只要您在一台可以访问校园网的计算机旁，就可以进入这个交流平台，来享用它的种种服务BBS 维基百科，自由的百科全书 BBS是电子公告板系统(Bulletin Board System)之英文缩写，它通过在计算机上运行服务软件，允许用户使用终端程序通过电话调制解调器拨号或者Internet来进行连接，执行下载数据或程序、上传数据、阅读新闻、与其它用户交换消息等功能。许多BBS由站长(通常被称为SYSOP-SYStem OPerator)业余维护，而另一些则提供收费服务。目前，有的时候BBS也泛指网络论坛或网络社群。目录 [隐藏] * 1 BBS技术及常见软件 * 2 BBS人文文化 o 2.1 中国大陆BBS“系统维护”现象 o 2.2 BBS用语 * 3 参看 * 4 外部链接 [编辑] BBS技术及常见软件因特网（Internet）之前，在20世纪80年代中叶就开始出现基于调制解调器（modem）和电话线通信的拨号BBS及其相互连接而成的BBS网络。后来随着因特网的普及，拨号BBS和BBS网络已经日渐凋零，所剩无几。目前的BBS站点，多数是基于Internet的Telnet协议。在服务器端，采用Maple BBS或者FireBird BBS 系统。用户端通过Telnet软件如NetTerm、CTerm、FTerm等来登陆服务器，阅读发表文

搜索引擎发展历史

搜索引擎成为互联网的重要应用之一 ??? 从90年代末开始，互联网上的网站与网页数量飞速增长，网民的兴趣点也从屈指可数的几家综合门户类网站分散到特色各异的中小网站去了。人们想在互联网上找到五花八门的信息，但由于人工分类编辑网站目录的方法受到时效和收录量的限制，无法再满足人们对网上内容的检索需求，于是搜索引擎在2000年后开始大行其道。使用蜘蛛程序在互联网上自动抓取海量网页信息，索引并存储到庞大的数据库中，并通过特殊算法将相关性最好的结果瞬间呈现给搜索者，搜索引擎的便捷使其成为互联网最受欢迎的应用之一。以至于有相当多的人将浏览器的默认首页设为搜索引擎，甚至形成了将网站名称输入到搜索框中而非浏览器地址栏这样独特的网络导航习惯。呼叫目录返回顶部搜索成为人们思考行为的一部分 ??? 随着网上社区（SNS），博客（Blog），维基百科（Wikipedia）等如火如荼的发展，网民从单纯的信息获取者演变成信息发布者，人们通过网络分享自己的知识、体验、情感或见闻，使互联网上的内容越来越丰富多彩。例如，按照统计，目前中国网民在百度知道平台上的问题解决率高达97.9%，这些问题涉及科技、社会、文化、商业等各个方面，尤其对人们的衣食住行等日常生活问题，几乎都能从平台获得满意的答案。截至到09年7月的4年时间内，中文互动问答平台百度知道已经累计为中国网民解决了5650多万个问题，成为人们日常生活的最佳互动问答平台。社区内容上的无所不谈使搜索引擎的收录也变得无所不包，人们发现通过搜索引擎可以找到他想要的任何信息，从新闻热点到柴米油盐，从育儿百科到MBA课程。信息的便捷获取潜移默化的改变了人们的思考行为，搜索结果页上汇集了整个互联网的智慧，谁不想在苦思冥想前“搜索一下”呢？呼叫目录返回顶部搜索成为人们消费行为的重要环节 ??? 随着对搜索引擎的依赖加深，当人们有消费需求或看到感兴趣的商品时，“搜索一下”已经是已形成的“条件反射”。以前，消费者依靠“货比三家”来对抗“买的没有卖的精”这种与商家之间的信息不对称。现在，通过搜索引擎收集到的产品功能与使用情况弥补了消费者与推广商家间在知情权上的鸿沟，成为消费决策的重要依据。价格低的线上销售渠道也成为搜索热点，以至于现在出现了消费者为省钱而先到实体专卖店挑选合适型号大小货品再到网店付款下单的有趣现象。随着年轻一代消费能力的提高，从前仅限于图书音像和电子产品的网上购物正在向工作生活的各个层面迅速渗透，服装食品等日用消费品也逐渐成为网购的宠儿。呼叫目录返回顶部搜索营销原理原理介绍 ????传统营销需要选择目标市场，通过创造、传递、传播优质的客户价值，获得、保持和发展优质客户。而在互联网时代，网站由于其内容丰富、查阅方便、不受时空限制、成本低等优势，广受网民和商家的喜爱，成为传递、传播价值的主要手段，并在获得、保持和发展客户方面呈现强大的潜力。所以，围绕网站的营销活动越来越丰富。