EDA期末考试题06(最新整理)

SEL

00

01

10

11 OTHERS

COUT A or B A xor B A and B A nor B “XX”

五、阅读下列 VHDL 程序，画出相应ＲＴＬ图：（10 分）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY three IS

PORT

(

clk,d : IN STD_LOGIC;

dout : OUT STD_LOGIC );

END;

ARCHITECTURE bhv OF three IS

SIGNAL tmp: STD_LOGIC;

BEGIN

P1: PROCESS(clk)

BEGIN

IF rising_edge(clk) THEN

Tmp <= d;

dout <= tmp;

END IF;

END PROCESS P1;

END bhv;

六、写 VHDL 程序：（20 分）

1.数据选择器MUX,其系统模块图和功能表如下图所示。试采用下面四种方式中的两种来描述该数据选择器MUX 的结构体。

SEL(1:0)

(a) 用if 语句。(b) 用case 语句。(c) 用when else 语句。(d) 用with select 语句。

Library ieee;

Use ieee.std_logic_1164.all;

Entity mymux is

Port ( sel : in std_logic_vector(1 downto 0); -- 选择信号输入Ain, Bin : in std_logic_vector(1 downto 0); -- 数据输入

Cout : out std_logic_vector(1 downto 0) );

End mymux;

Architecture one of mymux is

Begin

Process (sel, ain, bin)

Begin

If sel = “00” then cout <= ain or bin;

Elsif sel = “01” then cout <= ain xor bin;

Elsif sel = “10” then cout <= ain and bin;

Else cout <= ain nor bin;

End if;

End process;

End one;

Architecture two of mymux is

Begin

Process (sel, ain, bin)

Begin

Case sel is

when “00” => cout <= ain or bin;

when “01” => cout <= ain xor bin;

when “10” => cout <= ain and bin;

when others => cout <= ain nor bin;

End case;

End process;

End two;

2.看下面原理图，写出相应VHDL 描述

AIN(1:0)

BIN(1:0) MUX

COUT(1:0)

Library ieee;

Use ieee.std_logic_1164.all;

Entity mycir is

Port (ain , bin , clk : in std_logic;

Cout : out std_logic);

End mycir;

Architecture one of mycir is

Signal tb, tc;

begin

Process (clk) begin

If clk’event and clk = ‘1’ then

tb <= bin;

end if;

End process;

Process (clk, tc) begin

If clk = ‘1’ then cout <= tc;end if;

End process;

Tc <= ain xor tb;

End one;

elev2

cnt100 七、综合题（20 分）

用 VHDL 设计两层升降平台控制器

图 a 是一个两层的升降平台示意图，一层和二层各有一个按钮用来呼叫升降机。

问题 1，请完成 cnt100 模块的 VHDL 设计（实体部分已给出，不用写），参考的仿真波形如图 c 所示。

Architecture one of cnt100 is Begin

Process (clk, en)

图 c cnt100 仿真波形图

图 a 两层升降平台示意图

对应图 a 的升降平台控制器，拟用 VHDL 语言设计一个电路模拟其控制逻辑，图 b 为该 VHDL 电路的设计模块图。

Variable q : std_logic_vector (7 downto 0); Begin

If en = ‘0’ then q := (others => ‘0’);

Elsif clk’event and clk = ‘1’ then q := q + 1; End if;

If q < “01100100” then cout <= ‘0’; Else cout <= ‘1’; End if; End process; End one;

door up down

en

cout

2

2

clk rst

call arr

图 b 两层升降平台控制器设计模块图

图 b 中的 cnt100 模块用来控制升降台开关门延时，elev2 为升降平台状态控制器。升降台闸门由打开到

关闭或由关闭到打开时，elev2 模块向 cnt100 模块输出一个 en 计数使能信号（高电平有效）。cnt100 模块计数溢出（≥100）时 cnt100 输出 cout 信号为高电平，同时 cnt100 计数停止。

cnt100 模块的实体描述如下所示：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT100 IS

PORT ( CLK, EN : IN STD_LOGIC; -- 时钟、使能信号

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问题2，以下是elev2 模块的VHDL 描述：

library ieee;

use ieee.std_logic_1164.all;

entity elev2 is

port ( clk, rst : in std_logic; -- 时钟、复位信号

cout : in std_logic; -- 定时溢出信号

call : in std_logic_vector(2 downto 1); -- 呼叫信号

arr : in std_logic_vector(2 downto 1); -- 到达信号

door : out std_logic; -- 门控信号，低电平开门

up : out std_logic; -- 上升信号

down : out std_logic; -- 下降信号

en : out std_logic); -- 延时计数清零、使能信号

请根据elev2 的VHDL 描述画出其状态迁移图。

end elev2;

architecture behav of elev2 is

constant CL1 : std_logic_vector(2 downto 0) := "000";-- 一楼关门

constant OP1 : std_logic_vector(2 downto 0) := "100";-- 一楼开门

constant UP1 : std_logic_vector(2 downto 0) := "010";-- 一楼上升

constant DN2 : std_logic_vector(2 downto 0) := "001";-- 二楼下降

constant CL2 : std_logic_vector(2 downto 0) := "011";-- 二楼关门

constant OP2 : std_logic_vector(2 downto 0) := "111";-- 二楼开门

signal control : std_logic_vector(2 downto 0); -- 状态控制信号

begin

door <= not control(2); up <= control(1); down <= control(0);

process (clk, rst, arr, call)

variable ven : std_logic;

begin

if rst = '1' then control <= CL1;

elsif clk'event and clk = '1' then

case control is

when CL1 => if cout = '1' then -- 关门已完毕

if call(1) = '1' then control <= OP1; en <= '0';

elsif call(2) = '1' then control <= UP1; en <= '1';

else control <= CL1; en <= '1'; end if;

else control <= CL1; en <= '1'; end if;

when OP1 => if cout = '1' then -- 开门已完毕

if call(1) = '1' then control <= OP1; en <= '1';

else control <= CL1; en <= '0'; end if;

else control <= OP1; en <= '1'; end if;

when UP1 => if arr(2) = '1' then control <= CL2;

else control <= UP1; end if;

when DN2 => if arr(1) = '1' then control <= CL1;

else control <= DN2; end if;

when CL2 => if cout = '1' then -- 关门已完毕

if call(2) = '1' then control <= OP2; en <= '0';

elsif call(1) = '1' then control <= DN2; en <= '1';

else control <= CL2; en <= '1'; end if;

else control <= CL2; en <= '1'; end if;

when OP2 => if cout = '1' then -- 开门已完毕

if call(2) = '1' then control <= OP2; en <= '1';

else control <= CL2; en <= '0'; end if;

else control <= OP2; en <= '1'; end if;

when others => if arr(10 = ‘1’ then control <=CL1;

else control <= CL2;end if; 问题3，根据图b 所示升降平台模块图，写出升降平台控制器ELEV_TOP 的VHDL 顶层描述：Library ieee;

Use ieee.std_logic_1164.all;

Entity elev is

Port (clk, rst : in std_logic;

Call, arr : in std_logic_vector(2 downto 1);

Door, up, down : out std_logic );

End elev;

Architecture one of elev is

component CNT100

PORT ( CLK, EN : IN STD_LOGIC; -- 时钟、使能信号

COUT : OUT STD_LOGIC ); -- 溢出信号

END component;

component elev2 is

port ( clk, rst : in std_logic; -- 时钟、复位信号

cout : in std_logic; -- 定时溢出信号

call : in std_logic_vector(2 downto 1); -- 呼叫信号

arr : in std_logic_vector(2 downto 1); -- 到达信号

door : out std_logic; -- 门控信号，低电平开门

up : out std_logic; -- 上升信号

down : out std_logic; -- 下降信号

en : out std_logic); -- 延时计数清零、使能信号

end component;

signal ena, cout : std_logic;

begin

u1 : cnt100 port map (clk, ena, cout);

u2 : elev2 port map (clk, rst, cout, call, arr, door, up, down, ena);

end one;

end case; end if;

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At the end, Xiao Bian gives you a passage. Minand once said, "people who learn to learn are very happy people.". In every wonderful life, learning is an eternal theme. As a professional clerical and teaching position, I understand the importance of continuous learning, "life is diligent, nothing can be gained", only continuous learning can achieve better self. Only by constantly learning and mastering the latest relevant knowledge, can employees from all walks of life keep up with the pace of enterprise development and innovate to meet the needs of the market. This document is also edited by my studio professionals, there may be errors in the document, if there are errors, please correct, thank you!