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MT4LC8M8B6TG-5S中文资料

FEATURES

?Single +3.3V ±0.3V power supply

?Industry-standard x8 pinout, timing, functions,and packages

?13 row, 10 column addresses (E1) or 12 row, 11 column addresses (B6)

?High-performance CMOS silicon-gate process ?All inputs, outputs and clocks are LVTTL-compatible

?FAST PAGE MODE (FPM) access

?4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms

?Optional self refresh (S) for low-power data retention

OPTIONS

MARKING

?Refresh Addressing 4,096 (4K) rows B68,192 (8K) rows E1?Plastic Packages

32-pin SOJ (400 mil)DJ 32-pin TSOP (400 mil)TG ?Timing 50ns access -560ns access

-6?Refresh Rates

Standard Refresh (64ms period)None Self Refresh (128ms period)

NOTE: 1.The 8 Meg x 8 FPM DRAM base number

differentiates the offerings in one place—MT4LC8M8E1. The fifth field distinguishes

various options: E1 designates an 8K refresh and B6 designates a 4K refresh for FPM DRAMs.2.The # symbol indicates signal is active LOW.*Contact factory for availability

Part Number Example:

MT4LC8M8E1DJ-5

DRAM

MT4LC8M8E1, MT4LC8M8B6

For the latest data sheet, please refer to the Micron Web site: https://www.wendangku.net/doc/886781142.html,/products/datasheets/dramds.html

8 MEG x 8 FPM DRAM PART NUMBERS

x = speed

KEY TIMING PARAMETERS

GENERAL DESCRIPTION

The 8 Meg x 8 DRAMs are high-speed CMOS, dy-namic random-access memory devices containing 67,108,864 bits organized in a x8 configuration. The 8 Meg x 8 DRAMs are functionally organized as 8,388,608locations containing eight bits each. The 8,388,608memory locations are arranged in 8,192 rows by 1,024columns for the MT4LC8M8E1 or 4,096 rows by 2,048columns for the MT4LC8M8B6. During READ or WRITE cycles, each location is uniquely addressed via the address bits. First, the row address is latched by the

FUNCTIONAL BLOCK DIAGRAM MT4LC8M8E1 (13 row addresses)

FUNCTIONAL BLOCK DIAGRAM MT4LC8M8B6 (12 row addresses)

A0-A12

RAS#

V SS

WE#CAS#

OE#

DQ0-DQ7

A0-A11

RAS#

V SS

WE#CAS#

OE#

DQ0-DQ7

RAS# signal, then the column address by CAS#. Both devices provide FAST-PAGE-MODE operation, allow-ing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row.

The MT4LC8M8E1 and MT4LC8M8B6 must be re-freshed periodically in order to retain stored data. FAST PAGE MODE ACCESS

Each location in the DRAM is uniquely addressable as mentioned in the General Description. The data for each location is accessed via the eight I/O pins (DQ0-DQ7). The WE# signal must be activated to execute a WRITE operation; otherwise, a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary.

FAST-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the FAST-PAGE-MODE opera-tion.

DRAM REFRESH

The supply voltage must be maintained at the speci-fied levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all 8,192 rows (E1) or all 4,096 rows (B6) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC8M8E1 in-ternally refreshes two rows for every CBR cycle, whereas the MT4LC8M8B6 refreshes one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# address-ing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method only one row is refreshed at a time; so for the MT4LC8M8E1, 8,192 RAS#-ONLY REFRESH cycles must be executed every 64ms to cover all rows. Some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device.

An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified t RASS. The “S” option allows for an extended refresh period of 128ms, or 31.25μs per row for a 4K refresh and 15.625μs per row for an 8K refresh when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode.

The self refresh mode is terminated by driving RAS# HIGH for a minimum time of t RPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM con-troller utilizes RAS#-ONLY or burst CBR refresh se-quence, all rows must be refreshed with a refresh rate of t RC minimum prior to the resumption of normal operation.

STANDBY

Returning RAS# and CAS# H IGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.

GENERAL DESCRIPTION (continued)

ABSOLUTE MAXIMUM RATINGS*

Voltage on V CC Relative to V SS................-1V to +4.6V Voltage on NC, Inputs or I/O Pins

Relative to V SS.......................................-1V to +4.6V Operating Temperature, T A (ambient)...0°C to +70°C Storage Temperature (plastic)............-55°C to +150°C Power Dissipation...................................................1W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (V CC = +3.3V ±0.3V)

I CC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6) (V CC = +3.3V ±0.3V)

CAPACITANCE

(Note: 2)

AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (V CC = +3.3V ±0.3V)

NOTES

1.All voltages referenced to V SS.

2.This parameter is sampled. V CC = +

3.3V; f = 1

MHz.

3.I CC is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time and the outputs open.

4.Enables on-chip refresh and address counters.

5.The minimum specifications are used only to

indicate cycle time at which proper operation

over the full temperature range is ensured.

6.An initial pause of 100μs is required after power-

up, followed by eight RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the t REF

refresh requirement is exceeded.

7.AC characteristics assume t T = 5ns.

8.V IH (MIN) and V IL (MAX) are reference levels for

measuring timing of input signals. Transition

times are measured between V IH and V IL (or

between V IL and V IH).

9.In addition to meeting the transition rate

specification, all input signals must transit

between V IH and V IL (or between V IL and V IH) in a monotonic manner.

10.If CAS# = V IH, data output is High-Z.

11.If CAS# = V IL, data output may contain data from

the last valid READ cycle.

12.Measured with a load equivalent to two TTL

gates, 100pF and V OL = 0.8V and V OH = 2V.

13.If CAS# is LOW at the falling edge of RAS#,

output data will be maintained from the previous cycle. To initiate a new cycle and clear the data-

out buffer, CAS# must be pulsed HIGH for t CP. 14.The t RCD (MAX) limit is no longer specified.

t RCD (MAX) was specified as a reference point

only. If t RCD was greater than the specified t RCD (MAX) limit, then access time was controlled

exclusively by t CAC (t RAC [MIN] no longer

applied). With or without the t RCD limit, t AA

and t CAC must always be met.

15.The t RAD (MAX) limit is no longer specified.

t RAD (MAX) was specified as a reference point

only. If t RAD was greater than the specified t RAD (MAX) limit, then access time was controlled

exclusively by t AA (t RAC and t CAC no longer

applied). With or without the t RAD (MAX) limit, t AA, t RAC and, t CAC must always be met.

16.Either t RCH or t RRH must be satisfied for a READ

cycle.

17.t OFF (MAX) defines the time at which the output

achieves the open circuit condition and is not

referenced to V OH or V OL.18.t WCS, t RWD, t AWD,and t CWD are not restrictive

operating parameters. t WCS applies to EARLY

WRITE cycles.If t WCS> t WCS MIN,the cycle is an EARLY WRITE cycle and the data output will

remain an open circuit throughout the entire

cycle. t RWD, t AWD and t CWD define READ-

MODIFY-WRITE cycles.Meeting these limits

allows for reading and disabling output data and

then applying input data.The values shown were calculated for reference allowing10ns for the

external latching of read data and application of

write data.OE#held HIGH and WE#taken LOW

after CAS#goes LOW result in a LATE WRITE

(OE#-controlled)cycle. t WCS, t RWD, t CWD and

t AWD are not applicable in a LATE WRITE cycle.

19.These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20.If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not

possible.

21.A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# = LOW and

OE# = HIGH.

22.RAS#-ONLY REFRESH requires that all 8,192 rows

of the MT4LC8M8E1 or all 4,096 rows of the

MT4LC8M8B6 be refreshed at least once every

64ms. CBR REFRESH for either device requires

that at least 4,096 cycles be completed every

64ms.

23.The DQs open during READ cycles once t OD or

t OFF occurs. If CAS# goes HIGH before OE#, the

DQs will open regardless of the state of OE#. If

CAS# stays LOW while OE# is brought HIGH, the DQs will open. If OE# is brought back LOW

(CAS# still LOW), the DQs will provide the

previously read data.

https://www.wendangku.net/doc/886781142.html,TE WRITE and READ-MODIFY-WRITE cycles

must have both t OD and t OEH met (OE# HIGH

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE

cycle. If OE# is taken back LOW while CAS#

remains LOW, the DQs will remain open.

25.Column address changed once each cycle.

26.V IH overshoot: V IH (MAX) = V CC + 2V for a pulse

width ￡ 10ns, and the pulse width cannot be

greater than one third of the cycle rate. V IL

undershoot: V IL (MIN) = -2V for a pulse width ￡

10ns, and the pulse width cannot be greater than one third of the cycle rate.

READ CYCLE

RAS#

CAS#

ADDR

DQ WE#

TIMING PARAMETERS

EARLY WRITE CYCLE

TIMING PARAMETERS

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

OE#

TIMING PARAMETERS

FAST-PAGE-MODE READ CYCLE

CAS#

ADDR

WE#

OE#

TIMING PARAMETERS

FAST-PAGE-MODE EARLY WRITE CYCLE

CAS#

ADDR

WE#

DQ RAS#

OE#

TIMING PARAMETERS

OE#

WE#

FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)

NOTE: 1.t PC is for LATE WRITE only.

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

CAS#

ADDR

RAS#

WE#

NOTE: 1.Do not drive input data prior to output data going High-Z.

TIMING PARAMETERS

RAS#

CAS#

WE#

RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON ’

T CARE)

CAS#

ADDR

RAS#

DQ CBR REFRESH CYCLE

(Addresses and OE# = DON ’T CARE)

TIMING PARAMETERS

NOTE: 1.End of CBR REFRESH cycle.

HIDDEN REFRESH CYCLE 1(WE# = HIGH; OE# = LOW)

DQ ADDR

CAS#

RAS#

OE#

TIMING PARAMETERS

NOTE: 1.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH.

SELF REFRESH CYCLE

(Addresses and OE# = DON ’T CARE)

RAS#

CAS#

WE#

NOTE 1

NOTE: 1.Once t RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.

2.Once t RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR is used.

TIMING PARAMETERS

32-PIN PLASTIC SOJ (400 mil)

NOTE: 1.All dimensions in inches (millimeters)MAX or typical where noted.

MIN

2.Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.

32-PIN PLASTIC TSOP (400 mil)

0.50 ±0.10

DETAIL A

NOTE: 1.All dimensions in millimeters MAX or typical where noted.

MIN

2.Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side.

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