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OV7725 datasheet

? 2006 OmniVision Technologies, Inc.

VarioPixel, OmniVision, and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc.

Version 1.0, September 12, 2006

OmniPixel2 and CameraChip are trademarks of OmniVision Technologies, Inc.

These specifications are subject to change without notice.

Advanced Information Preliminary Datasheet

OV7725 Color CMOS VGA (640x480) C AMERA C HIP TM Sensor

O mni

ision

with OmniPixel2TM Technology

General Description

The OV7725 C AMERA C HIP ? image sensor is a low voltage CMOS device that provides the full functionality of a single-chip VGA camera and image processor in a small footprint package. The OV7725 provides full-frame,sub-sampled or windowed 8-bit/10-bit images in a wide range of formats, controlled through the Serial Camera

Applications

?Cellular and picture phones ?Toys

?PC Multimedia

Digital still cameras

Key Specifications

OV7725Color CMOS VGA OmniPixel2?C AMERA C HIP? Sensor O

Functional Description

Figure2 shows the functional block diagram of the OV7725 image sensor. The OV7725 includes:

?Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode)

?Analog Signal Processor

?A/D Converters

?Test Pattern Generator

?Digital Signal Processor (DSP)

?Image Scaler

?Timing Generator

2Proprietary to OmniVision Technologies, Inc.Version 1.0, September 12, 2006

Functional Description

Version 1.0, September 12, 2006Proprietary to OmniVision Technologies, Inc.3

Image Sensor Array

The OV7725 sensor has an image array of 656x 488pixels for a total of 320,128 pixels, of which 640x 480pixels are active (307,200 pixels). Figure 3 shows a cross-section of the image sensor array.

Figure 3 Image Sensor Array

In addition to the A/D conversion, this block also has the following functions:?Digital Black-Level Calibration (BLC)?Optional U/V channel delay ?Additional A/D range controls

In general, the combination of the A/D Range Multiplier and A/D Range Control sets the A/D range and maximum value to allow the user to adjust the final image brightness as a function of the individual application.

Test Pattern Generator

OL /I OH drive current

the C AMERA C HIP sensor operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB)Specification for detailed usage of the serial control port.

Proprietary to OmniVision Technologies, Inc.

Version 1.0, September 12, 2006

OV7725

Color CMOS VGA OmniPixel2? C AMERA C HIP ? Sensor

Pin Description

Table 1

Pin Description

Pin Number

Name Pin Type Function/Description

A1ADVDD Power ADC power supply

A2RSTB Input System reset input, active low

A3VREFH Reference Reference voltage - connect to ground using a 0.1 μF capacitor A4FSIN Input Frame synchronize input A5SCL Input SCCB serial interface clock input A6D0a a. D[9:0] for 10-bit Raw RGB data (D[9] MSB, D[0] LSB)Output Data output bit[0]B1ADGND Power ADC ground

B2VREFN Reference Reference voltage - connect to ground using a 0.1 μF capacitor B3AVDD Power Analog power supply B4AGND Power Analog ground

B5SDA I/O SCCB serial interface data I/O B6HREF Output HREF output

C1PWDN Input (0)b b. Input (0) represents an internal pull-down resistor.

Power Down Mode Selection

0:Normal mode

1:Power down mode C6VSYNC Output Vertical sync output D1D5Output Data output bit[5]D6D4Output Data output bit[4]E1D7Output Data output bit[7]E2D1Output Data output bit[1]

E3DVDD Power Power supply (+1.8 VDC) for digital logic core E4PCLK Output Pixel clock output

E5DOVDD Power Digital power supply for I/O (1.7V ~ 3.3V)E6D6Output Data output bit[6]F1D9c c. D[9:2] for 8-bit YUV or RGB565/RGB555 (D[9] MSB, D[2] LSB)

Output Data output bit[9]F2D3Output Data output bit[3]F3XCLK Input System clock input F4DOGND Power Digital ground F5D2Output Data output bit[2]F6

Output

Data output bit[8]

Electrical Characteristics

Version 1.0, September 12, 2006

Proprietary to OmniVision Technologies, Inc.

Electrical Characteristics

NOTE:

Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage.

Table 2

Operating Conditions

Parameter

Min Max Operating temperature -20°C +70°C Storage temperature a a.

Exceeding the stresses listed may permanently damage the device. This is a stress rating only and functional operation of the sensor at these and any other condition above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions for any extended period may affect reliability.

-40°C

+125°C

Table 3 Absolute Maximum Ratings

Ambient Storage Temperature

-40oC to +95oC

Supply Voltages (with respect to Ground)

V DD-A

4.5 V V DD-C 3 V V DD-IO

4.5 V

All Input/Output Voltages (with respect to Ground)-0.3V to V DD-IO +0.5V Lead-free Temperature, Surface-mount process 245oC

Table 4

DC Characteristics (-20°C < T A < 70°C)

Symbol Parameter

Condition

Min Typ Max Unit V DD-A DC supply voltage – Analog – 3.0 3.3 3.6V V DD-C DC supply voltage – Digital Core – 1.62 1.8 1.98V V DD-IO DC supply voltage – I/O power – 2.5

– 3.3

V I DDA Active (Operating) Current See Note a a. V DD-A = 3.3V, V DD-C = 1.8V, V DD-IO = 3.3V

I DDA = ∑{I DD-IO + I DD-C + I DD-A }, f CLK = 24MHz at 30 fps YUV output, no I/O loading 10 + 8b

b. I DD-C = 10mA, I DD-A = 8mA, without loading mA I DDS-SCCB Standby Current See Note c

c. V DD-A = 3.3V, V DD-C = 1.8V, V DD-IO = 3.3V

I DDS-SCCB refers to a SCCB-initiated Standby, while I DDS-PWDN refers to a PWDN pin-initiated Standby 1mA I DDS-PWDN Standby Current 10

20μA V IH Input voltage HIGH CMOS

0.7 x V DD-IO

V V IL Input voltage LOW 0.3 x V DD-IO

V V OH Output voltage HIGH CMOS

0.9 x V DD-IO

V V OL Output voltage LOW 0.1 x V DD-IO

V I OH Output current HIGH See Note d

d. Standard Output Loading = 25pF, 1.2K Ω8mA I OL Output current LOW 15

mA I L

Input/Output Leakage

GND to V DD-IO ± 1

μA

OV7725Color CMOS VGA OmniPixel2?C AMERA C HIP? Sensor O

Table 5 Functional and AC Characteristics (-20°C < T A < 70°C)

Symbol Parameter Min Typ Max Unit Functional Characteristics

A/D Differential Non-Linearity+ 1/2LSB

A/D Integral Non-Linearity+1LSB

AGC Range30dB

Red/Blue Adjustment Range12dB Inputs (PWDN, CLK, RESET#)

f CLK Input Clock Frequency102448MHz

t CLK Input Clock Period2142100ns t CLK:DC Clock Duty Cycle455055% t S:RESET Setting time after software/hardware reset1ms t S:REG Settling time for register change (10 frames required)300ms SCCB Timing (see Figure4)

f SCL Clock Frequency400KHz

t LOW Clock Low Period 1.3μs t HIGH Clock High Period600ns t AA SCL low to Data Out valid100900ns t BUF Bus free time before new START 1.3μs t HD:STA START condition Hold time600ns t SU:STA START condition Setup time600ns t HD:DAT Data-in Hold time0μs t SU:DAT Data-in Setup time100ns t SU:STO STOP condition Setup time600ns t R, t F SCCB Rise/Fall times300ns t DH Data-out Hold time50ns Outputs (VSYNC, HREF, PCLK, and D[9:0] (see Figure5, Figure6, Figure7, and Figure8)

t PDV PCLK[↓] to Data-out Valid5ns t SU D[9:0] Setup time15ns t HD D[9:0] Hold time8ns t PHH PCLK[↓] to HREF[↑]05ns t PHL PCLK[↓] to HREF[↓]05ns

AC Conditions:? V DD: V DD-C = 1.8V, V DD-A = 3.3V, V DD-IO = 3.3V ? Rise/Fall Times: I/O: 5ns, Maximum

SCCB: 300ns, Maximum ? Input Capacitance: 10pf

? Output Loading: 25pF, 1.2KΩ to 3.3V

? f CLK: 24MHz

6Proprietary to OmniVision Technologies, Inc.Version 1.0, September 12, 2006

Timing Specifications

Version 1.0, September 12, 2006Proprietary to OmniVision Technologies, Inc.7

Timing Specifications

Figure 4 SCCB Timing Diagram

OV7725Color CMOS VGA OmniPixel2?C AMERA C HIP? Sensor O

Figure 7 QVGA Frame Timing

8Proprietary to OmniVision Technologies, Inc.Version 1.0, September 12, 2006

Timing Specifications

Version 1.0, September 12, 2006Proprietary to OmniVision Technologies, Inc.9

Figure 9 RGB 565 Output Timing Diagram

OV7725Color CMOS VGA OmniPixel2?C AMERA C HIP? Sensor O

Figure 11 RGB 444 Output Timing Diagram

10Proprietary to OmniVision Technologies, Inc.Version 1.0, September 12, 2006

Version 1.0, September 12, 2006Proprietary to OmniVision Technologies, Inc.11

Table 6 provides a list and description of the Device Control registers contained in the OV7725. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read.

Table 6

Device Control Register List (Sheet 1 of 11)

Address (Hex)Register Name Default (Hex)R/W Description

GAIN

AGC – Gain control gain setting

Bit[7:0]:AGC[7:0] (see GREEN [7:6] (0x03) for AGC[9:8])?Range: [00] to [FF]

01BLUE 80RW AWB – Blue channel gain setting ?Range: [00] to [FF]

02RED 80RW AWB – Red channel gain setting ?Range: [00] to [FF]

GREEN

AWB – Green channel gain setting ?Range: [00] to [FF]04COM100RW

Common Control 1

Bit[7:2]:Reserved

Bit[1:0]:

AGC 2 MSBs, AGC[9:8]

05BAVG 00RW U/B Average Level

Automatically updated based on chip output format 06GAVG 00RW Y/Gb Average Level

Automatically updated based on chip output format 07

RAVG

V/R Average Level

Automatically updated based on chip output format 08AECH 00RW

Exposure Value – AEC MSBs

Bit[7:5]:AEC[15:8] (see register AEC for AEC[7:0]}Automatically updated based on chip output format 09COM201RW

Common Control 2

Bit[7:5]:Reserved

Bit[4]:Soft sleep mode

Bit[3:2]:

Pixel clock output delay control ?Range: [00] to [11]Bit[1:0]:

Output drive capability 00:1x 01:2x 10:3x 11:4x

0A PID 77R Product ID Number MSB (Read only)0B

VER

Product ID Number LSB (Read only)

OV7725Color CMOS VGA OmniPixel2?C AMERA C HIP? Sensor O

0C COM310RW Common Control 3

Bit[7]:Vertical flip image ON/OFF selection

Bit[6]:Horizontal mirror image ON/OFF selection

Bit[5]:Swap B/R output sequence in RGB output mode

Bit[4]:Swap Y/UV output sequence in YUV output mode

Bit[3]:Swap output MSB/LSB

Bit[2]:Tri-state option for output clock at power-down period 0:Tri-state at this period

1:No tri-state at this period

Bit[1]:Tri-state option for output data at power-down period 0:Tri-state at this period

1:No tri-state at this period

Bit[0]:Sensor color bar test pattern output enable

0D COM441RW Common Control 4

Bit[7:6]:PLL frequency control

00:Bypass PLL

01:PLL 4x

10:PLL 6x

11:PLL 8x

Bit[5:4]:AEC evaluate window

00:Full window

01:1/2 window

10:1/4 window

11:Low 2/3 window Bit[3:0]:Reserved

0E COM501RW Common Control 5

Bit[7]:Auto frame rate control ON/OFF selection

Bit[6]:Auto frame rate control speed selection

Bit[5:4]:Auto frame rate max rate control

00:No reduction of frame rate

01:Max reduction to 1/2 frame rate

10:Max reduction to 1/4 frame rate

11:Max reduction to 1/8 frame rate Bit[3:2]:Auto frame rate active point control

00:Add frame when AGC reaches 2x gain

01:Add frame when AGC reaches 4x gain

10:Add frame when AGC reaches 8x gain

11:Add frame when AGC reaches 16x gain Bit[1]:Reserved

Bit[0]:AEC max step control

0:AEC increase step has limit

1:No limit to AEC increase step

0F COM643RW Common Control 6

Bit[7:1]:Reserved

Bit[0]:Auto window setting ON/OFF selection when format changes

Table 6 Device Control Register List (Sheet 2 of 11)

Address (Hex)Register

Name

Default

(Hex)R/W Description

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Version 1.0, September 12, 2006Proprietary to OmniVision Technologies, Inc.13

AEC

Exposure Value

Bit[7:0]:AEC[7:0] (see register AECH for AEC[15:8])

11CLKRC 80RW

Internal Clock

Bit[7]:Reserved

Bit[6]:Use external clock directly (no clock pre-scale available)

Bit[5:0]:

Internal clock pre-scalar

F(internal clock) = F(input clock)/(Bit[5:0]+1)?Range: [0 0000] to [1 1111]12COM700RW

Common Control 7

Bit[7]:

SCCB Register Reset 0:No change

1:Resets all registers to default values Bit[6]:

Resolution selection 0:VGA 1:QVGA

Bit[5]:ITU656 protocol ON/OFF selection Bit[4]:Reserved

Bit[3:2]:

RGB output format control 00:GBR4:2:201:RGB56510:RGB55511:RGB444

Bit[1:0]:

Output format control 00:YUV

01:Processed Bayer RAW 10:RGB

11:Bayer RAW

13COM88F RW

Common Control 8

Bit[7]:Enable fast AGC/AEC algorithm Bit[6]:

AEC - Step size limit

0:Step size is limited to vertical blank 1:Unlimited step size Bit[5]:Banding filter ON/OFF

Bit[4]:Enable AEC below banding value Bit[3]:Fine AEC ON/OFF control Bit[2]:AGC Enable Bit[1]:AWB Enable Bit[0]:

AEC Enable

Table 6

Device Control Register List (Sheet 3 of 11)

Address (Hex)Register Name Default (Hex)R/W Description

Proprietary to OmniVision Technologies, Inc.

Version 1.0, September 12, 2006OV7725

Color CMOS VGA OmniPixel2? C AMERA C HIP ? Sensor O

14COM94A RW

Common Control 9

Bit[7]:Histogram or average based AEC/AGC selection Bit[6:4]:

Automatic Gain Ceiling - maximum AGC value 000:2x 001:4x 010:8x 011:16x 100:32x 10164x 110:128x

111:Not allowed Bit[3]:Reserved

Bit[2]:Drop VSYNC output of corrupt frame Bit[1]:Drop HREF output of corrupt frame Bit[0]:Reserved

15COM1000RW

Common Control 10

Bit[7]:Output negative data

Bit[6]:HREF changes to HSYNC Bit[5]:

PCLK output option 0:Free running PCLK

1:PCLK does not toggle during horizontal blank Bit[4]:PCLK reverse Bit[3]:HREF reverse Bit[2]:

VSYNC option

0:VSYNC changes on falling edge of PCLK 1:VSYNC changes on rising edge of PCLK Bit[1]:VSYNC negative

Bit[0]:

Output data range selection 0:Full range

1:Data from [10] to [F0] (8 MSBs)

16RSVD XX –Reserved

17HSTART 23 (VGA)3F (QVGA)RW Horizontal Sensor Size

18HSIZE A0 (VGA)50 (QVGA)RW Horizontal Frame (HREF column) end high 8-bit (low 2bits are at HREF [1:0])

19VSTRT 07 (VGA)03 (QVGA)RW Vertical Frame (row) start high 8-bit (low 1 bit is at HREF [6])1A

VSIZE

F0 (VGA)78 (QVGA)

Vertical Sensor Size

1B PSHFT 40RW

Data Format - Pixel Delay Select (delays timing of the D[9:0] data relative to HREF in pixel units)

?Range: [00] (no delay) to [FF] (256 pixel delay which accounts for whole array)1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)1D MIDL A2R Manufacturer ID Byte – Low (Read only = 0xA2)

RSVD

–

Reserved

Table 6

Device Control Register List (Sheet 4 of 11)

Address (Hex)

Default (Hex)

R/W

Description

Version 1.0, September 12, 2006Proprietary to OmniVision Technologies, Inc.15

LAEC

Fine AEC Value - defines exposure value less than one line period 20COM1110RW

Common Control 11

Bit[7:2]:Reserved

Bit[1]:Single frame ON/OFF selection Bit[0]:Single frame transfer trigger

21RSVD XX –Reserved

22BDBase FF RW Banding Filter Minimum AEC Value 23DBStep 01RW Banding Filter Maximum Step

24AEW 75RW AGC/AEC - Stable Operating Region (Upper Limit)25AEB 63RW AGC/AEC - Stable Operating Region (Lower Limit)26VPT D4RW AGC/AEC Fast Mode Operating Region

Bit[7:4]:High nibble of upper limit of fast mode control zone Bit[3:0]:High nibble of lower limit of fast mode control zone 27

RSVD

–

Reserved 28REG28??RW

Bit[7:2]:Reserved

Bit[1]:

Frame sync option (in external frame sync mode, set this bit to 1)

Bit[0]:

Auto frame adjust option

0:Always decrease frame rate by 2

1:Decrease frame rate by inserting dummy vertical

sync equal to maximum exposure lines 29HOutSize

A0 (VGA)50 (QVGA)

RW Horizontal Data Output Size MSBs (2 LSBs at register EXHCH [1:0])2A EXHCH 00RW

Dummy Pixel Insert MSB

Bit[7:4]: 4 MSB for dummy pixel insert in horizontal direction Bit[3]:Reserved

Bit[2]:Vertical data output size LSB

Bit[1:0]:Horizontal data output size 2 LSBs

2B EXHCL 00RW Dummy Pixel Insert LSB

8 LSB for dummy pixel insert in horizontal direction

2C VOutSize F0 (VGA)78 (QVGA)

RW Vertical Data Output Size MSBs (LSB at register EXHCH [2])2D ADVFL 00RW LSB of Insert Dummy Lines in Vertical Direction (1 bit equals 1 line)2E ADVFH 00RW MSB of Insert Dummy Lines in Vertical Direction 2F YAVE 00RW Y/G Channel Average Value

30LumHTh 80RW Histogram AEC/AGC Luminance High Level Threshold 31

LumLTh

Histogram AEC/AGC Luminance Low Level Threshold

Table 6

Device Control Register List (Sheet 5 of 11)

Address (Hex)Register Name Default (Hex)R/W Description

Proprietary to OmniVision Technologies, Inc.

Version 1.0, September 12, 2006

OV7725

Color CMOS VGA OmniPixel2? C AMERA C HIP ? Sensor O

32HREF 00RW

Image Start and Size Control

Bit[7]:Mirror image edge alignment

Bit[6]:Vertical HREF window start control LSB Bit[5:4]:Horizontal HREF window start control LSBs Bit[3]:Data output bit shift test pattern ON/OFF control Bit[2]:Vertical sensor size LSB

Bit[1:0]:

Horizontal sensor size 2 LSBs

33DM_LNL 00RW Dummy Line Low 8 Bits 34DM_LNH 00RW Dummy Line High 8 Bits

35ADoff_B 80RW AD Offset Compensation Value for B Channel 36ADoff_R 80RW AD Offset Compensation Value for R Channel 37ADoff_Gb 80RW AD Offset Compensation Value for Gb Channel 38ADoff_Gr 80RW AD Offset Compensation Value for Gr Channel 39Off_B 80RW Analog Process B Channel Offset Compensation Value 3A Off_R 80RW Analog Process R Channel Offset Compensation Value 3B Off_Gb 80RW Analog Process Gb Channel Offset Compensation Value 3C Off_Gr 80RW Analog Process Gr Channel Offset Compensation Value 3D

COM12

Common Control 12

Bit[7:6]:Reserved

Bit[5:0]:DC offset compensation for analog process 3E

COM13

Common Control 13

Bit[7]:Analog processing channel BLC ON/OFF control Bit[6]:ADC channel BLC ON/OFF control Bit[5:0]:Reserved

3F COM141F RW

Edge Enhancement Adjustment

Bit[7:4]:Reserved

Bit[3:2]:

AD offset compensation option

x0:Use R/Gr channel value for B/Gb 01:Use B/Gb channel value for R/Gr

11:Use B/Gb/R/Gr channel value independently Bit[1:0]:

Analog processing offset compensation option x0:Use R/Gr channel value for B/Gb 01:Use B/Gb channel value for R/Gr

11:Use B/Gb/R/Gr channel value independently 40

COM15

Common Control 15

Bit[7:4]:Reserved

Bit[3]:AD add 128 bit offset Bit[2:0]:Reserved 41COM1608RW Common Control 16

Bit[7:2]:Reserved

Bit[1:0]:

BLC target 2 LSBs

TGT_B

BLC Blue Channel Target Value

Table 6

Device Control Register List (Sheet 6 of 11)

Address (Hex)

Default (Hex)

R/W

Description

Version 1.0, September 12, 2006

Proprietary to OmniVision Technologies, Inc.

43TGT_R 80RW BLC Red Channel Target Value 44TGT_Gb 80RW BLC Gb Channel Target Value 45

TGT_Gr

BLC Gr Channel Target Value 46LCC000RW

Lens Correction Control 0

Bit[7:3]:Reserved

Bit[2]:

Lens correction control select

0:R, G, and B channel compensation coefficient is

set by registers LCC3 (0x49)

1:R, G, and B channel compensation coefficient is

set by registers LCC5 (0x4B), LCC3 (0x49), and LCC6 (0x4C), respectively Bit[1]:Reserved

Bit[0]:

Lens correction enable 0:Disable 1:Enable

47LCC100RW Lens Correction Option 1 – X Coordinate of Lens Correction Center Relative to Array Center

LCC2

Lens Correction Option 2 – Y Coordinate of Lens Correction Center Relative to Array Center

49LCC350–

Lens Correction Option 3

G channel compensation coefficient when LCC0[2] (0x46) is 1R, G, and B channel compensation coefficient when LCC0[2] is 04A LCC430–Lens Correction Option 4 – radius of the circular section where no compensation applies

4B LCC550RW Lens Correction Option 5 (effective only when LCC0[2] is high)4C

LCC6

Lens Correction Option 6 (effective only when LCC0[2] is high)4D FixGain 00RW

Analog Fix Gain Amplifier

Bit[7:6]:Gb channel fixed gain Bit[5:4]:Gr channel fixed gain Bit[3:2]: B channel fixed gain Bit[1:0]:

R channel fixed gain

4E AREF0EF RW

Sensor Reference Control ?Range: [00] to [FF]

4F AREF110RW

Sensor Reference Current Control

Bit[7:4]:Sensor reference current control Bit[3]:Internal regulator ON/OFF selection Bit[2]:Reserved

Bit[1:0]:

Analog reference control

50AREF260RW Analog Reference Control ?Range: [00] to [FF]51AREF300RW ADC Reference Control ?Range: [00] to [FF]52

AREF4

ADC Reference Control ?Range: [00] to [FF]

Table 6

Device Control Register List (Sheet 7 of 11)

Address (Hex)Register Name Default (Hex)R/W Description

Proprietary to OmniVision Technologies, Inc.

Version 1.0, September 12, 2006

OV7725

Color CMOS VGA OmniPixel2? C AMERA C HIP ? Sensor O

53AREF524RW ADC Reference Control ?Range: [00] to [FF]54AREF67A RW Analog Reference Control ?Range: [00] to [FF]55AREF7FC RW Analog Reference Control ?Range: [00] to [FF]56-5F RSVD XX –Reserved

60UFix 80RW U Channel Fixed Value Output 61VFix 80RW V Channel Fixed Value Output 62

AWBb_blk

AWB Option for Advanced AWB 63AWB_Ctrl0F0RW

AWB Control Byte 0

Bit[7]:AWB gain enable

Bit[6]:AWB calculate enable Bit[5]:Reserved

Bit[4:0]:WBC threshold 2

64DSP_Ctrl11F RW

DSP Control Byte 1

Bit[7]:FIFO enable/disable selection

Bit[6]:UV adjust function ON/OFF selection

Bit[5]:YUV444 to 422 UV channel option selection Bit[4]:Color matrix ON/OFF selection Bit[3]:Interpolation ON/OFF selection Bit[2]:Gamma function ON/OFF selection Bit[1]:Black defect auto correction ON/OFF Bit[0]:White defect auto correction ON/OFF 65

DSP_Ctrl2

DSP Control Byte 2

Bit[7:4]:Reserved

Bit[3:0]:Scaling control

66DSP_Ctrl310RW

DSP Control Byte 3

Bit[7]:UV output sequence option Bit[6]:Reserved

Bit[5]:DSP color bar ON/OFF selection Bit[4]:Reserved

Bit[3]:FIFO power down ON/OFF selection Bit[2]:Scaling module power down control 1Bit[1]:Scaling module power down control 2Bit[0]:

Interpolation module power down control

67DSP_Ctrl400RW DSP Control Byte 468AWB_bias 00RW AWB BLC Level Clip 69AWBCtrl15C RW AWB Control 16A AWBCtrl211RW AWB Control 26B AWBCtrl3A2RW AWB Control 36C

AWBCtrl4

AWB Control 4

Table 6

Device Control Register List (Sheet 8 of 11)

Address (Hex)Register Name Default (Hex)R/W Description

Version 1.0, September 12, 2006Proprietary to OmniVision Technologies, Inc.19

6D AWBCtrl550RW AWB Control 56E AWBCtrl680RW AWB Control 66F AWBCtrl780RW AWB Control 770AWBCtrl80F RW AWB Control 871AWBCtrl900RW AWB Control 972AWBCtrl1000RW AWB Control 1073AWBCtrl110F RW AWB Control 1174AWBCtrl120F RW AWB Control 1275AWBCtrl13FF RW AWB Control 1376AWBCtrl14FF RW AWB Control 1477AWBCtrl15FF RW AWB Control 1578AWBCtrl1610RW AWB Control 1679AWBCtrl1770RW AWB Control 177A AWBCtrl1870RW AWB Control 187B AWBCtrl19F0RW AWB Control 197C AWBCtrl20F0RW AWB Control 207D AWBCtrl21F0RW AWB Control 21

7E GAM10E RW Gamma Curve 1st Segment Input End Point 0x04 Output Value 7F GAM21A RW Gamma Curve 2nd Segment Input End Point 0x08 Output Value 80GAM331RW Gamma Curve 3rd Segment Input End Point 0x10 Output Value 81GAM45A RW Gamma Curve 4th Segment Input End Point 0x20 Output Value 82GAM569RW Gamma Curve 5th Segment Input End Point 0x28 Output Value 83GAM675RW Gamma Curve 6th Segment Input End Point 0x30 Output Value 84GAM77E RW Gamma Curve 7th Segment Input End Point 0x38 Output Value 85GAM888RW Gamma Curve 8th Segment Input End Point 0x40 Output Value 86GAM98F RW Gamma Curve 9th Segment Input End Point 0x48 Output Value 87GAM1096RW Gamma Curve 10th Segment Input End Point 0x50 Output Value 88GAM11A3RW Gamma Curve 11th Segment Input End Point 0x60 Output Value 89GAM12AF RW Gamma Curve 12th Segment Input End Point 0x70 Output Value 8A GAM13C4RW Gamma Curve 13th Segment Input End Point 0x90 Output Value 8B GAM14D7RW Gamma Curve 14th Segment Input End Point 0xB0 Output Value 8C GAM15E8RW Gamma Curve 15th Segment Input End Point 0xD0 Output Value 8D SLOP 20RW Gamma Curve Highest Segment Slope - calculated as follows:SLOP[7:0] = (0x100 - GAM15[7:0]) x 4/38E

DNSTh

De-noise Threshold

Table 6

Device Control Register List (Sheet 9 of 11)

Address (Hex)Register Name Default (Hex)R/W Description

Proprietary to OmniVision Technologies, Inc.

Version 1.0, September 12, 2006

OV7725

Color CMOS VGA OmniPixel2? C AMERA C HIP ? Sensor O

EDGE0

Edge Enhancement Control 0

Bit[7:5]:Reserved

Bit[4:0]:Edge enhancement strength control 90EDGE108RW Edge Enhancement Control 1

Bit[7:4]:Reserved

Bit[3:0]:

Edge enhancement threshold control

91DNSOff 10RW Auto De-noise Threshold Control

92EDGE21F RW Edge Enhancement Strength Low Point Control 93EDGE301RW Edge Enhancement Strength High Point Control 94MTX12C RW Matrix Coefficient 195MTX224RW Matrix Coefficient 296MTX308RW Matrix Coefficient 397MTX414RW Matrix Coefficient 498MTX524RW Matrix Coefficient 599

MTX6

Matrix Coefficient 69A MTX_Ctrl 9E RW

Matrix Control

Bit[7]:Matrix double ON/OFF selection Bit[6]:Reserved

Bit[5]:Sign bit for MTX6Bit[4]:Sign bit for MTX5Bit[3]:Sign bit for MTX4Bit[2]:Sign bit for MTX3Bit[1]:Sign bit for MTX2Bit[0]:

Sign bit for MTX1

9B BRIGHT 00RW Brightness Control 9C CNST 40RW Contrast Control 9D CNST_ctr 00RW Contrast Control Center 9E

UVADJ0

Auto UV Adjust Control 0

Bit[7:4]:Auto UV adjust offset control 4 LSBs Bit[3:0]:Auto UV adjust threshold control 9F

UVADJ1

Auto UV Adjust Control 1

Bit[7:3]:Auto UV adjust value Bit[2]:Reserved

Bit[1]:Auto UV adjust stop control

Bit[0]:

Auto UV adjust offset control MSB

A0SCAL000RW Scaling Control 0

A1SCAL140RW Scaling Control 1 – for horizontal scaling control A2SCAL240RW Scaling Control 2 – for vertical scaling control A3FIFOdlyM 06RW FIFO Manual Mode Delay Control A4