W39F010T-90中文资料
128K × 8 CMOS FLASH MEMORY
Publication Release Date: June 17, 2002
1. GENERAL DESCRIPTION
The W39F010 is a 1Mbit, 5-volt only CMOS flash memory organized as 128K × 8 bits. For flexible erase capability, the 1Mbits of data are divided into 32 small even pages with 4 Kbytes. The byte-wide (× 8) data appears on DQ7 ? DQ0. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V PP is not required. The unique cell architecture of the W39F010 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers.
2. FEATURES
? Single 5-volt operations
? 5-volt Read ? 5-volt Erase ? 5-volt Program
? Fast Program operation:
? Byte-by-Byte programming: 50 μS (max.)
? Fast Erase operation:
? Chip Erase cycle time: 100 mS (max.) ? P age Erase cycle time: 25 mS (max.)
? Read access time: 70/90 nS ? 32 even pages with 4K bytes ? Any individual page can be erased ? Hardware protection:
? Optional 16K byte Top/Bottom Boot Block with lockout protection ? Flexible 4K-page size can be used as
Parameter Blocks
? Typical program/erase cycles:
? 1K/10K
? Twenty-year data retention ? Low power consumption
? Active current: 15 mA (typ.) ? Standby current: 15 μA (typ.)
? End of program detection
? Software method: Toggle bit/Data polling ? TTL compatible I/O
? JEDEC standard byte-wide pinouts ? Available packages: 32-pin 600 mil DIP,
32-pin PLCC, 32- pin STSOP (8 x 14 mm) and 32- pin TSOP
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
5. PIN DESCRIPTION
SYMBOL
PIN NAME
A0 ? A16 Address Inputs DQ0 ? DQ7
Data Inputs/Outputs #CE Chip Enable #OE Output Enable #WE Write Enable V DD
Power Supply V SS Ground NC
No Connections
W39F010
Publication Release Date: June 17, 2002
6. FUNCTIONAL DESCRIPTION
Device Bus Operation
Read Mode
The read operation of the W39F010 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details.
Write Mode
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to bring #WE to logic low state, while #CE is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Standby Mode
There are two ways to implement the standby mode on the W39F010 device, both using the #CE pin.
A CMOS standby mode is achieved with the #CE input held at V DD ±0.5V. Under this condition the current
is typically reduced to less than 50 μA. A TTL standby mode is achieved with the #CE pin held at V IH . Under this condition the current is typically reduced to 2 mA.
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
Output Disable Mode
With the #OE input at a logic high level (V IH ), output from the device is disabled. This will cause the output pins to be in a high impedance state.
Data Protection
The W39F010 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from V DD power-up and power-down transitions or system noise.
W39F010
Boot Block Operation
There are two alternatives to set the boot block. The 16K-byte in the top/bottom location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes or first 16K bytes of the memory with the address range from 1C000(hex) to 1FFFF(hex) for top location or 00000(hex) to 03FFF(hex) for bottom location.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method.
In order to detect whether the boot block feature is set on the first/last 16K-byte block or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 0002(hex) for first(bottom) location or 1FFF2(hex) for last(top) location. If the DQ0/DQ1 of output data is "1," the 16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of output data is "0," the lockout feature will be inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Low V DD Inhibit
To avoid initiation of a write cycle during V DD power-up and power-down, the W39F010 locks out when V DD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited when V DD is less than 2.0V typical. The W39F010ignores all write and read operations until V DD > 2,0V. The user must ensure that the control pins are in the correct logic state when V DD > 2.0V to prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of #OE = V IL, #CE = V IH, or #WE = V IH. To initiate a write cycle #CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write Inhibit
Power-up of the device with #WE = #CE = V IL and #OE = V IH will not accept commands on the rising edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state machine is automatically reset to the read mode on power-up.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command Definitions" defines the valid register command sequences.
W39F010
Publication Release Date: June 17, 2002
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system.
The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39F010 = A1).
To terminate the operation, it is necessary to write the auto-select exit command sequence into the register.
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted.
Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only erase operations can convert "0"s to "1"s.
Refer to the Programming Command Flow Chart using typical command strings and bus operations.
W39F010
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each pages at the same time (see "Feature"). The system is not required to provide any controls or timings during these operations.
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Erase Command Flow Chart using typical command strings and bus operations.
Page Erase Command
Page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the page erase command. The page address (any address location within the desired page) is latched on the falling edge of #WE, while the command (50H) is latched on the rising edge of #WE.
Page erase does not require the user to program the device prior to erase. When erasing a page, the remaining unselected pages are not affected. The system is not required to provide any controls or timings during these operations.
The automatic page erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last page erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the pages being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
Write Operation Status
DQ7: Data Polling
The W39F010 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7.
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output.
For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequences. For page erase, the Data Polling is valid after the last rising edge of the page erase #WE pulse. Data Polling must be performed at addresses within any of the pages being erased. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on
W39F010
Publication Release Date: June 17, 2002
DQ7 at one instant of time and then that byte ′s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0–DQ6 may be still invalid. The valid data on DQ0 ? DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or page erase time-out (see "Command Definitions").
DQ6: Toggle Bit
The W39F010 also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For page erase, the Toggle Bit is valid after the last rising edge of the page erase #WE pulse. The Toggle Bit is active during the page erase time-out.
Either #CE or #OE toggling will cause DQ6 to toggle.
7. TABLE OF OPERATING MODES
Device Bus Operations
PIN
MODE
#CE #OE #WE DQ0 ? DQ7
Read V IL V IL V IH Dout Write V IL V IH V IL Din Standby V IH
X
X
High Z
X V IL X High Z/Dout Write Inhibit X
X
V IH
High Z/Dout
Output Disable
V IL V IH V IH High Z
W39F010
Command Definitions
COMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE 7TH CYCLE
DESCRIPTION Cycles Addr. (1)Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read 1 A IN D OUT
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Page Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 PA(3) 50
Byte Program 4 5555 AA 2AAA 55 5555 A0 A IN D IN
Top Boot Block
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 70 1FFFF XX(4) Lockout –16KByte
Bottom Boot Block
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 70 00000 XX(4) Lockout - 16KByte
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit (2) 3 5555 AA 2AAA 55 5555 F0
Product ID Exit (2) 1 XXXX F0
Notes:
1. Address Format: A14 ? A0 (Hex); Data Format: DQ7 ? DQ0 (Hex)
2. Either one of the two Product ID Exit commands can be used.
3. PA: Page Address
PA = 1FXXXh for Page 31 PA = 0FXXXh for Page 15
PA = 1EXXXh for Page 30 PA = 0EXXXh for Page 14
PA = 1DXXXh for Page 29 PA = 0DXXXh for Page 13
PA = 1CXXXh for Page 28 PA = 0CXXXh for Page 12
PA = 1BXXXh for Page 27 PA = 0BXXXh for Page 11
PA = 1AXXXh for Page 26 PA = 0AXXXh for Page 10
PA = 19XXXh for Page 25 PA = 09XXXh for Page 9
PA = 18XXXh for Page 24 PA = 08XXXh for Page 8
PA = 17XXXh for Page 23 PA = 07XXXh for Page 7
PA = 16XXXh for Page 22 PA = 06XXXh for Page 6
PA = 15XXXh for Page 21 PA = 05XXXh for Page 5
PA = 14XXXh for Page 20 PA = 04XXXh for Page 4
PA = 13XXXh for Page 19 PA = 03XXXh for Page 3
PA = 12XXXh for Page 18 PA = 02XXXh for Page 2
PA = 11XXXh for Page 17 PA = 01XXXh for Page 1
PA = 10XXXh for Page 16 PA = 00XXXh for Page 0
4. XX: Don't care
W39F010
Publication Release Date: June 17, 2002
Embedded Programming Algorithm
W39F010
Embedded Erase Algorithm
W39F010
Publication Release Date: June 17, 2002
Embedded #Data Polling Algorithm
Embedded Toggle Bit Algorithm
W39F010
Boot Block Lockout Enable Flow Chart
W39F010
Publication Release Date: June 17, 2002
Software Product Identification and Boot Block Lockout Detection Flow Chart
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7?DQ0 (Hex); Address Format: A14?A0 (Hex)
(2) A1?A16 = V IL ; manufacture code is read for A0 = V IL ; device code is read for A0 = V IH .
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0 or DQ1= " 1 " the boot block programming lockout feature is activated; if the output data
in DQ0 or DQ1= " 0 ," the lockout feature is inactivated and the matched boot block can be programmed. (5) The device returns to standard operation mode.
(6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
W39F010
8. DC CHARACTERISTICS
Absolute maximum Ratings
PARAMETER RATING UNIT Power Supply Voltage to V SS Potential -2.0 to +7.0 V Operating Temperature 0 to +70 °C Storage Temperature -65 to +125 °C Voltage on Any Pin to Ground Potential Except A9 -2.0 to +7.0 V Voltage on A9 Pin to Ground Potential -2.0 to +13.0 V Note: Exposure to conditions beyond those listed under Absolute maximum Ratings may adversely affect the life and reliability of the device.
DC Operating Characteristics
(V DD = 5V ±0.5V, V SS = 0V, T A = 0 to 70° C)
LIMITS PARAMETER SYM. TEST CONDITIONS
MIN. TYP. MAX.
UNIT
Power Supply Current I DD #CE = #OE = V IL, #WE = V IH,
all DQs open
Address inputs = V IL/V IH, at f = 5 MHz
- 15 30
mA
Standby V DD Current (TTL input) I SB1 #CE = V IH, all DQs open
Other inputs = V IL/V IH
- 1 2 mA
Standby V DD Current (CMOS input) I SB2
#CE = V DD -0.3V, all DQs open
Other inputs = V DD -0.3V/ V SS
- 15 50
μA
Input Leakage Current I LI V IN = V SS to V DD- - 1 μA Output Leakage
Current
I LO V OUT = V SS to V DD- - 1 μA Input Low Voltage V IL- -0.3 - 0.8 V Input High Voltage V IH- 2.0 - V DD +0.5 V Output Low Voltage V OL I OL = 2.1 mA - - 0.45 V Output High Voltage V OH I OH = -0.4 mA 2.4 - - V Pin Capacitance
(V DD = 5V, T A = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS TYP. MAX. UNIT Input Capacitance C IN V IN = 0V 6 8 pF Output Capacitance C OUT V OUT = 0V 10 12 pF
W39F010
Publication Release Date: June 17, 2002
9. AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels 0V to 3V Input Rise/Fall Time <5 nS Input/Output Timing Level 1.5V/1.5V
Output Load
1 TTL Gate and C L
= 30 pF
AC Test Load and Waveform
W39F010
AC Characteristics, continued
Read Cycle Timing Parameters
(V DD = 5V ±0.5V, V SS = 0V, T A = 0 to 70° C)
W39F010-70 W39F010-90
PARAMETER SYMBOL
UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time T RC 70 - 90 - nS Chip Enable Access Time T CE - 70 - 90 nS Address Access Time T AA - 70 - 90 nS Output Enable Access Time T OE - 35 - 45 nS
#CE Low to Active Output T CLZ 0 - 0 - nS
#OE Low to Active Output T OLZ 0 - 0 - nS
#CE High to High-Z Output T CHZ - 25 - 25 nS
#OE High to High-Z Output T OHZ - 25 - 25 nS Output Hold from Address Change T OH 0 - 0 - nS
Write Cycle Timing Parameters
PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Setup Time T AS 0 - - nS Address Hold Time T AH 40 - - nS
#WE and #CE Setup Time T CS 0 - - nS
#WE and #CE Hold Time T CH 0 - - nS
#OE High Setup Time T OES 0 - - nS
#OE High Hold Time T OEH 0 - - nS
#CE Pulse Width T CP 100 - - nS
#WE Pulse Width T WP 100 - - nS
#WE High Width T WPH 100 - - nS Data Setup Time T DS 40 - - nS Data Hold Time T DH 10 - - nS Byte programming Time T BP - 35 50 μS Chip Erase Cycle Time T EC - 50 100 mS Page Erase Cycle Time T EP - 12.5 25 mS Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is V IH and (b) low level signal's reference level is V IL.
W39F010
Publication Release Date: June 17, 2002
AC Characteristics, continued
Power-up Timing
PARAMETER
SYMBOL TYPICAL UNIT Power-up to Read Operation T PU . READ 100 μS Power-up to Write Operation
T PU . WRITE
5
mS
Data Polling and Toggle Bit Timing Parameters
W39F010-70 W39F010-90 PARAMETER
SYM. MIN.
MAX.
MIN.
MAX.
UNIT
#OE to Data Polling Output Delay T OEP - 35 - 45 nS #CE to Data Polling Output Delay T CEP - 70 - 90 nS #OE to Toggle Bit Output Delay T OET - 35 - 45 nS #CE to Toggle Bit Output Delay
T CET
-
70
-
90
nS
W39F010
10. TIMING WAVEFORMS
Read Cycle Timing Diagram
#WE Controlled Command Write Cycle Timing Diagram
W39F010
Publication Release Date: June 17, 2002
Timing Waveforms, continued
#CE Controlled Command Write Cycle Timing Diagram
Chip Erase Timing Diagram
W39F010
Timing Waveforms, continued
Page Erase Timing Diagram
#DATA Polling Timing Diagram