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LTC2225IUH中文资料

CODE

2225 G01

12225fa

2225fa

ABSOLUTE AXI U RATI GS

W W W

U PACKAGE/ORDER I FOR ATIO

W OV DD = V DD (Notes 1, 2)

Supply Voltage (V DD ).................................................4V Digital Output Ground Voltage (OGND).......–0.3V to 1V Analog Input Voltage (Note 3).....–0.3V to (V DD + 0.3V)Digital Input Voltage ....................–0.3V to (V DD + 0.3V)Digital Output Voltage................–0.3V to (OV DD + 0.3V)Power Dissipation............................................1500mW Operating Temperature Range

LTC2225C ...............................................0°C to 70°C LTC2225I.............................................–40°C to 85°C Storage Temperature Range..................–65°C to 125°C

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T A = 25°C. (Note 4)

PARAMETER CONDITIONS

MIN TYP MAX UNITS Resolution

●

12Bits

(No Missing Codes)Integral

Differential Analog Input ●–1.1±0.3 1.1LSB Linearity Error (Note 5)

Differential Differential Analog Input ●–0.7±0.150.7LSB Linearity Error Offset Error (Note 6)●–12±212mV Gain Error External Reference ●

–2.5

±0.5 2.5

%FS Offset Drift ±10μV/°C Full-Scale Drift Internal Reference ±30ppm/°C External Reference ±5ppm/°C Transition Noise

SENSE = 1V

0.25

LSB RMS

CO VERTER CHARACTERISTICS

ORDER PART NUMBER

Consult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.

T JMAX = 125°C, θJA = 34°C/W EXPOSED PAD IS GND (PIN 33)MUST BE SOLDERED TO PCB

3231302928272625

9101112TOP VIEW UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

13141516

17181920212223248

7654321A IN +A IN –REFH REFH REFL REFL V DD GND D8D7D6OV DD OGND D5D4D3

V D D

V C M

S E N S E

M O D E

O F

D 11

D 10D 9

C L K

S H D N

O E

N C

D 0

D 1

D 2

QFN PART MARKING

LTC2225CUH LTC2225IUH

2225*

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: https://www.wendangku.net/doc/a02841121.html,/leadfree/

2225fa

The ● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T A = 25°C. A IN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 5MHz Input ●69.871.3dB 70MHz Input 70.7dB SFDR Spurious Free Dynamic Range 5MHz Input ●7690dB 2nd or 3rd Harmonic 70MHz Input 85dB SFDR Spurious Free Dynamic Range 5MHz Input ●8290dB 4th Harmonic or Higher

70MHz Input 90dB S/(N+D)Signal-to-Noise Plus Distortion Ratio 5MHz Input ●

69.5

71.3dB 70MHz Input

70.4dB I MD

Intermodulation Distortion

f IN1 = 4.3MHz, f IN2 = 4.6MHz

DY A IC ACCURACY

W PARAMETER CONDITIONS MIN TYP MAX UNITS

V CM Output Voltage I OUT = 0

1.475

1.500 1.525

V V CM Output Tempco ±25ppm/°C V CM Line Regulation 2.7V < V DD < 3.4V 3mV/V V CM Output Resistance

–1mA < I OUT < 1mA

I TER AL REFERE CE CHARACTERISTICS

U U U

(Note 4)

A ALOG I PUT

The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T A = 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

V IN Analog Input Range (A IN + –A IN –) 2.7V < V DD < 3.4V (Note 7)●±0.5V to ±1V

V V IN,CM Analog Input Common Mode(A IN + +A IN –)/2Differential Input (Note 7)●1 1.5 1.9V Single Ended Input (Note 7)●0.5 1.5

2V I IN Analog Input Leakage Current 0V < A IN +, A IN – < V DD ●–11μA I SENSE SENSE Input Leakage 0V < SENSE < 1V

●–33μA I MODE MODE Pin Leakage

●

–3

μA t AP Sample-and-Hold Acquisition Delay Time 0ns t JITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2ps RMS

CMRR

Analog Input Common Mode Rejection Ratio

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V DD , they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup.

Note 4: V DD = 3V, f SAMPLE = 10MHz, input range = 2V P-P with differential drive, unless otherwise noted.

Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.The deviation is measured from the center of the quantization band.Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111.Note 7: Guaranteed by design, not subject to test.

Note 8: V DD = 3V, f SAMPLE = 10MHz, input range = 1V P-P with differential drive.

Note 9: Recommended operating conditions.

TI I G CHARACTERISTICS

W The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T A = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f s Sampling Frequency (Note 9)

●110MHz t L

CLK Low Time

Duty Cycle Stabilizer Off ●4050500ns Duty Cycle Stabilizer On ●550500ns (Note 7)

t H

CLK High Time

Duty Cycle Stabilizer Off ●4050500ns Duty Cycle Stabilizer On ●

50500

ns (Note 7)t AP Sample-and-Hold Aperture Delay 0

t D

CLK to DATA delay C L = 5pF (Note 7)● 1.4 2.7 5.4ns Data Access Time After OE ↓C L = 5pF (Note 7)● 4.310ns BUS Relinquish Time

(Note 7)

●

3.38.5

ns Pipeline 5

Cycles

Latency

Typical DNL, 2V Range

Typical INL, 2V Range

8192 Point FFT, f IN = 5.1MHz,–1dB, 2V Range

TYPICAL PERFOR A CE CHARACTERISTICS

U W

CODE

–1.0

I N L E R R O R (L S B )

–0.8–0.4–0.201.00.4

1024

20482225 G01

–0.60.6

0.80.23072

4096

CODE

–1.0

D N L

E R R O R (L S B )

–0.8–0.4–0.201.00.4

1024

20482225 G02

–0.60.60.80.23072

4096

FREQUENCY (MHz)

0A M P L I T U D E (d B )

–60–40–20042225 G03

–80–100–70–50–30–10–90–110–120

SNR vs Input Frequency, –1dB,2V Range

SFDR vs Input Frequency, –1dB,2V Range

FREQUENCY (MHz)

–6004

2225 G04

–701

FREQUENCY (MHz)

2225 G05

INPUT FREQUENCY (MHz)

2040502225 G07

3060

INPUT FREQUENCY (MHz)

030502225 G08

406070

2225fa

APPLICATIO S I FOR ATIO

W U

U and nap modes, all digital outputs are disabled and enter the Hi-Z state.

Grounding and Bypassing

The LTC2225 requires a printed circuit board with a clean,unbroken ground plane. A multilayer board with an inter-nal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at the V DD , OV DD , V CM , REFH, and REFL pins. Bypass capaci-tors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402ceramic capacitor is recommended. The large 2.2μF

capacitor between RE FH and RE FL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2225 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.Heat Transfer

Most of the heat generated by the LTC2225 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

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Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● https://www.wendangku.net/doc/a02841121.html,

? LINEAR TECHNOLOGY CORPORATION 2004

LT 0106 REV A ? PRINTED IN USA

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