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MT90826中文资料

Features

?4,096 × 4,096 channel non-blocking switching at 8.192 or 16.384Mbps

?Per-channel variable or constant throughput delay

?Accepts 32 ST-BUS streams of 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps ?Split Rate mode provides a rate conversion option to convert data from one rate to another rate ?Automatic frame offset delay measurement for ST-BUS input streams

?Per-stream input delay programming

?Per-stream output advancement programming ?Per-channel high impedance output control ?Bit Error Monitoring on selected ST-BUS input and output channels.?Per-channel message mode

?Connection memory block programming ?IEEE-1149.1 (JTAG) Test Port

3.3V local I/O with 5V tolerant inputs and TTL compatible outputs

Applications

?Medium switching platforms ?CTI application ?Voice/data multiplexer ?Digital cross connects ?WAN access system ?

Wireless base stations

August 2005

Ordering Information

MT90826AL 160 Pin MQFP Trays MT90826AG 160 Ball PBGA Trays MT90826AV 144 Ball LBGA Trays MT90826AL1160 Pin MQFP*

Trays

*Pb Free Matte Tin -40°C to +85°C

MT90826

Quad Digital Switch

Data Sheet

Figure 1 - Functional Block Diagram

Test Port

STo0STo1???STo31

STi0/FEi0STi1/FEi1

???

STi31/FEi31

Parallel to Serial Converter

Output MUX

Microprocessor Interface

Timing Unit

Internal Registers

F0i

DS CS R/W A13-A0DTA D15-D0

ODE

V SS

Connection Memory

CLK V DD TDI TDO RESET TCK TRST Serial to Parallel Converter

TMS Multiple Buffer Data Memory

PLLV SS PLLV DD

Description

The MT90826 Quad Digital Switch has a non-blocking switch capacity of 4,096 x 4,096 channels at a serial bit rate of 8.192Mbps or 16.384Mbps, 2,048 x 2,048 channels at 4.096Mbps and 1024 x 1024 channels at 2.048Mbps. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control.

The per stream input and output delay control is particularly useful for managing large multi-chip switches with a distributed backplane.

Operating in Split Rate mode allows rate conversion for switching between two groups of bit rate streams.

Table of Contents

1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1 Data and Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.2 Connection and Message Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.3 Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.0 Switching Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.1 Serial Input Frame Alignment Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2 Input Frame Offset Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.3 Output Advance Offset Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.4 Memory Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.5 Bit Error Rate Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.0 Delay Through the MT90826. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.1 Variable Delay Mode (TM1=0, TM0=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.2 Constant Delay Mode (TM1=1, TM0=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.0 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

6.0 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

7.0 Connection Memory Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

8.0 DTA Data Transfer Acknowledgment Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9.0 Initialization of the MT90826. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

10.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

10.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

10.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - 160-Pin MQFP Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3 - 160 Ball PBGA Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - 144 Ball LBGA Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5 - Example for Frame Alignment Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6 - Examples for Input Offset Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7 - Examples for Frame Output Offset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 8 - ST-BUS Timing for Stream rate of 16.384Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 9 - ST-BUS Timing for Stream rate of 8.192Mbps when CLK = 16.384MHz . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10 - ST-BUS Timing for Stream rate of 4.096Mbps when CLK = 16.384MHz . . . . . . . . . . . . . . . . . . . . . 38 Figure 11 - ST-BUS Timing for Stream rate of 4.096Mbps when CLK = 8.192MHz. . . . . . . . . . . . . . . . . . . . . . . 38 Figure 12 - ST-BUS Timing for Stream rate of 2.048Mbps when CLK = 16.384MHz. . . . . . . . . . . . . . . . . . . . . 39 Figure 13 - -BUS Timing for Stream rate of 2.048Mbps when CLK = 8.192MHz. . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 14 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 15 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 16 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 1 - Stream Usage under Various Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2 - Output High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5 - Control Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6 - Serial Data Rate Selections and External Clock Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7 - Frame Alignment (FAR) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8 - Frame Delay Offset Register (DOS) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 10 - Frame Output Offset (FOR) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11 - Output Offset Bits (FD9, FD2-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12 - Bit Error Input Selection (BISR) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13 - Bit Error Count (BECR) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 14 - Connection Memory Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 15 - SAB and CAB Bits Programming for Various Interface Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Changes Summary

The following table captures the changes from the April 2005 issue.

Page Item Change

26Figure6 “Examples for Input Offset Delay Timing”Clarified the mid-point sampling of the 16Mbps input data.

30Section 9.0 Initialization of the

MT90826Added the 600μs waiting time needed for the APLL module to be stabilized before starting the next microprocessor port access cycle.

37 AC Electrical Characteristics - Serial

Streams for ST-BUS.Clarified the 16, 8, 4 and 2Mbps Input Data Sampling timing.

37Figure8 “ST-BUS Timing for Stream rate of 16.384Mbps”Clarified the input data sampling position at 16Mbps data rate.

38Figure9 “ST-BUS Timing for Stream rate of 8.192Mbps when CLK =

16.384MHz”Added the input data sampling position at 8Mbps data rate.

38Figure10 “ST-BUS Timing for Stream rate of 4.096Mbps when CLK =

16.384MHz”Added the input data sampling position at 4Mbps data rate.

39Figure12 “ST-BUS Timing for Stream rate of 2.048Mbps when CLK =

16.384MHz”Added the input data sampling position at 2Mbps data rate.

Figure 2 - 160-Pin MQFP Pin Connections

S T o 16S T o 17S T o 18S T o 19S T o 20S T o 21STo22STo23ODE STo24STo25STo26STi0/FEi0STi1/FEi1STi2/FEi2STi3/FEi3STi4/FEi4STi5/FEi5STi6/FEi6STi7/FEi7STi8/FEi8STi9/FEi9S T i 10/F E i 10S T i 12/F E i 12A 3T C K T D O A 8A 9A 10A 11A 12A 13A 2STo27STo28STo29STo30STo31S T i 11/F E i 11S T i 15/F E i 15S T i 14/F E i 14S T i 13/F E i 13T D I D1D3D4D5D6D7D 9D 10D 11D 12D 13D T A T R S T D2D0IC1T M S 160 Pin MQFP RESET 103109111

113

101

117

115

107105119

1351411431451271291311331491231471251211391371515755535149656763

6159474543697141

171513119252723211975329311S T i 16/F E i 16S T i 17/F E i 17S T i 18/F E i 18S T i 19/F E i 19S T i 20/F E i 20V S S S T i 21/F E i 21S T i 22/F E i 22S T i 23/F E i 23STi24/FEi24STi25/FEi25STI26/FEi26STi27/FEi27

STi28/FEi28STi29/FEi29STi31/FEi31

VSS VDD CLK VSS S T o 13S T o 12STo7STo6STo5STo4STo3VDD V S S D8A 4IC2S T o 8S T o 15S T o 14S T o 987

S T o 1033353739

C S R /W

D S A 0A 1153157155159

S T o 11D 14D 1573757779F0i PLLGND NC IC3VDD

VSS V D D V S S VSS NC

NC PLLVDD V D D VDD

VSS V S S V S S V S S V S S V D D VSS VDD VSS

VSS VDD VSS VDD V D D V S S V D D V S S STi30/FEi30STo2VSS STo0STo1NC

VSS V D D N C VSS

N C

NC NC A 7A 6A 5N C V S S N C N C N C 28mm x 28mm Pin Pitch 0.65mm

Figure 3 - 160 Ball PBGA Pin Connections

12345678910111213

1 - A1 corner is identified by metallized markings.

STo22

STo24STo27

STi29

STi31

STo30

STo31

D10

D13

D11

D14

D12

D15

R/W

TMS

A12

A13

TDO

TCK

IC1RESET

IC2IC3

CLK

F0i

ODE

STi0

STi1

STi2

STi6

STi7

STo4

STo2

STo5

STo6

STo3

STo7

STi12

STi15

STo16

PLLGND

STi13

A10

PLLVDD STo0STi14

VDD

GND

VDD

GND

VDD

VDD VDD

VDD

GND

GND STi26

STi24STo20

STi22STi20

STi18

STi16

STo15

STo13

STo10STo8STi10

STi9

STi27

STi25

STo21

STi23

STi21

STi19STi17

STo14

STo12

STo11

STo9STi11

STi8

STo26STo25

STo23

STo19

STo18STo17GND

GND

STi28

STi30

STi3STo1

STi4

STi5

STo28STo29

DTA

A11

TDI

TRST

23mm x 23mm TOP VIEW

Ball Pitch 1.5mm

PINOUT DIAGRAM: (as viewed through top of package)

A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner

123456789101112

A STo23STo20STi21STi20STi17STi16STo14STo13STo11STo9STi11STi9

B STo22STo21STi23STi22STi19STi18STo15STo12STo10STo8STI10STi8

C STi26STi25STo24STo19STo18STo17STo16STi14STi13STi12STo7STo5

D STi27STi24STo25GND VDD VDD VDD STi15GND STo2STo6STo4

E STi29STi28STo27STo26GND GND GND GND VDD STo3STi7STi6

F STi30STi31STo28VDD GND GND GND GND VDD STo1STi4STi5

G STo30STo31STo29VDD GND GND GND GND PLLVDD STo0STi3STi2

H D1D2D0VDD GND GND GND GND PLLGND ODE STi0STi1

J D3D7D4GND DS VDD VDD VDD NC NC FOi CLK K D5D15D11D13CS A2A5A8A9RESET IC1IC3 L D6D8D9R/W A13A1A4A10A12TCK TDO IC2 M D10D12D14DTA A0A3A6A7A11TMS TDI TRST

Figure 4 - 144 Ball LBGA Pin Connections

Pin Description

Pin # MQFP Pin # PBGA Pin # LBGA Name Description

12,22,33,54, 66,77,90,101, 112,125,136, 147,157D5,D6,D7,D8,D9,

E4,E10,F4,

F10,G4,G10,

H4,J4,J10,K5,

K6,K7

D5,D6,D7,E9,

F4,F9,G4,H4,

J6,J7,J8

V DD+3.3 Volt Power Supply.

11,21,32,45, 53,60,65,71, 76,84,89,95, 100,106,111, 117,124,130, 135,141,146,

156D4,D10,E5,E6,

E7,E8,E9,F5,

F9,G5,G9,H5,

H9,H10,J5,J6,

J7,J8,J9,K4

D4,D9,E5,E6,

E7,E8,F5,F6,

F7,F8,G5,G6,

G7,G8,H5,H6,

H7,H8,J4

V ss Ground.

34N11M10TMS Test Mode Select (3.3 V Input with

Internal pull-up). JTAG signal that

controls the state transitions of the TAP

controller. This pin is pulled high by an

internal pull-up when not driven.

35M11M11TDI Test Serial Data In (3.3 V Input with

Internal pull-up). JTAG serial test

instructions and data are shifted in on

this pin. This pin is pulled high by an

internal pull-up when not driven.

36N12L11TDO Test Serial Data Out (3.3 V Output).

JTAG serial data is output on this pin

on the falling edge of TCK. This pin is

held in high impedance state when

JTAG scan is not enabled.

37N13L10TCK Test Clock (5 V Tolerant Input).

Provides the clock to the JTAG test

logic.

38M12M12TRST Test Reset (3.3 V Input with internal

pull-up). Asynchronously initializes the

JTAG TAP controller by putting it in the

Test-Logic-Reset state. This pin is

pulled by an internal pull-up when not

driven. This pin should be pulsed low

on power-up, or held low, to ensure that

the device is in the normal functional

mode.

42L11K11IC1Internal Connection 1 (3.3 V Input

with internal pull-down). Connect to

V SS for normal operation.

43M13K10RESET Device Reset (5 V Tolerant Input).

This input (active LOW) puts the device

in its reset state which clears the

device internal counters and registers.

44L12L12IC2Internal Connection 2 (3.3 V Input

with internal pull-down). Connect to

V SS for normal operation.

46L13K12IC3Internal Connection 3 (3.3 V Input

with internal pull-down). Connect to

V SS for normal operation.

47K12J11F0i Master Frame Pulse (5 V Tolerant

Input). This input accepts a 122ns or

60ns wide negative frame pulse. The

CPLL bit in the control register

determines the usage of the frame

pulse width. See Table 6 for details.

50K10H9PLLGND Phase Lock Loop Ground.

51K9G9PLLVDD Phase Lock Loop Power Supply.

3.3V

52K13J12CLK Master Clock (5V Tolerant Input).

Serial clock for shifting data in/out on

the serial streams. This pin accepts a

clock frequency of 8.192MHz or

16.384MHz. The CPLL bit in the

control register determines the usage

of the clock frequency. See Table 6 for

details.

55J13H10ODE Output Drive Enable (5V Tolerant

Input). This is the output-enable

control pin for the STo0 to STo31 serial

outputs. See Table 2 for details.

59 67-70 78,79 82,83 91-94 102-105 113-116 126-129 137-140

H13

H12

G13

G12

F13,F12,E13,E12

B13,A13

A12,B12

C11,C10,C9,C8

A7,B7,A6,B6

A5,B5,A4,B4

A2,B2,A1,B1

E2,F2,E1,F1

H11

H12

G12

G11

F11,F12,E12,E11

B12,A12

B11,A11

C10,C9,C8,D8

A6,A5,B6,B5,

A4,A3,B4,B3

D2,C2,C1,D1

E2,E1,F1,F2

STi0/FEi0,

STi1/FEi1

STi2/FEi2

STi3/FEi3

STi4-7/FEi4-7

STi8-9/FEi8-9

STi10-11/FEi10-11

STi12-15/FEi12-15

STi16-19/FEi16-19

STi20-23/FEi20-23

STi24-27/FEi24-27

STi28-31/FEi28-31

Serial Input Streams 0 to 31 and

Frame Evaluation Inputs 0 to 31 (5V

Tolerant Inputs). Serial data input

streams. These streams may have

data rates of 2.048, 4.096, 8.192 or

16.384Mbps, depending upon the

value programmed at bits DR0 - DR2 in

the control register. In the frame

evaluation mode, they are used as the

frame evaluation inputs.

61-64 72-75 85-88 96-99 107-110 118,119 122,123 131-134 142-145G11,F11,E11,D11

D13,C13,D12,C12

A11,B11,A10,B10

B9,A9,B8,A8

C7,C6,C5,C4

A3,B3

D3,C3

D2,C2,C1,D1

G1,G2,H1,H2

G10,F10,D10,E10

D12,C12,D11,C11

B10,A10,B9,A9

B8,A8,A7,B7

C7,C6,C5,C4

A2,B2

B1,A1

C3,D3,E4,E3

F3,G3,G1,G2

STo0 - 3

STo4 - 7

STo8 - 11

STo12 - 15

STo16 - 19

STo20, STo21

STo22, STo23

STo24 - 27

STo28 - 31

ST-BUS Output 0 to 31 (Three-state

Outputs). Serial data output streams.

These streams may have data rates of

2.048, 4.096, 8.192, or 16.384Mbps,

depending upon the value programmed

at bits DR0 - DR2 in the control

Pin # MQFP Pin # PBGA Pin # LBGA Name Description

1.0 Device Overview

The MT90826 Quad Digital Switch is capable of switching up to 4,096 × 4,096 channels. The MT90826 is designed to switch 64Kbps PCM or N x 64Kbps data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis.

The serial input streams of the MT90826 can have a bit rate of 2.048, 4.096, 8.192 or 16.384Mbps and are arranged in 125μs wide frames, which contain 32, 64,128 or 256 channels, respectively. The data rates on input and output streams match. All inputs and outputs may be programmed to 2.048, 4.096 or 8.192Mbps. STi0-15 and STo0-15 may be set to 16.384Mbps. Combinations of two bit rates, N and 2N are provided. See Table 1.

By using Zarlink’s message mode capability, the microprocessor can access input and output timeslots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS devices.

To correct for backplane delays, the MT90826 has a frame offset calibration function which allows users to measure the frame delay on any of the input streams, This information can then be used to program the input offset dealy for each individual stream. Refer to Table 7, 8, and 9 and Figure 6. In addition, the MT90826 allow users to advance

148 - 153154,1551583 - 78,9

G3,J1,H3,J2,J3,K1,

K2,K3L1

L2,M1,M2,M3,N1,

N2,N3

H3,H1,H2,J1,J3,K1

L1,J2L2

L3,M1,K3,M2,K4

M3,K2

D0 - 5,D6, D7D8D9 - 13D14, D15

Data Bus 0 to 15 (5V Tolerant I/O). These pins form the 16-bit data bus of the microprocessor port.

10M4M4DTA

Data Transfer Acknowledgment (Three-state Output). This output pulses low from tristate to indicate that a databus transfer is complete. A pull-up resistor is required to hold a HIGH level when the pin is tristated.

15N5J5DS

Data Strobe (5V Tolerant Input). This active low input works in conjunction with CS to enable the read and write operations.

14N4L4R/W

Read/Write (5V Tolerant Input). This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.

13M5K5CS

Chip Select (5V Tolerant Input). Active low input used by a microprocessor to activate the microprocessor port.

16 - 2023 - 31

M6,N6,N7,M7,N8N9,N10,M8,M9,L7L8,M10,L9,L10M5,L6,K6,M6,L7,K7,M7,M8,K8,K9,L8,M9,L9,L5

A0 - A4A5 - A13

Address 0 to 13 (5V Tolerant Input). These lines provide the A0 - A13 address lines when accessing the internal registers or memories.1,2,39,40,41,48,49,80,81,120,121,159,160

E3,F3,H11,J11,J12,K8,K11,L3,L4,L5,L6.

J9,J10

No Connect. These pins have to be left unconnected.

Pin # MQFP

Pin # PBGA

Pin # LBGA

Name

Description

the output data position up to 45ns to compensate for the output delay caused by excessive output loading conditions. See Figure7 “Examples for Frame Output Offset Timing”.

Serial Interface Mode Input Stream Input Data Rate Output Stream Output Data Rate 8Mbps STi0-318Mbps STo0-318Mbps

16Mbps STi0-1516Mbps STo0-1516Mbps 4Mbps and 8Mbps STi0-154Mbps STo0-154Mbps

STi15-318Mbps STo16-318Mbps 16Mbps and 8Mbps STi0-1116Mbps STo0-1116Mbps

STi12-198Mbps STo12-198Mbps 4Mbps STi0-314Mbps STo0-314Mbps 2Mbps and 4Mbps STi0-152Mbps STo0-152Mbps

STi16-314Mbps STo16-314Mbps 2Mbps STi0-312Mbps STo0-312Mbps

Table 1 - Stream Usage under Various Operation Modes

ODE pin OSB bit in Control register OE bit in Connection Memory ST-BUS Output Driver 00X High-Z

X X0Per Channel High-Z

101Enable

011Enable

111Enable

Table 2 - Output High Impedance Control

The microport interface is compatible with Motorola non-multiplexed buses. Connection memory locations may be directly written to or read from; data memory locations may be directly read from. A DTA signal is provided to hold the bus until the asynchronous microport operation is queued into the device.

A13A12A11A10A9A8A7A6A5A4A3A2A1A0Location

00000000000000Control Register,CR

00000000000001Frame Alignment Register,FAR

00000000000010Input Offset Selection Register0,DOS0 00000000000011Input Offset Selection Register1,DOS1 00000000000100Input Offset Selection Register2,DOS2 00000000000101Input Offset Selection Register3,DOS3 00000000000110Input Offset Selection Register4,DOS4

Table 3 - Address Map for Registers (A13 = 0)

A13A12A11A10A9A8A7A6A5A4A3A2A1A0Location

00000000000111Input Offset Selection Register5,DOS5 00000000001000Input Offset Selection Register6,DOS6 00000000001001Input Offset Selection Register7,DOS7 00000000001010Frame Output Offset Register,FOR0 00000000001011Frame Output Offset Register,FOR1 00000000001100Frame Output Offset Register,FOR2 00000000001101Frame Output Offset Register,FOR3 00000000001110Unused

00000000001111Unused

00000000010000Unused

00000000010001Bit Error Input Selection Register,BISR 00000000010010Bit Error Count Register,BECR

Table 3 - Address Map for Registers (A13 = 0) (continued)

2.0 Functional Description

A functional Block Diagram of the MT90826 is shown in Figure 1.

2.1 Data and Connection Memory

For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the data memory. Depending upon the selected operation programmed in the control register, the usable data memory may be as large as 4,096 bytes. The sequential addressing of the data memory is performed by an internal counter, which is reset by the input 8kHz frame pulse (F0i) to mark the frame boundaries of the incoming serial data streams.

Data to be output on the serial streams may come from either the data memory or connection memory. Locations in the connection memory are associated with particular ST-BUS output channels. When a channel is due to be transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular channel on a serial output stream is read from the data memory or connection memory during the previous channel timeslot. This allows enough time for memory access and parallel-to-serial conversion.

2.2 Connection and Message Modes

In the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream.

By having several output channels connected to the same input source channel, data can be broadcast from one input channel to several output channels.

In message mode, the microprocessor writes data to the connection memory locations corresponding to the output stream and channel number. The lower half (8 least significant bits) of the connection memory content is

transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame until the data is changed by the microprocessor.

The three most significant bits of the connection memory controls the following for an output channel: message or connection mode, constant or variable delay mode, enables/tristate the ST-BUS output drivers and bit error test pattern enable. If an output channel is set to a high-impedance state by setting the OE bit to zero in the connection memory, the ST-BUS output will be in a high impedance state for the duration of that channel. In addition to the per-channel control, all channels on the ST-BUS outputs can be placed in a high impedance state by pulling the ODE input pin low and programming the output stand by (OSB) bit in the control register to low. This action overrides the individual per-channel programming by the connection memory bits. See Table 2 for detail.

The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The addressing of the device internal registers, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register.

2.3 Clock Timing Requirements

The master clock (CLK) frequency must be either at 8.192MHz or 16.384MHz for serial data rate of 2.048, 4.096, 8.192 and 16.384Mbps; see Table 6 for the selections of the master clock frequency.

3.0 Switching Configurations

The MT90826 maximum non-blocking switching configurations is determined by the data rates selected for the serial inputs and outputs. The switching configuration is selected by three DR bits in the control register. See Table 5 and Table 6.

8Mbps mode (DR2=0, DR1=0, DR0=0)

When the 8Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 128 64Kbps channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels. Table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies.

16Mbps mode (DR2=0, DR1=0, DR0 =1)

When the 16Mbps mode is selected, the device is configured with 16-input/16-output data streams each having 256 64Kbps channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels.

4Mbps and 8Mbps mode (DR2=0, DR1=1, DR0=0)

When the 4Mbps and 8Mbps mode is selected, the device is configured with 32-input/32-output data streams. STi0-15/STo0-15 have a data rate of 4Mbps and STi16-31/STo16-31 have a data rate of 8Mbps. This mode allows a maximum non-blocking capacity of 3,072 x 3,072 channels. The MT90826 is capable of rate conversion, allowing 4Mbps input to be converted to 8Mbps output and vice versa.

16Mbps and 8Mbps mode (DR2=0, DR1=1, DR0=1)

When the 16Mbps and 8Mbps mode is selected, the device is configured with 20-input/20-output data streams. STi0-11/STo0-11 have a data rate of 16Mbps and STi12-19/STo12-19 have a data rate of 8Mbps. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels. The MT90826 is capable of rate conversion, allowing 16Mbps input to be converted to 8Mbps output and vice versa.

4Mbps mode (DR2=1, DR1=0, DR0=0)

When the 4Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 64 64Kbps channels. This mode allows a maximum non-blocking capacity of 2,048 x 2,048 channels.

2Mbps and 4Mbps mode (DR2=1, DR1=0, DR0=1)

When the 2Mbps and 4Mbps mode is selected, the device is configured with 32-input/32-output data streams. STi0-15/STo0-15 have a data rate of 2Mbps and STi16-31/STo16-31 have a data rate of 4Mbps. This mode allows a maximum non-blocking capacity of 1,536 x 1,536 channels. The MT90826 is capable of rate conversion, allowing 2Mbps input to be converted to 4Mbps output and vice versa.

2Mbps mode (DR2=1, DR1=1, DR0 =0)

When the 2Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 32 64Kbps channels. This mode allows a maximum non-blocking capacity of 1,024 x 1,024 channels.

3.1 Serial Input Frame Alignment Evaluation

The MT90826 provides the frame evaluation inputs, FEi0 to FEi31, to determine different data input delays with respect to the frame pulse F0i. By using the frame evaluation input select bits (FE0 to FE4) of the frame alignment register (FAR), users can select one of the thirty-two frame evaluation inputs for the frame alignment measurement.

The internal master clock, which has a fixed relationship with the CLK and F0i depending upon the mode of operation, is used as the reference timing signal to determine the input frame delays. See Figure 5 for the signal alignments between the internal and the external master clocks.

A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the control register is changed from low to high. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started.

The falling edge of the frame measurement signal (FEi) is evaluated against the falling edge of the frame pulse (F0i). See Table 7 for the description of the frame alignment register.

3.2 Input Frame Offset Selection

Input frame offset selection allows the channel alignment of individual input streams, which operate at 4.096Mbps, 8.192Mbps or 16.384Mbps, to be shifted against the input frame pulse (F0i). The input offset selection is not available for streams operated at 2.048Mbps. This feature is useful in compensating for variable path delays caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching systems.

Each input stream has its own delay offset value programmed by the input delay offset registers. Each delay offset register can control 4 input streams. There are eight delay offset registers (DOS0 to DOS7) to control 32 input streams. Possible adjustment can range up to +4.5 internal master clock periods forward with resolution of 0.5 internal master clock period. See Table 8 and Table 9 for frame input delay offset programming.

3.3 Output Advance Offset Selection

The MT90826 allows users to advance individual output streams up to 45ns with a resolution of 15ns when the device is in 8Mbps, 16Mbps, 4 and 8Mbps or 16 and 8Mbps mode. The output delay adjustment is useful in compensating for variable output delays caused by various output loading conditions. The frame output offset registers (FOR0 & FOR3) control the output offset delays for each output streams via the programming of the OFn bits.

See Table 10 and Table 11 for the frame output offset programming.

3.4 Memory Block Programming

The MT90826 provides users with the capability of initializing the entire connection memory block in two frames.Bits 13 to 15 of every connection memory location will be programmed with the pattern stored in bits 13 to 15 of the control register.

The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the control register is set to high, the block programming data will be loaded into the bits 13 to 15 of every connection memory location. The other connection memory bits (bit 0 to 12) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero.

3.5 Bit Error Rate Monitoring

The MT90826 allows users to perform bit error rate monitoring by sending a pseudo random pattern to a selected ST-BUS output channel and receiving the pattern from a selected ST-BUS input channel. The pseudo random pattern is internally generated by the device with the polynomial of 215 -1.

Users can select the pseudo random pattern to be presented on a ST-BUS channel by programming the TM0 and TM1 bits in the connection memory. When TM0 and TM1 bits are high, the pseudo random pattern is output to the selected ST-BUS output channel. The pseudo random pattern is then received by a ST-BUS input channel which is selected using the BSA and BCA bits in the bit error rate input selection register (BISR). An internal bit error counter keeps track of the error counts which is then stored in the bit error count register (BECR).

The bit error test is enabled and disabled by the SBER bit in the control register. Setting the bit from zero to one initiates the bit error test and enables the internal bit error counter. When the bit is programmed from one to zero,

A13Stream Address (ST0-31)

Channel Address (Ch0-255)A12A11A10A9A8Stream Location A7A6A5A4A3A2A1A0Channel Location 111111111 (1111111111)

000000000 (1111111111)

000000001 (0011111111)

000011110 (1100001111)

001100110 (1100110011)

010101010 (010*******)

Stream 0Stream 1Stream 2Stream 3Stream 4Stream 5Stream 6Stream 7Stream 8...

Stream 22Stream 23Stream 24Stream 25Stream 26Stream 27Stream 28Stream 29Stream 30Stream 31

00..0000..0000.0011.11

00..0000..0011.1100.11

00..0011..1100.1100.11

00..1100..1100.1100.11

01..0101..0101.0101.01

Ch 0Ch 1..

Ch 30

Ch 31 (Note 2)Ch 32Ch 33..

Ch 62

Ch 63 (Note 3)Ch 64Ch 65.

Ch 126

Ch 127 (Note 4)Ch 128Ch 129.

Ch 254

Ch 255 (Note 5)

1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.

2. Channels 0 to 31 are used when serial stream is at 2Mbps.

3. Channels 0 to 63 are used when serial stream is at 4Mbps

4. Channels 0 to 127 are used when serial stream is at 8Mbps

5. Channels 0 to 255 are used when serial stream is at 16Mbps

Table 4 - Address Map for Memory Locations (A13 = 1)

the device stops the bit error rate test and the internal bit error counter and transfers the error counts to the bit error count register.

In the control register, a zero to one transition of the CBER bit resets the bit error count register and the internal bit error counter.

The MT90826 does not recognize an input of all 1s as an error. If all 1s are being fed into the input stream and channel, the BERT on chip BECR does not increment. This test is performed by sending defined data through the message mode to ensure there is proper connectivity, and then running the BER test normally.

4.0 Delay Through the MT90826

The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform timeslot interchange functions with different throughput delay capabilities on the per-channel basis. For voice application, select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch.

The delay through the device varies according to the type of throughput delay selected by the TM bits in the connection memory.

4.1 Variable Delay Mode (TM1=0, TM0=0)

The delay in this mode is dependent only on the combination of source and destination channels and is independent of input and output streams. The delay through the switch can vary from 3 channels to 1 frame + 3 channels. The Variable delay is only available for odd number output streams but not for the even number output streams. Avoid programming the TM0 and TM1 bits to zero in the connection memory when the destination output streams are STo0, 2, 4, ..., 28 and 30.

4.2 Constant Delay Mode (TM1=1, TM0=0)

In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. The delay through the switch is always two frames. The constant delay mode is available for all output streams.

5.0 Microprocessor Interface

The MT90826 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed buses. The required microprocessor signals are the 16-bit data bus (D0-D15), 14-bit address bus (A0-A13) and 4 control lines (CS, DS, R/W and DTA). See Figure 16 for Motorola non-multiplexed microport timing.

The MT90826 microport provides access to the internal registers, connection and data memories. All locations provide read/write access except for the data memory and BECR registers which are read only.

For data memory read operations, two consecutive microprocessor cycles are required. The read address (A0-A13) should remain the same for the two consecutive read cycles. The data memory content from the first read cycle should be ignored.

Bit Name Description

15 - 13

BPD2-0

Block Programming Data. These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is

activated. After the MBP bit is set to 1 and the BPE bit is set to 1, the contents of the bits BPD2- 0 are loaded into bit 15 to bit 13 of the connection memory. Bit 12 to bit 0 of the connection memory are set to 0.12Unused Must be zero for normal operation .

CPLL

PLL Input Frequency Select. When zero or one, the CLK input is 16.384MHz and the F0i input is 60ns wide. When one, the CLK input is 8.192MHz and the F0i input is 122ns wide. See Table 6 for the usage of the clock frequency.

10CBER Clear Bit Error Rate Register . A zero to one transition in this bit resets the internal bit error counter and the bit error count register to zero.

SBER

Start Bit Error Rate Test . A zero to one transition in this bit starts the bit error rate test. The bit error test result is kept in the bit error count register. A one to zero transition stops the bit error rate test and the internal bit error counter.

8SFE

Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the frame alignement (FAR) register changes from zero to one, the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero.

7Unused Must be zero for normal operation.

BPE

Begin Block programming Enable. A zero to one transition of this bit enables the memory block programming function. The BPE and BPD2-0 bits have to be defined in the same write operation. Once the BPE bit is set high, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort the programming operation.

When BPE = 1, the other bits in the control register must not be changed for two frames to ensure proper operation.

5MBP

Memory Block Program. When 1, the connection memory block programming

feature is ready to program Bit13 to Bit15 of the connection memory. When 0, feature is disabled.

Table 5 - Control Register Bits

Read/Write Address: 0000H ,Reset Value:0000H .7

13DR0

DR1

BPE

1415

SFE

OSB

MBP

SBER

BPD2

BPD1BPD0CBER 0

DR2

CPLL

Memory Select. When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read operations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data memory.)

For data memory read operations, two consecutive microprocessor cycles are required. The read address should remain the same for the two consecutive read cycles. The data memory content from the first read cycle should be ignored. The correct data memory content will be presented to the data bus on the second read cycle.

3OSB

Output Stand By. This bit controls the device output drivers. OSB bit ODE pin OE bit STo0 - 31 0 1 1 Enable 1 0 1 Enable 1 1 1 Enable

0 0 X High impedance state

X X 0 Per-channel high impedance

2 - 0DR2-0

Data Rate Select. Input/Output data rate selection. See next table (Table 6) for detailed programming.

DR2DR1DR0Serial Interface Mode

CLK (CPLL=0)CLK (CPLL=1)

0008Mbps 16.384MHz 16.384MHz

00116Mbps 010 4 and 8Mbps 01116 and 8Mbps

1004Mbps 16.384MHz 8.192MHz

101 2 and 4Mbps

2Mbps

16.384MHz 8.192MHz

Table 6 - Serial Data Rate Selections and External Clock Rates

Bit Name Description

Table 5 - Control Register Bits (continued)

Read/Write Address: 0000H ,Reset Value:0000H .7

13DR0

DR1

BPE

1415

SFE

OSB

MBP

SBER

BPD2

BPD1BPD0CBER 0

DR2

CPLL