ATTINY13A-SU中文资料
Features
?High Performance, Low Power AVR? 8-Bit Microcontroller ?Advanced RISC Architecture
–120 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 20 MIPS Througput at 20 MHz
?High Endurance Non-volatile Memory segments
–1K Bytes of In-System Self-programmable Flash program memory
–64 Bytes EEPROM
–64 Bytes Internal SRAM
–Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
–Data retention: 20 Years at 85°C/100 Years at 25°C (see page 6)
–Programming Lock for Self-Programming Flash & EEPROM Data Security ?Peripheral Features
–One 8-bit Timer/Counter with Prescaler and Two PWM Channels
–4-channel, 10-bit ADC with Internal Voltage Reference
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
?Special Microcontroller Features
–debugWIRE On-chip Debug System
–In-System Programmable via SPI Port
–External and Internal Interrupt Sources
–Low Power Idle, ADC Noise Reduction, and Power-down Modes
–Enhanced Power-on Reset Circuit
–Programmable Brown-out Detection Circuit with Software Disable Function –Internal Calibrated Oscillator
?I/O and Packages
–8-pin PDIP/SOIC: Six Programmable I/O Lines
–20-pad MLF: Six Programmable I/O Lines
?Operating Voltage:
–1.8 - 5.5V
?Speed Grade:
–0 - 4 MHz @ 1.8 - 5.5V
–0 - 10 MHz @ 2.7 - 5.5V
–0 - 20 MHz @ 4.5 - 5.5V
?Industrial Temperature Range
?Low Power Consumption
–Active Mode:
?190 μA at 1.8 V and 1 MHz
–Idle Mode:
?24 μA at 1.8 V and 1 MHz 8-bit Microcontroller
with 1K Bytes
In-System Programmable
ATtiny13A
Summary
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ATtiny13A
1.Pin Configurations
Figure 1-1.
Pinout of ATtiny13A
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1.1
Pin Description
1.1.1
VCC
Supply voltage.
1.1.2GND
Ground.
1.1.3
Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny13A as listed on page 55.
1.1.4RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min-imum pulse length is given in Table 18-4 on page 120. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
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ATtiny13A
2.Overview
The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-sumption versus processing speed.
2.1Block Diagram
Figure 2-1.
Block Diagram
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ATtiny13A
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.
The ATtiny13A provides the following features: 1K byte of In-System Programmable Flash, 64bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Inter-rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core.
The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
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3.About
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at https://www.wendangku.net/doc/a010465845.html,/avr.
3.2Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.
3.3Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25?C.
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4.Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F SREG I T H S V N Z C page 90x3E Reserved ––––
––––
0x3D SPL SP[7:0]page 11
0x3C Reserved ––––––––0x3B
GIMSK
–INT0PCIE –––––page 470x3A GIFR –INTF0PCIF –––––page 480x39 TIMSK0––––OCIE0B OCIE0A TOIE0–page 750x38 TIFR0––––OCF0B OCF0A TOV0–page 760x37 SPMCSR –––CTPB RFLB PGWRT
PGERS SELFPR-page 980x36 OCR0A Timer/Counter – Output Compare Register A
page 750x35
MCUCR
–PUD SE SM1SM0–ISC01ISC00page 330x34 MCUSR ––––WDRF BORF EXTRF PORF page 420x33 TCCR0B FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
page 730x32 TCNT0 Timer/Counter (8-bit)page 740x31 OSCCAL Oscillator Calibration Register
page 27
0x30 BODCR ––––––BODS BODSE page 330x2F TCCR0A COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
page 700x2E DWDR DWDR[7:0]
page 97
0x2D Reserved –0x2C Reserved –0x2B Reserved –0x2A Reserved –
0x29
OCR0B
Timer/Counter – Output Compare Register B
page 750x28 GTCCR TSM –––
–
–
–
PSR10
page 780x27 Reserved –
0x26 CLKPR CLKPCE
–––CLKPS3
CLKPS2
CLKPS1CLKPS0page 280x25
PRR
–
–
–
–
–
–
PRTIM0
PRADC
page 34
0x24 Reserved –0x23 Reserved –0x22
Reserved
–
0x21 WDTCR WDTIF
WDTIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
page 42
0x20 Reserved –0x1F Reserved –
0x1E EEARL ––EEPROM Address Register
page 200x1D EEDR EEPROM Data Register
page 200x1C EECR –
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
page 21
0x1B Reserved –0x1A
Reserved
–0x19 Reserved –
0x18 PORTB ––PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0page 570x17DDRB ––DDB5DDB4DDB3DDB2DDB1DDB0page 570x16 PINB ––PINB5PINB4PINB3PINB2PINB1PINB0page 580x15
PCMSK
––PCINT5PCINT4PCINT3PCINT2PCINT1PCINT0page 480x14 DIDR0–
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
page 81, page 95
0x13 Reserved –0x12Reserved –0x11 Reserved –0x10
Reserved
–0x0F Reserved –0x0E Reserved –0x0D Reserved –0x0C Reserved –0x0B Reserved –0x0A Reserved –0x09Reserved –
0x08ACSR ACD ACBG ACO ACI ACIE –ACIS1ACIS0page 800x07ADMUX –REFS0ADLAR –––MUX1MUX0page 920x06ADCSRA ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
page 930x05ADCH ADC Data Register High Byte page 940x04ADCL ADC Data Register Low Byte
page 94
0x03ADCSRB –
ACME
–
–
–
ADTS2
ADTS1
ADTS0
page 95
0x02Reserved –0x01Reserved –0x00
Reserved
–
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Notes:
1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.2.I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
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5.Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S 2SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1SBCI Rd, K Subtract with Carry Constant from Reg.
Rd ← Rd - K - C Z,C,N,V,H 1SBIW Rdl,K Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S 2AND Rd, Rr Logical AND Registers Rd ← Rd ? Rr Z,N,V 1ANDI Rd, K Logical AND Register and Constant
Rd ← Rd ? K Z,N,V 1OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1ORI Rd, K Logical OR Register and Constant
Rd ← Rd v K Z,N,V 1EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1COM Rd One’s Complement Rd ← 0xFF ? Rd Z,C,N,V 1NEG Rd Two’s Complement Rd ← 0x00 ? Rd Z,C,N,V,H 1SBR Rd,K Set Bit(s) in Register Rd ← Rd v K
Z,N,V 1CBR Rd,K Clear Bit(s) in Register
Rd ← Rd ? (0xFF - K)
Z,N,V 1INC Rd Increment Rd ← Rd + 1
Z,N,V 1DEC Rd Decrement Rd ← Rd ? 1 Z,N,V 1TST Rd Test for Zero or Minus
Rd ← Rd ? Rd Z,N,V 1CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1SER Rd
Set Register Rd ← 0xFF None 1BRANCH INSTRUCTIONS
RJMP k
Relative Jump PC ← PC + k + 1
None 2IJMP Indirect Jump to (Z)PC ← Z None 2RCALL k
Relative Subroutine Call PC ← PC + k + 1
None 3ICALL Indirect Call to (Z)PC ←
Z None 3RET Subroutine Return PC ← STACK None 4RETI Interrupt Return PC ← STACK
I 4CPSE Rd,Rr Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None 1/2/3CP Rd,Rr Compare Rd ? Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry
Rd ? Rr ? C Z, N,V,C,H 1CPI Rd,K Compare Register with Immediate Rd ? K
Z, N,V,C,H 1SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None 1/2/3SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3None 1/2/3BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1None 1/2BRBC s, k Branch if Status Flag Cleared
if (SREG(s) = 0) then PC ←PC+k + 1None 1/2BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1/2BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None 1/2BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1/2BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1/2BRSH k Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1None 1/2BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1/2BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1/2BRPL k Branch if Plus
if (N = 0) then PC ← PC + k + 1None 1/2BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None 1/2BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None 1/2BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1None 1/2BRHC k Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1None 1/2BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None 1/2BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None 1/2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1/2BRVC k Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1None 1/2BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1None 1/2BRID k Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None 1/2BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ←
1None 2CBI P,b Clear Bit in I/O Register
I/O(P,b) ← 0
None 2LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V 1LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V 1ROL
Rd Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C ←Rd(7)
Z,C,N,V
1
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ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C ←Rd(0)
Z,C,N,V 1ASR Rd Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V 1SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None 1BSET s Flag Set SREG(s) ← 1
SREG(s)1BCLR s Flag Clear
SREG(s) ← 0 SREG(s)
1BST Rr, b Bit Store from Register to T T ← Rr(b)T 1BLD Rd, b
Bit load from T to Register
Rd(b) ←
T None 1SEC Set Carry C ←
1C 1CLC Clear Carry C ← 0 C 1SEN Set Negative Flag N ←
1N 1CLN Clear Negative Flag N ← 0 N 1SEZ Set Zero Flag Z ← 1Z 1CLZ Clear Zero Flag Z ← 0 Z 1SEI Global Interrupt Enable I ←
1I 1CLI Global Interrupt Disable I ← 0 I 1SES Set Signed Test Flag S ←
1S 1CLS Clear Signed Test Flag S ← 0 S 1SEV Set Twos Complement Overflow.V ← 1V 1CLV Clear Twos Complement Overflow
V ← 0 V 1SET Set T in SREG T ←
1T 1CLT Clear T in SREG
T ← 0
T 1SEH Set Half Carry Flag in SREG H ←
1
H 1CLH Clear Half Carry Flag in SREG
H ← 0 H 1DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr
None 1MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1LDI Rd, K Load Immediate Rd ← K
None 1LD Rd, X Load Indirect
Rd ← (X)
None 2LD Rd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None 2LD Rd, - X Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)None 2LD Rd, Y Load Indirect
Rd ← (Y)
None 2LD Rd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1
None 2LD Rd, - Y Load Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None 2LDD Rd,Y+q Load Indirect with Displacement
Rd ← (Y + q)None 2LD Rd, Z Load Indirect
Rd ← (Z)
None 2LD Rd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None 2LD Rd, -Z Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)
None 2LDD Rd, Z+q Load Indirect with Displacement
Rd ← (Z + q)None 2LDS Rd, k Load Direct from SRAM
Rd ← (k)None 2ST X, Rr Store Indirect
(X) ← Rr None 2ST X+, Rr Store Indirect and Post-Inc.(X) ← Rr, X ← X + 1None 2ST - X, Rr Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None 2ST Y, Rr Store Indirect
(Y) ← Rr None 2ST Y+, Rr Store Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None 2ST - Y, Rr Store Indirect and Pre-Dec.Y ← Y - 1, (Y) ← Rr
None 2STD Y+q,Rr Store Indirect with Displacement
(Y + q) ← Rr None 2ST Z, Rr Store Indirect
(Z) ← Rr None 2ST Z+, Rr Store Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None 2ST -Z, Rr Store Indirect and Pre-Dec.Z ← Z - 1, (Z) ← Rr
None 2STD Z+q,Rr Store Indirect with Displacement
(Z + q) ← Rr None 2STS k, Rr Store Direct to SRAM (k) ← Rr None 2LPM Load Program Memory R0 ← (Z)None 3LPM Rd, Z Load Program Memory Rd ← (Z)None 3LPM Rd, Z+Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None 3SPM Store Program Memory
(z) ← R1:R0None IN Rd, P In Port Rd ←
P None 1OUT P, Rr Out Port
P ← Rr None 1PUSH Rr Push Register on Stack STACK ← Rr None 2POP Rd
Pop Register from Stack
Rd ← STACK
None 2MCU CONTROL INSTRUCTIONS
NOP No Operation
None
1SLEEP Sleep (see specific descr. for Sleep function)None 1WDR Watchdog Reset
(see specific descr. for WDR/Timer)
None 1BREAK
Break
For On-chip Debug Only
None
N/A
Mnemonics
Operands
Description
Operation
Flags
#Clocks
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6.Ordering Information
Notes:
1.For device speed vs. V CC , see “Speed Grades” on page 118.
2.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.3.All packages are Pb-free, Halide-free, fully green and they comply with the European directive for Restriction of Hazardous
Substances (RoHS).
Speed (MHz) (1)
Power Supply (V) (1)
Ordering Code Package (2) (3)
Operation Range
20 1.8 - 5.5
A Ttiny13A-PU A Ttiny13A-SU A Ttiny13A-SH A Ttiny13A-SSU A Ttiny13A-SSH A Ttiny13A-MU A Ttiny13A-MMU
8P38S28S28S18S120M110M1
Industrial (-40?C to 85?C)
Package Type
8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S28-lead, 0.209" Wide, Plastic Small Outline Package (EIAJ SOIC)8S18-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20M120-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)10M1
10-pad, 3 x 3 x 1 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
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7.Packaging Information
7.1
8P3
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7.2
8S2
14
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7.38S1
15
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ATtiny13A
7.4
20M1
16
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7.510M1
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8.Errata
The revision letters in this section refer to the revision of the ATtiny13A device.
8.1ATtiny13A Rev. G – H
No known errata.
8.2ATtiny13A Rev. E – F
These device revisions were not sampled.
8.3ATtiny13A Rev. A – D
These device revisions were referred to as ATtiny13/ATtiny13V.
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ATtiny13A
9.Datasheet Revision History
Please note that page numbers in this section refer to the current version of this document and may not apply to previous versions.
9.1Rev. 8126B – 11/08
1.Updated order codes on page 11 to reflect changes in material composition.
2.Updated sections:
–“DIDR0 – Digital Input Disable Register 0” on page 81–“DIDR0 – Digital Input Disable Register 0” on page 953.Updated “Register Summary” on page 7.
9.2Rev. 8126A – 05/08
1.Initial revision, created from document 2535I – 04/08.
2.Updated characteristic plots of section “Typical Characteristics” , starting on page 124.
3.Updated “Ordering Information” on page 11.
4.Updated section:
–“Speed Grades” on page 1185.Update tables:
–“DC Characteristics, T A = -40?C to 85?C” on page 117–“Calibration Accuracy of Internal RC Oscillator” on page 119
–“Reset, Brown-out, and Internal Voltage Characteristics” on page 120
–“ADC Characteristics, Single Ended Channels. TA = -40?C - 85?C” on page 121–“Serial Programming Characteristics, T A = -40?C to 85?C” on page 1226.Added description of new function, “Power Reduction Register”:
–Added functional description on page 31–Added bit description on page 34
–Added section “Supply Current of I/O Modules” on page 124–Updated Register Summary on page 7
7.Added description of new function, “Software BOD Disable”:
–Added functional description on page 31–Updated section on page 32
–Added register description on page 33–Updated Register Summary on page 7
8.Added description of enhanced function, “Enhanced Power-On Reset”:
–Updated Table 18-4 on page 120, and Table 18-5 on page 120
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8126BS–AVR–12/08
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