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SN74LVC07ADBR

https://www.wendangku.net/doc/b42770350.html, FEATURES

SN74LVC07A...RGY PACKAGE (TOP VIEW)11478234561312111096A 6Y 5A 5Y 4A 1Y 2A 2Y 3A 3Y 1A 4Y

V G N D

C C 1234567141312111098

GND V CC 6A 6Y 5A 5Y 4A 4Y SN54LVC07A...J OR W PACKAGE

SN74LVC07A...D, DB, DGV, NS,

OR PW PACKAGE

(TOP VIEW)32120199101112134567818171615146Y NC 5A NC 5Y 2A NC 2Y NC 3A SN54LVC07A...FK PACKAGE (TOP VIEW)1Y 1A N C 4Y 4A 6A 3Y G N D N C V C C NC - No internal connection

DESCRIPTION/ORDERING INFORMATION

SN54LVC07A,SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595O–OCTOBER 1997–REVISED JULY 2005?

Operate From 1.65V to 5V ?Max t pd of 2.6ns at 5V ?Inputs and Open-Drain Outputs Accept

?Latch-Up Performance Exceeds 250mA Per Voltages up to 5.5V

JESD 17These hex buffers/drivers are designed for 1.65-V to 5.5-V V CC operation.

The outputs of the 'LVC07A devices are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.The maximum sink current is 24mA.

Inputs can be driven from 1.8-V,2.5-V,3.3-V (LVTTL),or 5-V (CMOS)devices.This feature allows the use of these devices as translators in a mixed-system environment.

ORDERING INFORMATION

T A

PACKAGE (1)ORDERABLE PART NUMBER TOP-SIDE MARKING QFN –RGY

Reel of 1000SN74LVC07ARGYR LC07A Tube of 50SN74LVC07AD SOIC –D

Reel of 2500SN74LVC07ADR LVC07A Reel of 250SN74LVC07ADT SOP –NS

Reel of 2000SN74LVC07ANSR LVC07A –40°C to 85°C SSOP –DB

Reel of 2000SN74LVC07ADBR LC07A Tube of 90SN74LVC07APW TSSOP –PW

Reel of 2000SN74LVC07APWR LC07A Reel of 250SN74LVC07APWT TVSOP –DGV

Reel of 2000SN74LVC07ADGVR LC07A CDIP –J

Tube of 25SNJ54LVC07AJ SNJ54LVC07AJ –55°C to 125°C CFP –W

Tube of 150SNJ54LVC07AW SNJ54LVC07AW LCCC –FK

Tube of 55SNJ54LVC07AFK SNJ54LVC07AFK (1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at

https://www.wendangku.net/doc/b42770350.html,/sc/package.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Absolute Maximum Ratings (1)

SN54LVC07A,SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS

SCAS595O–OCTOBER 1997–REVISED JULY 2005FUNCTION TABLE (EACH BUFFER/DRIVER)

INPUT

OUTPUT A

Y H

H L L

LOGIC DIAGRAM,EACH BUFFER/DRIVER (POSITIVE LOGIC)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT V CC

Supply voltage range –0.5 6.5V V I

Input voltage range (2)–0.5 6.5V V O

Output voltage range –0.5 6.5V I IK

Input clamp current V I <0–50mA I OK

Output clamp current V O <0–50mA I O Continuous output current

±50mA Continuous current through V CC or GND

±100mA D package (3)

86DB package

(3)96DGV package (3)127

θJA Package thermal impedance °C/W

NS package (3)76

PW package (3)113

RGY package (4)47T stg

Storage temperature range –65150°C (1)

Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)

The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3)

The package thermal impedance is calculated in accordance with JESD 51-7.(4)The package thermal impedance is calculated in accordance with JESD 51-5.

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Recommended Operating Conditions(1) Electrical Characteristics

SN54LVC07A,SN74LVC07A

HEX BUFFERS/DRIVERS

WITH OPEN-DRAIN OUTPUTS SCAS595O–OCTOBER1997–REVISED JULY2005

SN54LVC07A(2)SN74LVC07A

UNIT MIN MAX MIN MAX

V CC Supply voltage 1.65 5.5 1.65 5.5V

V CC=1.65V to1.95V0.65×V CC0.65×V CC

V CC=2.3V to2.7V 1.7 1.7

V IH High-level input voltage V

V CC=2.7V to3.6V22

V CC=4.5V to5.5V0.7×V CC0.7×V CC

V CC=1.65V to1.95V0.35×V CC0.35×V CC

V CC=2.3V to2.7V0.70.7

V IL Low-level input voltage V

V CC=2.7V to3.6V0.80.8

V CC=4.5V to5.5V0.3×V CC0.3×V CC

V I Input voltage0 5.50 5.5V

V O Output voltage0 5.50 5.5V

V CC=1.65V44

V CC=2.3V1212

I OL Low-level output current V CC=2.7V1212mA

V CC=3V2424

V CC=4.5V2424

T A Operating free-air temperature–55125–4085°C (1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs,literature number SCBA004.

(2)Product preview

over recommended operating free-air temperature range(unless otherwise noted)

SN54LVC07A(1)SN74LVC07A PARAMETER TEST CONDITIONS V CC UNIT

MIN TYP(2)MAX MIN TYP(2)MAX

I OL=100μA 1.65V to5.5V0.20.2

I OL=4mA 1.65V0.450.45

2.3V0.70.7

V OL I OL=12mA V

2.7V0.40.4

3V0.550.55

I OL=24mA

4.5V

I I V I=5.5V or GND 3.6V±5±5μA

I CC V I=V CC or GND,I O=0 3.6V1010μA

One input at V CC–0.6V,

?I CC 2.7V to3.6V500500μA Other inputs at V CC or GND

C i V I=V CC or GN

D 3.3V55pF

(1)Product preview

(2)All typical values are at V CC=3.3V,T A=25°C.

https://www.wendangku.net/doc/b42770350.html, Switching Characteristics

Switching Characteristics

Operating Characteristics

SN54LVC07A,SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS

SCAS595O–OCTOBER 1997–REVISED JULY 2005over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 4)

SN54LVC07A (1)

FROM

TO V CC =1.8V V CC =2.5V V CC =3.3V V CC =5V PARAMETER V CC =2.7V UNIT

(INPUT)

(OUTPUT)±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t pd

A Y 1 3.51 2.831 2.91 2.6ns (1)Product preview over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 4)

SN74LVC07A

FROM

TO V CC =1.8V V CC =2.5V V CC =3.3V V CC =5V PARAMETER V CC =2.7V UNIT

(INPUT)

(OUTPUT)±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t pd A Y 1 3.51 2.831 2.91 2.6ns T A =25°C

V CC =1.8V V CC =2.5V V CC =3.3V V CC =5V TEST PARAMETER

UNIT CONDITIONS TYP TYP TYP TYP Power dissipation capacitance C pd f =10MHz 1.82 2.5 3.78pF per buffer/driver

https://www.wendangku.net/doc/b42770350.html, PARAMETER MEASUREMENT INFORMATION t PZL (see Note F)t PLZ (see Note G)

t PHZ /t PZH 2 × V CC 2 × V CC 2 × V CC

TEST S1

V CC V OL From Output

Under Test

C L LOA

D CIRCUIT

Open Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CC (see Note B)Output Waveform 2S1 at 2 × V CC (see Note B)0 V 0 V V CC

0 V

V CC V CC VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data

Input Input NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2 ns, t f ≤ 2 ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.Since this device has open-drain outputs, t PLZ and t PZL are the same as t pd .

F.t PZL is measured at V CC /2.

G.t PLZ is measured at V OL + 0.15 V.

H.All parameters and waveforms are not applicable to all devices.

0 V V CC Input Output VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES × V CC

V CC SN54LVC07A,SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595O–OCTOBER 1997–REVISED JULY 2005

V CC =1.8V ±0.15V

Figure 1.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION t PZL (see Note F)t PLZ (see Note G)

t PHZ /t PZH 2 × V CC 2 × V CC 2 × V CC

TEST S1

V CC V OL From Output

Under Test

C L LOA

D CIRCUIT

Open Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CC (see Note B)Output Waveform 2S1 at 2 × V CC (see Note B)0 V 0 V V CC

0 V

V CC V CC VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data

Input Input NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2 ns, t f ≤ 2 ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.Since this device has open-drain outputs, t PLZ and t PZL are the same as t pd .

F.t PZL is measured at V CC /2.

G.t PLZ is measured at V OL + 0.15 V.

H.All parameters and waveforms are not applicable to all devices.

0 V V CC Input Output VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES × V CC

V CC SN54LVC07A,SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS

SCAS595O–OCTOBER 1997–REVISED JULY 2005V CC =2.5V ±0.2V

Figure 2.Load Circuit and Voltage Waveforms

https://www.wendangku.net/doc/b42770350.html, PARAMETER MEASUREMENT INFORMATION

3 V V OL From Output

Under Test

C L LOA

D CIRCUIT

Open Output Control (low-level enabling)Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at 6 V (see Note B)0 V 0 V 2.7 V

0 V

2.7 V 2.7 V 3 V VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input

Data

Input Input t PZL (see Note F)t PLZ (see Note G)

t PHZ /t PZH 6 V 6 V 6 V

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.Since this device has open-drain outputs, t PLZ and t PZL are the same as t pd .

F.t PZL is measured at 1.5 V.

G.t PLZ is measured at V OL + 0.3 V.

H.All parameters and waveforms are not applicable to all devices.

0 V 2.7 V Input Output VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES SN54LVC07A,SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595O–OCTOBER 1997–REVISED JULY 2005

V CC =2.7and 3.3V ±0.3V

Figure 3.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION

V CC

3.5 V V OL From Output

Under Test

C L LOA

D CIRCUIT

Open Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CC (see Note B)Output Waveform 2S1 at 7 V (see Note B)0 V 0 V 3 V

0 V

3 V V CC V CC VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input

Data

Input Input t PZL (see Note F)t PLZ (see Note G)

t PHZ /t PZH 2 × V CC 2 × V CC 7 V

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.Since this device has open-drain outputs, t PLZ and t PZL are the same as t pd .

F.t PZL is measured at V CC /2.

G.t PLZ is measured at V OL + 0.3 V.

H.All parameters and waveforms are not applicable to all devices.

0 V 3 V Input Output VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES SN54LVC07A,SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS

SCAS595O–OCTOBER 1997–REVISED JULY 2005V CC =5V ±0.5V

Figure 4.Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status(1)Package

Type Package

Drawing

Pins Package

Qty

Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)

SN74LVC07AD ACTIVE SOIC D1450Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADBR ACTIVE SSOP DB142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADBRG4ACTIVE SSOP DB142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADE4ACTIVE SOIC D1450Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADGVR ACTIVE TVSOP DGV142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADGVRE4ACTIVE TVSOP DGV142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADGVRG4ACTIVE TVSOP DGV142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADR ACTIVE SOIC D142500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADRE4ACTIVE SOIC D142500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADRG4ACTIVE SOIC D142500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADT ACTIVE SOIC D14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ADTE4ACTIVE SOIC D14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ANSR ACTIVE SO NS142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ANSRE4ACTIVE SO NS142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07APW ACTIVE TSSOP PW1490Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07APWE4ACTIVE TSSOP PW1490Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM SN74LVC07APWLE OBSOLETE TSSOP PW14TBD Call TI Call TI

SN74LVC07APWR ACTIVE TSSOP PW142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07APWRE4ACTIVE TSSOP PW142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07APWRG4ACTIVE TSSOP PW142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07APWT ACTIVE TSSOP PW14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07APWTE4ACTIVE TSSOP PW14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07APWTG4ACTIVE TSSOP PW14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC07ARGYR ACTIVE QFN RGY141000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-2-260C-1YEAR

(1)The marketing status values are defined as follows:

ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.

(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS)or Green(RoHS&no Sb/Br)-please check https://www.wendangku.net/doc/b42770350.html,/productcontent for the latest availability information and additional product content details.

TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)

(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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