M48T86_0707中文资料
July 2007 Rev 61/36
M48T86
5.0 V PC real-time clock
Features
■Drop-in replacement for PC computer clock/calendar
■
Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation
■Clock accuracy better than ±1 minute per month
■
Interfaced with software as 128 RAM locations:–14 bytes of clock and control registers –114 bytes of general purpose RAM ■Selectable bus timing (Intel/Motorola)■
Three interrupts are separately software-maskable and testable
–Time-of-day alarm (once/second to once/day)
–Periodic rates from 122μs to 500ms –End-of-clock update cycle ■Programmable square wave output
■10 years of data retention and clock operation in the absence of power
■Self-contained battery and crystal in the caphat dip package
■Packaging includes a 28-lead SOIC and Snaphat ? top (to be ordered separately)■SOIC package provides direct connection for a snaphat top contains the battery and crystal ■Pin and function compatible with bq3285/7A and DS12887
■
RoHS compliant
–Lead-free second level interconnect
https://www.wendangku.net/doc/ba11186775.html,
Contents M48T86
Contents
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V CC, V SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SQW (square wave output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AD0-AD7 (multiplexed bi-directional address/data bus) . . . . . . . . . . . . . . . . . . . . . 9
AS (address strobe input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MOT (mode select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DS (data strobe input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
E (chip enable input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IRQ (interrupt request output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RST (reset input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RCL (RAM clear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R/W (read/write input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Non-volatile RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Time, calendar, and alarm locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Periodic interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alarm interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Update cycle interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Oscillator control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Update cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Square wave output selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UIP update in progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OSC0, OSC1, OSC2 oscillator control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RS3, RS2, RS1, RS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/36
M48T86Contents
PIE: periodic interrupt enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AIE: alarm interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
UIE: update ended interrupt enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SQWE: square wave enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DM: data mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
24/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DSE: daylight savings enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IRQF: interrupt request flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PF: periodic interrupt flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AF: alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
UF: update ended interrupt flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
BIT 0 through 3: unused bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VRT: valid RAM and time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
BIT 0 through 6: unused bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V CC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC and AC parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of tables M48T86 List of tables
Table 1.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2.AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.Time, calendar, and alarm formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.Square wave frequency/periodic interrupt rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5.Register A MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6.Register B MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7.Register C MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8.Register D MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10.Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 12.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13.Power down/up mode AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14.Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15.PCDIP24 – 24-pin plastic DIP, battery CAPHAT, package mechanical data. . . . . . . . . . . 29 Table 16.SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package mechanical data30
Table 17.SH – 4-pin SNAPHAT housing for 48mAh battery and crystal, package mechanical data. 31 Table 18.SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package mechanical data32 Table 19.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 20.SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 21.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4/36
M48T86List of figures List of figures
Figure 1.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.24-pin DIP connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5.Intel bus read AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6.Intel bus write mode AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7.Motorola bus read/write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8.Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9.Update period timing and UIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10.Update-ended/periodic interrupt relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11.Supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12.AC testing load circuit (no IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13.AC testing load circuit (with IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14.Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 15.PCDIP24 – 24-pin plastic DIP, battery CAPHAT, package outline. . . . . . . . . . . . . . . . . . . 28 Figure 16.SOH28 – 28-lead plastic small outline, 4-socket SNAPHAT, package outline. . . . . . . . . . 29 Figure 17.SH – 4-pin SNAPHAT housing for 48mAh battery and crystal, package outline . . . . . . . . 30 Figure 18.SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package outline . . . . . . . 31
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Summary description
The M48T86 is an industry standard Real Time Clock (RTC). The M48T86 is composed of a
lithium energy source, quartz crystal, write protection circuitry, and a 128-byte RAM array.
This provides the user with a complete subsystem packaged in either a 24-pin DIP
CAPHAT? or 28-pin SNAPHAT? SOIC. Functions available to the user include a non-
volatile time-of-day clock, alarm interrupts, a one-hundred-year clock with programmable
interrupts, square wave output, and 128 bytes of non-volatile static RAM.
The 24-pin, 600mil DIP CAPHAT houses the M48T86 silicon with a quartz crystal and a
long-life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT? housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal
damage due to the high temperatures required for device surface-mounting. The SNAPHAT
housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in
Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package part number is “M4T28-BR12SH” (see
Table20 on page34).
6/36
7/36
Table 1.
Signal names
AD0-AD7
Multiplexed address/data bus E Chip enable input R/W WRITE enable input DS Data strobe input AS Address strobe input RST Reset Input RCL RAM clear input MOT Bus type select input SQW Square wave output IRQ Interrupt request output (open drain)V CC Supply voltage V SS Ground
NC
Not connected internally
8/36
M48T86Operation Operation
The M48T86 clock is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 23 ppm (parts per million) oscillator
frequency error at 25°C, which equates to approximately ±1 minute per month. Automatic
deselection of the device ensures the data integrity is not compromised should V CC fall
below specified Power-fail Deselect Voltage (V PFD) levels (see Figure14 on page27). The
automatic deselection of the device remains in effect upon power up for a period of 200ms
(max) after V CC rises above V PFD, provided that the Real Time Clock is running and the
count-down chain is not reset. This allows sufficient time for V CC to stabilize and gives the
system clock a wake-up period so that a valid system reset can be established.
The block diagram in Figure4 on page8 shows the pin connections and the major internal
functions of the M48T86.
Signal description
V CC, V SS
DC power is provided to the device on these pins.The M48T86 uses a 5V V CC.
SQW (square wave output)
During normal operation (e.g., valid V CC), the SQW pin can output a signal from one of 13
taps. The frequency of the SQW pin can be changed by programming Register A as shown
in T able4 on page18. The SQW signal can be turned on and off using the SQWE Bit
(Register B; Bit 3). The SQW signal is not available when V CC is less than V PFD.
AD0-AD7 (multiplexed bi-directional address/data bus)
The M48T86 provides a multiplexed bus in which address and data information share the
same signal path. The bus cycle consists of two stages; first the address is latched, followed
by the data. Address/Data multiplexing does not slow the access time of the M48T86,
because the bus change from address to data occurs during the internal RAM access time.
Addresses must be valid prior to the falling edge of AS (see Figure5 on page11), at which
time the M48T86 latches the address present on AD0-AD7. Valid WRITE data must be
present and held stable during the latter portion of the R/W pulse (see Figure6 on page11).
In a READ cycle, the M48T86 outputs 8 bits of data during the latter portion of the DS pulse.
The READ cycle is terminated and the bus returns to a high impedance state upon a high
transition on R/W.
AS (address strobe input)
A positive going pulse on the Address Strobe (AS) input serves to demultiplex the bus. The
falling edge of AS causes the address present on AD0-AD7 to be latched within the
M48T86.
9/36
Operation M48T86
MOT (mode select)
The MOT pin offers the flexibility to choose between two bus types (see Figure7 on
page12). When connected to V CC, Motorola bus timing is selected. When connected to V SS
or left disconnected, Intel bus timing is selected. The pin has an internal pull-down
resistance of approximately 20KΩ.
DS (data strobe input)
The DS pin is also referred to as READ (RD). A falling edge transition on the Data Strobe
(DS) input enables the output during a a READ cycle. This is very similar to an Output
E (chip enable input)
The Chip Enable pin must be asserted low for a bus cycle in the M48T86 to be accessed.
Bus cycles which take place without asserting E will latch the addresses present, but no
data access will occur.
is an open drain output so it requires an external pull-up resistor to V CC.
RST (reset input)
The M48T86 is reset when the RST input is pulled low. With a valid V CC applied and a low
on RST, the following events occur:
1.Periodic Interrupt Enable (PIE) Bit is cleared to a zero (Register B; Bit 6);
2. Alarm Interrupt Enable (AIE) Bit is cleared to a zero (Register B; Bit 5);
3. Update Ended Interrupt Request (UF) Bit is cleared to a zero (Register C; Bit 4);
4. Interrupt Request (IRQF) Bit is cleared to a zero (Register C Bit 7);
5. Periodic Interrupt Flag (PF) Bit is cleared to a zero (Register C; Bit 6);
6. The device is not accessible until RST is returned high;
7. Alarm Interrupt Flag (AF) Bit is cleared to a zero (Register C; Bit 5);
8. The IRQ pin is in the high impedance state
9. Square Wave Output Enable (SQWE) Bit is cleared to zero (Register B; Bit 3); and
10. Update Ended Interrupt Enable (UIE) is cleared to a zero (Register B; Bit 4).
least 100ms with the oscillator running. Usage of this pin does not affect battery load. This
function is applicable only when V CC is applied.
10/36
M48T86Operation
R/W (read/write input)
The R/W pin is used to latch data into the M48T86 and provides functionality similar to W in
other memory systems.
Non-volatile RAM
The 114 general-purpose non-volatile RAM bytes are not dedicated to any special function
within the M48T86. They can be used by the processor program as non-volatile memory
and are fully accessible during the update cycle.
Operation M48T86
M48T86
Operation
Table 2.
AC characteristics
Symbol Parameter (1)
1.Valid for ambient operating temperature: T A = 0 to 70°C; V CC = 4.5 to 5.5V (except where noted).M48T86
Unit
Min Typ
Max
t CYC Cycle time
160ns t DSL Pulse width, data strobe low or R/W high 80ns t DSH Pulse width, data strobe high or R/W low 55ns t RWH R/W hold time 0ns t RWS R/W setup time 10ns t CS Chip select setup time 5ns t CH Chip select hold time 0ns t DHR READ data hold time 025
ns t DHW WRITE data hold time 0ns t AS Address setup time 20ns t AH Address hold time
5ns t DAS Delay time, data strobe to address strobe rise
10ns t ASW Pulse width address strobe high
30ns t ASD Delay time, address strobe to data strobe rise
35
ns t OD Output data delay time from data strobe rise
50ns t DW WRITE setup time
30
ns t BUC Delay time before update cycle 244μs
t PI (2)2.See Table 4 on page 18.
Periodic interrupt time interval –––
t UC
Time of update cycle
1
μs
Clock operations M48T86 Clock operations
Address map
The address map of the M48T86 is shown in Figure8. It consists of 114 bytes of user RAM,
10 bytes of RAM that contain the RTC time, calendar and alarm data, and 4 bytes which are
used for control and status. All bytes can be read or written to except for the following:
1.Registers C & D are “Read only.”
2. Bit 7 of Register A is “Read only.”
The contents of the four Registers A, B, C, and D are described in the “Registers” section.
Time, calendar, and alarm locations
The time and calendar information is obtained by reading the appropriate memory bytes.
The time, calendar, and alarm registers are set or initialized by writing the appropriate RAM
bytes. The contents of the time, calendar, and alarm bytes can be either Binary or Binary-
Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm register,
the SET Bit (Register B; Bit 7) should be written to a logic '1.' This will prevent updates from
occurring while access is being attempted. In addition to writing the time, calendar, and
alarm registers in a selected format (binary or BCD), the Data Mode (DM) Bit (Register B;
Bit 2), must be set to the appropriate logic level ('1' signifies binary data; '0' signifies Binary
Coded Decimal (BCD data). All time, calendar, and alarm bytes must use the same data
mode. The SET Bit should be cleared after the Data Mode Bit has been written to allow the
Real Time Clock to update the time and calendar bytes. Once initialized, the Real Time
Clock makes all updates in the selected mode. The data mode cannot be changed without
reinitializing the ten data bytes. Table3 on page15 shows the binary and BCD formats of
the time, calendar, and alarm locations. The 24/12 Bit (Register B; Bit 1) cannot be changed
without reinitializing the hour locations. When the 12-hour format is selected, a logic '1' in
the high order bit of the hours byte represents PM. The time, calendar, and alarm bytes are
always accessible because they are double-buffered. Once per second the ten bytes are
advanced by one second and checked for an alarm condition. If a READ of the time and
calendar data occurs during an update, a problem exists where data such as seconds,
minutes, or hours may not correlate. However, the probability of reading incorrect time and
calendar data is low. Methods of avoiding possible incorrect time and calendar READs are
reviewed later in this text.
M48T86Clock operations
Table 3.Time, calendar, and alarm formats
Address RTC Bytes
Range
Decimal Binary BCD 0Seconds0-5900-3B00-59
1Seconds alarm0-5900-3B00-59
2Minutes0-5900-3B00-59
3Minutes alarm0-5900-3B00-59
4Hours, 12-hrs1-12
01-0C AM
81-8C PM
01-12 AM
81-92 PM Hours, 24-hrs0-2300-1700-23
5Hours alarm, 12-hrs1-12
01-0C AM
81-8C PM
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81-92 PM Hours alarm, 24-hrs0-2300-1700-23
6Day of week (1 = Sun)1-701-0701-07 7Day of month1-3101-1F01-31 8Month1-1201-0C01-12 9Y ear0-9900-6300-99
Clock operations M48T86
Interrupts
The RTC plus RAM includes three separate, fully automatic sources of interrupt (alarm,
periodic, update-in-progress) available to a processor. The alarm interrupt can be
programmed to occur at rates from once per second to once per day. The periodic interrupt
can be selected from rates of 500ms to 122μs. The update-ended interrupt can be used to
indicate that an update cycle has completed.
The processor program can select which interrupts, if any, are going to be used. Three bits
in Register B enable the interrupts. Writing a logic '1' to an interrupt-enable bit (Register B;
Bit 6=PIE; Bit 5=AIE; Bit 4=UIE) permits an interrupt to be initialized when the event
occurs. A '0' in an interrupt-enable bit prohibits the IRQ pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is
immediately set at an active level, although the interrupt initiating the event may have
occurred much earlier. As a result, there are cases where the program should clear such
earlier initiated interrupts before first enabling new interrupts.
When an interrupt event occurs, the related flag bit (Register C; Bit 6 = PF; Bit 5 = AF; Bit 4
= UF) is set to a logic '1.' These flag bits are set independent of the state of the
corresponding enable bit in Register B and can be used in a polling mode without enabling
the corresponding enable bits. The interrupt flag bits are status bits which software can
interrogate as necessary.
When a flag is set, an indication is given to software that an interrupt event has occurred
since the flag bit was last read; however, care should be taken when using the flag bits as all
are cleared each time Register C is read. Double latching is included with Register C so that
bits which are set remain stable throughout the READ cycle. All bits which are set high are
cleared when read. Any new interrupts which are pending during the READ cycle are held
until after the cycle is completed. One, two, or three bits can be set when reading Register
C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit
is set and the corresponding enable bit is also set, the IRQ pin is asserted low. IRQ is
asserted as long as at least one of the three interrupt sources has its flag and enable bits
both set. The IRQF Bit (Register C; Bit 7) is a '1' whenever the IRQ pin is being driven low.
Determination that the RTC initiated an interrupt is accomplished by reading Register C. A
logic '1' in the IRQF Bit indicates that one or more interrupts have been initiated by the
M48T86. The act of reading Register C clears all active flag bits and the IRQF Bit. Periodic interrupt
to once every 122μs. This function is separate from the alarm interrupt which can be output
from once per second to once per day. The periodic interrupt rate is selected using the
same Register A bits which select the square wave frequency (see Table4 on page18).
Changing the Register A bits affects both the square wave frequency and the periodic
interrupt output. However, each function has a separate enable bit in Register B. The
periodic interrupt is enabled by the PIE Bit (Register B; Bit 6). The periodic interrupt can be
used with software counters to measure inputs, create output intervals, or await the next
needed software function.
M48T86Clock operations
Alarm interrupt
The alarm interrupt provides the system processor with an interrupt when a match is made
between the RTC's hours, minutes, and seconds bytes and the corresponding alarm bytes.
The three alarm bytes can be used in two ways. First, when the alarm time is written in the
appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at
the specified time each day if the Alarm Interrupt Enable Bit (Register B; Bit 5) is high. The
second use is to insert a “Don't care” state in one or more of the three alarm bytes. The
“Don't care” code is any hexadecimal value from C0 to FF. The two most significant bits of
each byte set the “Don't care” condition when at logic '1.' An alarm will be generated each
hour when the “Don't care” is are set in the hours byte. Similarly, an alarm is generated
every minute with “Don't care” codes in the hour and minute alarm bytes. The “Don't care”
codes in all three alarm bytes create an interrupt every second.
Update cycle interrupt
After each update cycle, the Update Cycle Ended Flag Bit (UF) (Register C; Bit 4) is set to a
'1.' If the Update Interrupt Enable Bit (UIE) (Register B; Bit 4) is set to a '1,' and the SET Bit
(Register B; Bit 7) is a '0,' then an interrupt request is generated at the end of each update
cycle.
Oscillator control bits
When the M48T86 is shipped from the factory the internal oscillator is turned off. This
feature prevents the lithium energy cell from being discharged until it is installed in a system.
A pattern of “010” in Bits 4-6 of Register A will turn the oscillator on and enable the
countdown chain. A pattern of “11X” will turn the oscillator on, but holds the countdown
chain of the oscillator in reset. All other combinations of Bits 4-6 keep the oscillator off.
Update cycle
The M48T86 executes an update cycle once per second regardless of the SET Bit (Register
B; Bit 7). When the SET Bit is asserted, the user copy of the double buffered time, calendar,
and alarm bytes is frozen and will not update as the time increments. However, the time
countdown chain continues to update the internal copy of the buffer. This feature allows
accurate time to be maintained, independent of reading and writing the time, calendar, and
alarm buffers. This also guarantees that the time and calendar information will be
consistent. The update cycle also compares each alarm byte with the corresponding time
byte and issues an alarm if a match or if a “Don't care” code is present in all three positions.
There are three methods of accessing the real time clock that will avoid any possibility of
obtaining inconsistent time and calendar data. The first method uses the update-ended
interrupt. If enabled, an interrupt occurs after every update cycle which indicates that over
999ms are available to read valid time and date information. If this interrupt is used, the
IRQF Bit (Register C; Bit 7) should be cleared before leaving the interrupt routine.
A second method uses the Update-In-Progress (UIP) Bit (Register A; Bit 7) to determine if
the update cycle is in progress. The UIP Bit will pulse once per second. After the UIP Bit
goes high, the update transfer occurs 244μs later. If a low is read on the UIP Bit, the user
has at least 244μs before the time/calendar data will be changed. Therefore, the user
Clock operations M48T86 should avoid interrupt service routines that would cause the time needed to read valid
time/calendar data to exceed 244μs.
The third method uses a periodic interrupt to determine if an update cycle is in progress.
The UIP Bit is set high between the setting of the PF Bit (Register C; Bit 6). Periodic
interrupts that occur at a rate greater than t BUC allow valid time and date information to be
reached at each occurrence of the periodic interrupt.The READs should be completed
within 1/(t PL/2 + t BUC) to ensure that data is not read during the update cycle.
Square wave output selection
Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the
block diagram of Figure4 on page8. The purpose of selecting a divider tap is to generate a
square wave output signal on the SQW pin. The RS3-RS0 bits in Register A establish the
square wave output frequency. These frequencies are listed in Table4 on page18. The
SQW frequency selection shares the 1-of-15 selector with the periodic interrupt generator.
Once the frequency is selected, the output of the SQW pin can be turned on and off under
program control with the Square Wave Enabled (SQWE) Bit.
Table 4.Square wave frequency/periodic interrupt rate
Register A bits Square wave Periodic interrupt RS3RS2RS1RS0Frequency Units Period Units
0000None None
0001256Hz 3.90625ms
0010128Hz7.8125ms
00118.192kHz122.070us
0100 4.096kHz244.141us
0101 2.048kHz488.281us
0110 1.024kHz976.5625us
0111512Hz 1.953125ms
1000256Hz 3.90625ms
1001128Hz7.8125ms
101064Hz15.625ms
101132Hz31.25ms
110016Hz62.5ms
11018Hz125ms
11104Hz250ms
11112Hz500ms
M48T86Clock operations Register A
UIP update in progress
The Update in Progress (UIP) Bit is a status flag that can be monitored. When the UIP Bit is
'1,' the update transfer will soon occur (see Figure9). When UIP is a '0,' the update transfer
will not occur for at least 244μs. The time, calendar, and alarm information in RAM is fully
available for access when the UIP Bit is '0.' The UIP Bit is “Read only” and is not affected by
RST. Writing the SET Bit in Register B to a '1' inhibits any update transfer and clears the
UIP Status Bit.
OSC0, OSC1, OSC2 oscillator control
These three bits are used to control the oscillator and reset the countdown chain. A pattern
of “010” enables operation by turning on the oscillator and enabling the divider chain. A
pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When “010”
is written, the first update begins after 500ms.
RS3, RS2, RS1, RS0
These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the
divider output. The tap selected may be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user may do one of the following:
1.Enable the interrupt with the PIE Bit;
or
2. Enable the SQW output with the SQWE Bit;
or
3. Enable both at the same time and same rate;
or
4. Enable neither.
Table4 on page18 lists the periodic interrupt rates and the square wave frequencies that
may be chosen with the RS Bits. These four READ/WRITE bits are not affected by RST.
Table 5.Register A MSB
BIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0 UIP OSC2OSC1OSC0RS3RS2RS1RS0
Clock operations M48T86 Register B
SET
When the SET Bit is a '0,' the update transfer functions normally by advancing the counts
once per second. When the SET Bit is written to a '1,' any update transfer is inhibited and
the program may initialize the time and calendar bytes without an update occurring. READ
cycles can be executed in a similar manner. SET is a READ/WRITE bit which is not
modified by RST or internal functions of the M48T86.
PIE: periodic interrupt enable
The Periodic Interrupt Enable Bit (PIE) is a READ/WRITE bit which allows the Periodic
Figure10 on page21 for the relationship between PIE and UIE). When the PIE Bit is set to '1,' periodic
interrupt, but the Periodic Flag (PF) Bit is still set at the periodic rate. PIE is not modified by
AIE: alarm interrupt enable
The Alarm Interrupt Enable (AIE) Bit is a READ/WRITE bit which, when set to a '1,' permits
the Alarm Flag (AF) Bit in Register C to assert IRQ. An alarm interrupt occurs for each
second that the three time bytes equal the three alarm bytes including a “Don't care” alarm
code of binary 1XXXXXXX. When the AIE Bit is set to '0,' the AF Bit does not initiate the IRQ
signal. The RST pin clears AIE to '0.' The internal functions of the M48T86 do not affect the
AIE Bit.
UIE: update ended interrupt enable
The Update Ended Interrupt Enable (UIE) Bit is a READ/WRITE bit which enables the
SET Bit going high clears the UIE Bit.
SQWE: square wave enable
When the Square Wave Enable (SQWE) Bit is set to a '1,' a square wave signal is driven out
on the SQW pin. The frequency is determined by the rate-selection bits RS3-RS0. When the
SQWE Bit is set to '0,' the SQW pin is held low. The SQWE Bit is cleared by the RST pin.
SQWE is a READ/WRITE bit.
DM: data mode
The Data Mode (DM) Bit indicates whether time and calendar information are in binary or
BCD format. The DM Bit is set by the program to the appropriate format and can be read as
and a '0' specifies Binary Coded Decimal (BCD) data.