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COP8SGB928N8中文资料

COP8SG Family

8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory,Two Comparators and USART

General Description

The COP8SG Family ROM and OTP based microcontrollers are highly integrated COP8?Feature core devices with 8k to 32k memory and advanced features including Analog comparators,and zero external components.These single-chip CMOS devices are suited for more complex applica-tions requiring a full featured controller with larger memory,low EMI,two comparators,and a full-duplex USART.COP8SGx7devices are 100%form-fit-function compatible OTP (One Time Programmable)versions for use in produc-tion or development of the COP8SGx5ROM.

Erasable windowed versions (Q3)are available for use with a range of COP8software and hardware development tools.Family features include an 8-bit memory mapped architec-ture,15MHz CKI with 0.67μs instruction cycle,14inter-rupts,three multi-function 16-bit timer/counters with PWM,full duplex USART,MICROWIRE/PLUS ?,two analog com-parators,two power saving HALT/IDLE modes,MIWU,idle timer,on-chip R/C oscillator,high current outputs,user se-lectable options (WATCHDOG ?,4clock/oscillator modes,power-on-reset),2.7V to 5.5V operation,program code se-curity,and 28/40/44pin packages.

Devices included in this datasheet are:

Device Memory (bytes)

RAM (bytes)I/O Pins Packages Temperature COP8SGE58k ROM 25624/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85?C,-40to +125?C COP8SGG516k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85?C,-40to +125?C COP8SGH520k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85?C,-40to +125?C COP8SGK524k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85?C,-40to +125?C COP8SGR532k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85?C,-40to +125?C COP8SGE78k OTP EPROM 25624/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85?C,-40to +125?C COP8SGR732k OTP EPROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85?C,-40to +125?C COP8SGR7-Q3

32k EPROM

512

24/36/40

28DIP ,40DIP ,44PLCC

Room Temp.

Key Features

n Low cost 8-bit microcontroller

n Quiet Design (low radiated emissions)

n Multi-Input Wakeup pins with optional interrupts (8pins)n

Mask selectable clock options —Crystal oscillator

—Crystal oscillator option with on-chip bias resistor —External oscillator —Internal R/C oscillator

n Internal Power-On-Reset —user selectable

n WATCHDOG and Clock Monitor Logic —user selectable n Eight high current outputs

n 256or 512bytes on-board RAM

8k to 32k ROM or OTP EPROM with security feature

CPU Features

n Versatile easy to use instruction set n 0.67μs instruction cycle time

n Fourteen multi-source vectored interrupts servicing —External interrupt /Timers T0—T3—MICROWIRE/PLUS Serial Interface —Multi-Input Wake Up —Software Trap

—USART (2;1receive and 1transmit)—Default VIS (default interrupt)

n 8-bit Stack Pointer SP (stack in RAM)

n Two 8-bit Register Indirect Data Memory Pointers n True bit manipulation

n BCD arithmetic instructions

Peripheral Features

n Multi-Input Wakeup Logic

n Three 16-bit timers (T1—T3),each with two 16-bit registers supporting:

—Processor Independent PWM mode —External Event Counter mode —Input Capture mode

COP8?is a trademark of National Semiconductor Corporation.

October 2001

COP8SG Family,8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory,Two Comparators and USART

?2001National Semiconductor Corporation https://www.wendangku.net/doc/c06705287.html,

Peripheral Features

(Continued)

n Idle Timer (T0)

n MICROWIRE/PLUS Serial Interface (SPI Compatible)n Full Duplex USART

Two Analog Comparators

I/O Features

n Software selectable I/O options (TRI-STATE ?

Output,Push-Pull Output,Weak Pull-Up Input,and High Impedance Input)

n Schmitt trigger inputs on ports G and L n Eight high current outputs

n Packages:28SO with 24I/O pins,40DIP with 36I/O pins,44PLCC,PQFP and CSP with 40I/O pins

Fully Static CMOS Design

n Low current drain (typically <4μA)

n Two power saving modes:HALT and IDLE

Temperature Range

n ?40?C to +85?C,?40?C to +125?C

Development Support

n Windowed packages for DIP and PLCC

n Real time emulation and debug tools available

Block Diagram

10131744

FIGURE 1.COP8SGx Block Diagram

C O P 8S G F a m i l y

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1.0Device Description

1.1ARCHITECTURE

The COP8family is based on a modified Harvard architec-ture,which allows data tables to be accessed directly from program memory.This is very important with modern microcontroller-based applications,since program memory is usually ROM or EPROM,while data memory is usually RAM.Consequently data tables need to be contained in non-volatile memory,so they are not lost when the micro-controller is powered down.In a modified Harvard architec-ture,instruction fetch and memory data transfers can be overlapped with a two stage pipeline,which allows the next instruction to be fetched from program memory while the current instruction is being executed using data memory. This is not possible with a Von Neumann single-address bus architecture.

The COP8family supports a software stack scheme that allows the user to incorporate many subroutine calls.This capability is important when using High Level Languages. With a hardware stack,the user is limited to a small fixed number of stack levels.

1.2INSTRUCTION SET

In today’s8-bit microcontroller application arena cost/ performance,flexibility and time to market are several of the key issues that system designers face in attempting to build well-engineered products that compete in the marketplace. Many of these issues can be addressed through the manner in which a microcontroller’s instruction set handles process-ing tasks.And that’s why COP8family offers a unique and code-efficient instruction set—one that provides the flexibil-ity,functionality,reduced costs and faster time to market that today’s microcontroller based products require.

Code efficiency is important because it enables designers to pack more on-chip functionality into less program memory space.Selecting a microcontroller with less program memory size translates into lower system costs,and the added security of knowing that more code can be packed into the available program memory space.

1.2.1Key Instruction Set Features

The COP8family incorporates a unique combination of in-struction set features,which provide designers with optimum code efficiency and program memory utilization.

Single Byte/Single Cycle Code Execution

The efficiency is due to the fact that the majority of instruc-tions are of the single byte variety,resulting in minimum program space.Because compact code does not occupy a substantial amount of program memory space,designers can integrate additional features and functionality into the microcontroller program memory space.Also,the majority instructions executed by the device are single cycle,result-ing in minimum program execution time.In fact,77%of the instructions are single byte single cycle,providing greater code and I/O efficiency,and faster code execution.

1.2.2Many Single-Byte,Multifunction Instructions

The COP8instruction set utilizes many single-byte,multi-function instructions.This enables a single instruction to accomplish multiple functions,such as DRSZ,DCOR,JID, LD(Load)and X(Exchange)instructions with post-

incrementing and post-decrementing,to name just a few

examples.In many cases,the instruction set can simulta-

neously execute as many as three functions with the same

single-byte instruction.

JID:(Jump Indirect);Single byte instruction;decodes exter-

nal events and jumps to corresponding service routines

(analogous to“DO CASE”statements in higher level lan-

guages).

LAID:(Load Accumulator-Indirect);Single byte look up table

instruction provides efficient data path from the program

memory to the CPU.This instruction can be used for table

lookup and to read the entire program memory for checksum

calculations.

RETSK:(Return Skip);Single byte instruction allows return

from subroutine and skips next instruction.Decision to

branch can be made in the subroutine itself,saving code.

AUTOINC/DEC:(Auto-Increment/Auto-Decrement);These

instructions use the two memory pointers B and X to effi-

ciently process a block of data(analogous to“FOR NEXT”in

higher level languages).

1.2.3Bit-Level Control

Bit-level control over many of the microcontroller’s I/O ports

provides a flexible means to ease layout concerns and save

board space.All members of the COP8family provide the

ability to set,reset and test any individual bit in the data

memory address space,including memory-mapped I/O ports

and associated registers.

1.2.4Register Set

Three memory-mapped pointers handle register indirect ad-

dressing and software stack pointer functions.The memory

data pointers allow the option of post-incrementing or post-

decrementing with the data movement instructions(LOAD/

EXCHANGE).And15memory-maped registers allow de-

signers to optimize the precise implementation of certain

specific instructions.

1.3EMI REDUCTION

The COP8SGx5family of devices incorporates circuitry that

guards against electromagnetic interference—an increasing

problem in today’s microcontroller board designs.National’s

patented EMI reduction technology offers low EMI clock

circuitry,gradual turn-on output drivers(GTOs)and internal

smoothing filters,to help circumvent many of the EMI issues influencing embedded control designs.National has

achieved15dB–20dB reduction in EMI transmissions when

designs have incorporated its patented EMI reducing cir-

cuitry.

1.4PACKAGING/PIN EFFICIENCY

Real estate and board configuration considerations demand

maximum space and pin efficiency,particularly given today’s

high integration and small product form factors.Microcon-

troller users try to avoid using large packages to get the I/O

https://www.wendangku.net/doc/c06705287.html,rge packages take valuable board space and

increases device cost,two trade-offs that microcontroller

designs can ill afford.

The COP8family offers a wide range of packages and do not

waste pins:up to90.9%(or40pins in the44-pin package)

are devoted to useful I/O.

COP8SG

Family

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Connection Diagrams

10131704Top View

Order Number COP8SGXY28M8See NS Package Number M28B Order Number COP8SGXY28N8See NS Package Number N28B Order Number COP8SGR728Q3See NS Package Number D28JQ

10131753

Top View

Order Number COP8SGR7HLQ8See NS Package Number LQA44A

10131705

Top View

Order Number COP8SGXY40N8See NS Package Number N40A Order Number COP8SGR5740Q3See NS Package Number D40KQ

10131706Top View

Order Number COP8SGXY44V8See NS Package Number V44A Order Number COP8SGR744J3See NS Package Number EL44C

10131743

Top View

Order Number COP8SGXYVEJ8See NS Package Number VEJ44A

Note 1:X =E for 8k,G for 16k,

H for 20k,K for 24k,R for 32k Y =5for ROM,7for OTP

C O P 8S G F a m i l y

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Pinouts for28-,40-and44-Pin Packages

Port Type Alt.Fun 28-Pin

40-Pin DIP

44-Pin

PLCC

44-Pin PQFP44-Pin CSP

L0I/O MIWU1117171112 L1I/O MIWU or CKX1218181213 L2I/O MIWU or TDX1319191314 L3I/O MIWU or RDX1420201415 L4I/O MIWU or T2A1521251920 L5I/O MIWU or T2B1622262021 L6I/O MIWU or T3A1723272122 L7I/O MIWU or T3B1824282223 G0I/O INT2535393334 G1I/O WDOUT*2636403435 G2I/O T1B2737413536 G3I/O T1A2838423637 G4I/O SO1334142 G5I/O SK2444243 G6I SI3554344 G7I CKO466441 D0O1925292324 D1O2026302425 D2O2127312526 D3O2228322627 D4O29332728 D5O30342829 D6O31352930 D7O32363031 F0I/O79934 F1I/O COMP1IN?8101045 F2I/O COMP1IN+9111156 F3I/O COMP1OUT10121267 F4I/O COMP2IN?131378 F5I/O COMP2IN+141489 F6I/O COMP2OUT1515910 F7I/O16161011 C0I/O39433738 C1I/O40443839 C2I/O113940 C3I/O224041 C4I/O211516 C5I/O221617 C6I/O231718 C7I/O241819 V

68823 GND2333373132 CKI I57712 RESET I2434383233 *G1operation as WDOUT is controlled by ECON bit2.COP8SG Family

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2.1Ordering Information

10131708

FIGURE 2.Part Numbering Scheme

C O P 8S G F a m i l y

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3.0Electrical Characteristics

Absolute Maximum Ratings(Note2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage(V CC)7V

Voltage at Any Pin?0.3V to V CC+0.3V

Total Current into V CC

Pin(Source)100mA

Total Current out of

GND Pin(Sink)110mA

Storage Temperature

Range?65?C to+140?C

ESD Protection Level2kV(Human Body

Model) Note2:Absolute maximum ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics

?40?C≤T A≤+85?C unless otherwise specified.

Parameter Conditions Min Typ Max Units Operating Voltage 2.7 5.5V Power Supply Rise Time1050x106ns V CC Start Voltage to Guarantee POR00.25V Power Supply Ripple(Note4)Peak-to-Peak0.1V cc V Supply Current(Note5)

CKI=15MHz V CC=5.5V,t C=0.67μs9.0mA CKI=10MHz V CC=5.5V,t C=1μs 6.0mA CKI=4MHz V CC=4.5V,t C=2.5μs 2.1mA HALT Current(Note6)V CC=5.5V,CKI=0MHz<410μA IDLE Current(Note5)

CKI=15MHz V CC=5.5V,t C=0.67μs 2.25mA CKI=10MHz V CC=5.5V,t C=1μs 1.5mA CKI=4MHz V CC=4.5V,t C=2.5μs0.8mA Input Levels(V IH,V IL)

RESET

Logic High0.8V cc V Logic Low0.2V cc V CKI,All Other Inputs

Logic High0.7V cc V Logic Low0.2V cc V Internal Bias Resistor for the

Crystal/Resonator Oscillator

0.512M?

CKI Resistance to V CC or GND when R/C

Oscillator is selected

V CC=5.5V5811k?Hi-Z Input Leakage V CC=5.5V?2+2μA Input Pullup Current V CC=5.5V,V IN=0V?40?250μA G and L Port Input Hysteresis V CC=5.5V0.25V cc V COP8SG Family

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DC Electrical Characteristics

(Continued)

?40?C ≤T A ≤+85?C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

Output Current Levels D Outputs Source V CC =4.5V,V OH =3.3V ?0.4mA V CC =2.7V,V OH =1.8V -0.2mA Sink V CC =4.5V,V OL =1.0V 10mA V CC =2.7V,V OL =0.4V 2mA All Others

Source (Weak Pull-Up Mode)V CC =4.5V,V OH =2.7V ?10.0?110μA V CC =2.7V,V OH =1.8V -2.5-33

μA Source (Push-Pull Mode)V CC =4.5V,V OH =3.3V ?0.4mA V CC =2.7V,V OH =1.8V -0.2mA Sink (Push-Pull Mode)V CC =4.5V,V OL =0.4V V CC =2.7V,V OL =0.4V 1.60.7mA mA TRI-STATE Leakage

V CC =5.5V

+2μA Allowable Sink Current per Pin (Note 9)D Outputs and L0to L315mA All Others

3mA Maximum Input Current without Latchup (Note 7)

Room Temp.

±200

mA RAM Retention Voltage,Vr 2.0

V V CC Rise Time from a V CC ≥2.0V (Note 10)12

μs

EPROM Data Retenton (Note 8),(Note 9)T A =55?C >29

years Input Capacitance (Note 9)7pF Load Capacitance on D2

(Note 9)

1000

AC Electrical Characteristics

?40?C ≤T A ≤+85?C unless otherwise specified.

Parameter

Conditions

Min Typ Max Units Instruction Cycle Time (t C )Crystal/Resonator,External 4.5V ≤V CC ≤5.5V 0.67μs 2.7V ≤V CC ≤4.5V 2

μs

R/C Oscillator (Internal) 4.5V ≤V CC ≤5.5V 2μs Frequency Variation (Note 9) 4.5V ≤V CC ≤5.5V ±35

External CKI Clock Duty Cycle (Note 9)fr =Max

55%Rise Time (Note 9)fr =10MHz Ext Clock 8ns Fall Time (Note 9)

fr =10MHz Ext Clock

ns MICROWIRE Setup Time (t UWS )(Note 11)

20ns MICROWIRE Hold Time (t UWH )(Note 11)

MICROWIRE Output Propagation Delay (t UPD )(Note 11)

220

Input Pulse Width (Note 9)Interrupt Input High Time 1t C Interrupt Input Low Time 1t C Timer 1,2,3,Input High Time 1t C Timer 12,3,Input Low Time 1t C Reset Pulse Width

μs

Note 3:t C =Instruction cycle time.

C O P 8S G F a m i l y

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AC Electrical Characteristics(Continued)

Note4:Maximum rate of voltage change must be<0.5V/ms.

Note5:Supply and IDLE currents are measured with CKI driven with a square wave Oscillator,External Oscillator,inputs connected to V CC and outputs driven low but not connected to a load.

Note6:The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations.In the R/C configuration,CKI is forced high internally.In the crystal or external configuration,CKI is TRI-STATE.Measurement of I DD HALT is done with device neither sourcing nor sinking current;with L.F,C,G0,and G2–G5 programmed as low outputs and not driving a load;all outputs programmed low and not driving a load;all inputs tied to V CC;clock monitor disabled.Parameter refers to HALT mode entered via setting bit7of the G Port data register.

Note7:Pins G6and RESET are designed with a high voltage input network.These pins allow input voltages>V CC and the pins will have sink current to V CC when biased at voltages>V CC(the pins do not have source current when biased at a voltage below V CC).The effective resistance to V CC is750?(typical).These two pins will not latch up.The voltage at the pins must be limited to<14V.WARNING:Voltages in excess of14V will cause damage to the pins.This warning excludes ESD transients.

Note8:National Semiconductor uses the High Temperature Storage Life(HTSL)test to evaluate the data retention capabilities of the EPROM memory cells used in our OTP microcontrollers.Qualification devices have been stressed at150?C for1000hours.Under these conditions,our EPROM cells exhibit data retention capabilities in excess of29years.This is based on an activation energy of0.7eV derated to55?C.

Note9:Parameter characterized but not tested.

Note10:Rise times faster than the minimum specification may trigger an internal power-on-reset.

Note11:MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock.See and the MICROWIRE operation description.

Comparators AC and DC Characteristics

V CC=5V,?40?C≤T A≤+85?C.

Parameter Conditions Min Typ Max Units Input Offset Voltage(Note12)0.4V≤V IN≤V CC?1.5V±5±15mV Input Common Mode Voltage Range0.4V CC?1.5V Voltage Gain100dB Low Level Output Current V OL=0.4V?1.6mA High Level Output Current V OH=V CC?0.4V 1.6mA DC Supply Current per Comparator

(When Enabled)

150μA

Response Time(Note13)200mV step input

100mV Overdrive,

100pF Load

600ns

Comparator Enable Time(Note14)600ns Note12:The comparator inputs are high impedance port inputs and,as such,input current is limited to port input leakage current.

Note13:Response time is measured from a step input to a valid logic level at the comparator output.software response time is dependent of instruction execution. Note14:Comparator enable time is that delay time required between the end of the instruction cycle that enables the comparator and using the output of the comparator,either by hardware or by software.

10131709

FIGURE3.MICROWIRE/PLUS Timing COP8SG Family

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Absolute Maximum Ratings

(Note 2)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (V CC )7V

Voltage at Any Pin ?0.3V to V CC +0.3V

Total Current into V CC Pin (Source)100mA Total Current out of GND Pin (Sink)

110mA

Storage Temperature Range

?65?C to +140?C ESD Protection Level

2kV (Human Body

Model)

Note 15:Absolute maximum ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics

?40?C ≤T A ≤+125?C unless otherwise specified.

Parameter

Conditions

Min Typ

Max Units Operating Voltage 4.5 5.5V Power Supply Rise Time

1050x 106ns V CC Start Voltage to Guarantee POR 0

0.25V Power Supply Ripple (Note 4)Peak-to-Peak

0.1V cc

Supply Current (Note 5)CKI =10MHz V CC =5.5V,t C =1μs 6.0mA CKI =4MHz V CC =4.5V,t C =2.5μs 2.1

mA HALT Current (Note 6)V CC =5.5V,CKI =0MHz

μA

IDLE Current (Note 5)CKI =10MHz V CC =5.5V,t C =1μs 1.5mA CKI =4MHz V CC =4.5V,t C =2.5μs

0.8

Input Levels (V IH ,V IL )RESET Logic High 0.8V cc

V Logic Low 0.2V cc

CKI,All Other Inputs Logic High 0.7V cc

V Logic Low

0.2V cc

V Internal Bias Resistor for the Crystal/Resonator Oscillator

0.512M ?CKI Resistance to V CC or GND when R/C Oscillator is selected V CC =5.5V 58

11k ?Hi-Z Input Leakage V CC =5.5V

?5+5μA Input Pullup Current

V CC =5.5V,V IN =0V ?35?400

μA G and L Port Input Hysteresis V CC =5.5V

0.25V cc

Output Current Levels D Outputs Source V CC =4.5V,V OH =3.3V ?0.4mA Sink V CC =4.5V,V OL =1.0V

All Others

Source (Weak Pull-Up Mode)V CC =4.5V,V OH =2.7V ?9?140

μA Source (Push-Pull Mode)V CC =4.5V,V OH =3.3V ?0.4mA Sink (Push-Pull Mode)V CC =4.5V,V OL =0.4V 1.4mA TRI-STATE Leakage

V CC =5.5V

+5μA

Allowable Sink Current per Pin (Note 9)D Outputs and L0to L315

15mA All Others

C O P 8S G F a m i l y

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DC Electrical Characteristics(Continued)

?40?C≤T A≤+125?C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Maximum Input Current without Latchup (Note7)Room Temp.

±200mA

RAM Retention Voltage,Vr 2.0V V CC Rise Time from a V CC≥2.0V(Note10)12μs EPROM Data Retenton(Note8),(Note9)T A=55?C>29years Input Capacitance(Note9)7pF Load Capacitance on D2(Note9)1000pF COP8SG Family

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AC Electrical Characteristics

?40?C ≤T A ≤+125?C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t C )Crystal/Resonator,External 4.5V ≤V CC ≤5.5V 1

μs R/C Oscillator (Internal) 4.5V ≤V CC ≤5.5V 2

μs Frequency Variation (Note 9) 4.5V ≤V CC ≤5.5V ±35

External CKI Clock Duty Cycle (Note 9)fr =Max

4555%Rise Time (Note 9)fr =10MHz Ext Clock 12ns Fall Time (Note 9)

fr =10MHz Ext Clock

ns MICROWIRE Setup Time (t UWS )(Note 11)

20ns MICROWIRE Hold Time (t UWH )(Note 11)

ns MICROWIRE Output Propagation Delay (t UPD )(Note 11)

220

Input Pulse Width (Note 9)Interrupt Input High Time 1t C Interrupt Input Low Time 1t C Timer 1,2,3,Input High Time 1t C Timer 12,3,Input Low Time 1t C Reset Pulse Width

μs

Comparators AC and DC Characteristics

V CC =5V,?40?C ≤T A ≤+125?C.

Parameter

Conditions

Min

Typ

Max

Units Input Offset Voltage (Note 12)0.4V ≤V IN ≤V CC ?1.5V

±5±25

mV Input Common Mode Voltage Range 0.4

V CC ?1.5

V Voltage Gain

100

dB Low Level Output Current V OL =0.4V ?1.6mA High Level Output Current

V OH =V CC ?0.4V

1.6

mA DC Supply Current per Comparator (When Enabled)

150

μA

Response Time (Note 13)200mV step input 100mV Overdrive,600ns Comparator Enable Time

600

C O P 8S G F a m i l y

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Typical Performance Characteristics

T A =25?C (unless otherwise specified)

1013174910131750

1013175110131752

COP8SG Family

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4.0Pin Descriptions

The COP8SGx I/O structure enables designers to reconfig-ure the microcontroller’s I/O functions with a single instruc-tion.Each individual I/O pin can be independently configured as output pin low,output high,input with high impedance or input with weak pull-up device.A typical example is the use of I/O pins as the keyboard matrix input lines.The input lines can be programmed with internal weak pull-ups so that the input lines read logic high when the keys are all open.With a key closure,the corresponding input line will read a logic zero since the weak pull-up can easily be overdriven.When the key is released,the internal weak pull-up will pull the input line back to logic high.This eliminates the need for external pull-up resistors.The high current options are avail-able for driving LEDs,motors and speakers.This flexibility helps to ensure a cleaner design,with less external compo-nents and lower costs.Below is the general description of all available pins.

V CC and GND are the power supply pins.All V CC and GND pins must be connected.

CKI is the clock input.This can come from the Internal R/C oscillator,external,or a crystal oscillator (in conjunction with CKO).See Oscillator Description section.

RESET is the master reset input.See Reset description section.

Each device contains four bidirectional 8-bit I/O ports (C,G,L and F),where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),output or TRI-STATE under program control.Three data memory address locations are allocated for each of these I/O ports.Each I/O port has two associated 8-bit memory mapped registers,the CONFIGURATION register and the output DATA register.A memory mapped address is also reserved for the input pins of each I/O port.(See the memory map for the various addresses associated with the I/O ports.)Figure 4shows the I/O port configurations.The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown be-low:

CONFIGURATION

DATA Register

Port Set-Up

00Hi-Z Input

(TRI-STATE Output)01Input with Weak Pull-Up 10Push-Pull Zero Output 1

Push-Pull One Output

Port L is an 8-bit I/O port.All L-pins have Schmitt triggers on the inputs.

Port L supports the Multi-Input Wake Up feature on all eight pins.Port L has the following alternate pin functions:L7Multi-input Wakeup or T3B (Timer T3B Input)L6Multi-input Wakeup or T3A (Timer T3A Input)L5Multi-input Wakeup or T2B (Timer T2B Input)L4Multi-input Wakeup or T2A (Timer T2A Input)

L3Multi-input Wakeup and/or RDX (USART Receive)L2Multi-input Wakeup or TDX (USART Transmit)L1Multi-input Wakeup and/or CKX (USART Clock)L0Multi-input Wakeup

Port G is an 8-bit port.Pin G0,G2–G5are bi-directional I/O ports.Pin G6is always a general purpose Hi-Z input.All pins have Schmitt Triggers on their inputs.Pin G1serves as the

dedicated WATCHDOG output with weak pullup if WATCHDOG feature is selected by the Mask Option reg-ister.The pin is a general purpose I/O if WATCHDOG feature is not selected.If WATCHDOG feature is selected,bit 1of the Port G configuration and data register does not have any effect on Pin G1setup.Pin G7is either input or output depending on the oscillator option selected.With the crystal oscillator option selected,G7serves as the dedicated output pin for the CKO clock output.With the internal R/C or the external oscillator option selected,G7serves as a gen-eral purpose Hi-Z input pin and is also used to bring the device out of HALT mode with a low to high transition on G7.Since G6is an input only pin and G7is the dedicated CKO clock output pin (crystal clock option)or general purpose input (R/C or external clock option),the associated bits in the data and configuration registers for G6and G7are used for special purpose functions as outlined below.Reading the G6and G7data bits will return zeroes.

Each device will be placed in the HALT mode by writing a “1”to bit 7of the Port G Data Register.Similarly the device will be placed in the IDLE mode by writing a “1”to bit 6of the Port G Data Register.

Writing a “1”to bit 6of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alter-nate phase of the SK clock.The G7configuration bit,if set high,enables the clock start up delay after HALT when the R/C clock configuration is used.

Config.Reg.

Data Reg.G7CLKDLY HALT G6

Alternate SK

IDLE

Port G has the following alternate features:

G7CKO Oscillator dedicated output or general purpose

input

G6SI (MICROWIRE Serial Data Input)G5SK (MICROWIRE Serial Clock)

G4SO (MICROWIRE Serial Data Output)G3T1A (Timer T1I/O)

G2T1B (Timer T1Capture Input)

G1WDOUT WATCHDOG and/or CLock Monitor if WATCH-DOG enabled,otherwise it is a general purpose I/O G0INTR (External Interrupt Input)

Port C is an 8-bit I/O port.The 40-pin device does not have a full complement of Port C pins.The unavailable pins are not terminated.A read operation on these unterminated pins will return unpredictable values.The 28pin device do not offer Port C.On this device,the associated Port C Data and Configuration registers should not be used.

Port F is an 8-bit I/O port.The 28--pin device does not have a full complement of Port F pins.The unavailable pins are not terminated.A read operation on these unterminated pins will return unpredictable values.

Port F1–F3are used for Comparator 1.Port F4–F6are used for Comparator 2.

The Port F has the following alternate features:F6COMP2OUT (Comparator 2Output)

F5COMP2+IN (Comparator 2Positive Input)F4COMP2-IN (Comparator 2Negative Input)F3COMP1OUT (Comparator 1Output)

F2COMP1+IN (Comparator 1Positive Input)F1COMP1-IN (Comparator 1Negative Input)

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4.0Pin Descriptions(Continued)

Note:For compatibility with existing software written for COP888xG devices and with existing Mask ROM devices,a read of the Port I input pins (address xxD7)will return the same data as reading the Port F input pins(address xx96).It is recommended new applications which will go to production with the COP8SGx use the Port F addresses.Note that compatible ROM devices contains the input only Port I instead of the bi-directional Port F.

Port D is an8-bit output port that is preset high when RESET goes low.The user can tie two or more D port outputs (except D2)together in order to get a higher drive.

Note:Care must be exercised with the D2pin operation.At RESET,the external loads on this pin must ensure that the output voltages stay above0.7V CC to prevent the chip from entering special modes.Also keep the external loading on D2to less than1000pF.

10131710 FIGURE4.I/O Port Configurations

10131712 FIGURE5.I/O Port Configurations—Output Mode

10131711

FIGURE6.I/O Port Configurations—Input Mode

COP8SG

Family

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5.0Functional Description

The architecture of the devices are a modified Harvard ar-chitecture.With the Harvard architecture,the program memory ROM is separated from the data store memory (RAM).Both ROM and RAM have their own separate ad-dressing space with separate address buses.The architec-ture,though based on the Harvard architecture,permits transfer of data from ROM to RAM.

5.1CPU REGISTERS

The CPU can do an 8-bit addition,subtraction,logical or shift operation in one instruction (t C )cycle time.There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7bits of the program counter (PC)PL is the lower 8bits of the program counter (PC)

B is an 8-bit RAM address pointer,which can be optionally post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer,which can be optionally post auto incremented or decremented.

S is the 8-bit Segment Address Register used to extend the lower half of the address range (00to 7F)into 256data segments of 128bytes each.

SP is the 8-bit stack pointer,which points to the subroutine/interrupt stack (in RAM).With reset the SP is initialized to RAM address 02F Hex (devices with 64bytes of RAM),or initialized to RAM address 06F Hex (devices with 128bytes of RAM).

All the CPU registers are memory mapped with the excep-tion of the Accumulator (A)and the Program Counter (PC).5.2PROGRAM MEMORY

The program memory consists of varies sizes of ROM.These bytes may hold program instructions or constant data (data tables for the LAID instruction,jump vectors for the JID instruction,and interrupt vectors for the VIS instruction).The program memory is addressed by the 15-bit program counter (PC).All interrupts in the device vector to program memory location 0FF Hex.The contents of the program memory read 00Hex in the erased state.Program execution starts at location 0after RESET.

5.3DATA MEMORY

The data memory address space includes the on-chip RAM and data registers,the I/O registers (Configuration,Data and Pin),the control registers,the MICROWIRE/PLUS SIO shift register,and the various registers,and counters associated with the timers (with the exception of the IDLE timer).Data memory is addressed directly by the instruction or indirectly by the B,X and SP pointers.

The data memory consists of 256or 512bytes of RAM.Sixteen bytes of RAM are mapped as “registers”at ad-

dresses 0F0to 0FE Hex.These registers can be loaded immediately,and also decremented and tested with the DRSZ (decrement register and skip if zero)instruction.The memory pointer registers X,SP and B are memory mapped into this space at address locations 0FC to 0FE Hex respec-tively,with the other registers (except 0FF)being available for general usage.

The instruction set permits any bit in memory to be set,reset or tested.All I/O and registers (except A and PC)are memory mapped;therefore,I/O bits and register bits can be directly and individually set,reset and tested.The accumu-lator (A)bits can also be directly and individually tested.

Note:RAM contents are undefined upon power-up.

5.4DATA MEMORY SEGMENT RAM EXTENSION

Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S).

The data store memory is either addressed directly by a single byte address within the instruction,or indirectly rela-tive to the reference of the B,X,or SP pointers (each contains a single-byte address).This single-byte address allows an addressing range of 256locations from 00to FF hex.The upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously.With the exception of the RAM register memory from address locations 00F0to 00FF,all RAM memory is memory mapped with the upper bit of the single-byte ad-dress being equal to zero.This allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000to 00FF)is extended.If this upper bit equals one (representing address range 0080to 00FF),then address extension does not take place.Alternatively,if this upper bit equals zero,then the data segment extension register S is used to extend the base address range (from 0000to 007F)from XX00to XX7F,where XX represents the 8bits from the S register.Thus the 128-byte data segment extensions are located from addresses 0100to 017F for data segment 1,0200to 027F for data segment 2,etc.,up to FF00to FF7F for data segment 255.The base address range from 0000to 007F represents data segment 0.

Figure 7illustrates how the S register data memory exten-sion is used in extending the lower half of the base address range (00to 7F hex)into 256data segments of 128bytes each,with a total addressing range of 32kbytes from XX00to XX7F.This organization allows a total of 256data seg-ments of 128bytes each with an additional upper base segment of 128bytes.Furthermore,all addressing modes are available for all data segments.The S register must be changed under program control to move from one data segment (128bytes)to another.However,the upper base segment (containing the 16memory registers,I/O registers,control registers,etc.)is always available regardless of the contents of the S register,since the upper base segment (address range 0080to 00FF)is independent of data seg-ment extension.

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5.0Functional Description(Continued)

The instructions that utilize the stack pointer(SP)always reference the stack as part of the base segment(Segment 0),regardless of the contents of the S register.The S register is not changed by these instructions.Consequently,the stack(used with subroutine linkage and interrupts)is always located in the base segment.The stack pointer will be initial-ized to point at data memory location006F as a result of reset.

The128bytes of RAM contained in the base segment are split between the lower and upper base segments.The first 112bytes of RAM are resident from address0000to006F in the lower base segment,while the remaining16bytes of RAM represent the16data memory registers located at addresses00F0to00FF of the upper base segment.No RAM is located at the upper sixteen addresses(0070to 007F)of the lower base segment.

Additional RAM beyond these initial128bytes,however,will always be memory mapped in groups of128bytes(or less) at the data segment address extensions(XX00to XX7F)of the lower base segment.The additional384bytes of RAM in this device are memory mapped at address locations0100 to017F,0200to027F and0300to037F hex.

Memory address ranges0200to027F and0300to037F are unavailable on the COP8SGx5and,if read,will return un-derfined data.

5.5ECON(CONFIGURATION)REGISTER

For compatibility with COP8SGx7devices,mask options are defined by an ECON Configuration Register which is pro-grammed at the same time as the program code.Therefore, the register is programmed at the same time as the program memory.The format of the ECON register is as follows:

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0 X POR SECURITY CKI2CKI1WATCH F-Port HALT

DOG

Bit7=x This is for factory test.The polarity is“Don’t

Care.”

Bit6=1Power-on reset enabled.

=0Power-on reset disabled.

Bit5=1Security enabled.

Bits4,3=0,0External CKI option selected.G7is avail-

able as a HALT restart and/or general pur-

pose input.CKI is clock input.

=0,1R/C oscillator option selected.G7is avail-

able as a HALT restart and/or general pur-

pose input.CKI clock input.Internal R/C

components are supplied for maximum R/C

frequency.

=1,0Crystal oscillator with on-chip crystal bias

resistor disabled.G7(CKO)is the clock

generator output to crystal/resonator.

=1,1Crystal oscillator with on-chip crystal bias

resistor enabled.G7(CKO)is the clock gen-

erator output to crystal/resonator.

Bit2=1WATCHDOG feature disabled.G1is a gen-

eral purpose I/O.

=0WATCHDOG feature enabled.G1pin is

WATCHDOG output with weak pullup.

Bit1=1Force port I compatibility.Disable port F

outputs and pull-ups.This is intended for

compatibility with existing code and Mask

ROMMed devices only.This bit should be

10131745

FIGURE7.RAM Organization

COP8SG

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5.0Functional Description

(Continued)

programmed to 0for all other applications.

Enable full port F capability.Bit 0

=1HALT mode disabled.=0

HALT mode enabled.

5.6USER STORAGE SPACE IN EPROM

The ECON register is outside of the normal address range of the ROM and can not be accessed by the executing soft-ware.

The COP8assembler defines a special ROM section type,CONF,into which the ECON may be coded.Both ECON and User Data are programmed automatically by programmers that are certified by National.

The following examples illustrate the declaration of ECON and the User information.Syntax:

[label:].sect econ,conf

.db value ;1byte,

;configures options

.db .endsect ;up to 8bytes

Example:The following sets a value in the ECON register and User Identification for a COP8SGR728M7.The ECON bit values shown select options:Power-on enabled,Security disabled,Crystal oscillator with on-chip bias disabled,WATCHDOG enabled and HALT mode enabled..sect econ,conf .db 0x55;por,xtal,wd,halt .db 'my v1.00';user data declaration .endsect

5.7OTP SECURITY

The device has a security feature that,when enabled,pre-vents external reading of the OTP program memory.The security bit in the ECON register determines,whether secu-rity is enabled or disabled.If the security feature is disabled,the contents of the internal EPROM may be read.

If the security feature is enabled,then any attempt to externally read the contents of the EPROM will result in the value FF Hex being read from all program locations Under no circumstances can a secured part be read.In addition,with the security feature enabled,the write opera-tion to the EPROM program memory and ECON register is inhibited.The ECON register is readable regardless of the state of the security bit.The security bit,when set,cannot be erased,even in windowed packages.If the security bit is set in a device in a windowed package,that device may be erased but will not be further programmable.

If security is being used,it is recommended that all other bits in the ECON register be programmed first.Then the security bit can be programmed.

5.8ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that era-sure begins to occur when exposed to light with wavelengths shorter than approximately 4000Angstroms (?).It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000?-4000?range.

After programming,opaque labels should be placed over the window of windowed devices to prevent unintentional era-sure.Covering the window will also prevent temporary func-tional failure due to the generation of photo currents.

The recommended erasure procedure for windowed devices is exposure to short wave ultraviolet light which has a wave-length of 2537Angstroms (?).The integrated dose (i.e.UV intensity X exposure time)for erasure should be a minimum of 15W-sec/cm 2.5.9RESET

The devices are initialized when the RESET pin is pulled low or the On-chip Power-On Reset is enabled.

The following occurs upon initialization:

Port L:TRI-STATE (High Impedance Input)Port C:TRI-STATE (High Impedance Input)Port G:TRI-STATE (High Impedance Input)Port F:TRI-STATE (High Impedance Input)Port D:HIGH

PC:CLEARED to 0000

PSW,CNTRL and ICNTRL registers:CLEARED SIOR:

UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on T2CNTRL:CLEARED T3CNTRL:CLEARED

Accumulator,Timer 1,Timer 2and Timer 3:

RANDOM after RESET with crystal clock option (power already applied)

UNAFFECTED after RESET with R/C clock option (power already applied)

RANDOM after RESET at power-on WKEN,WKEDG:CLEARED WKPND:RANDOM SP (Stack Pointer):

Initialized to RAM address 06F Hex B and X Pointers:

UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on S Register:CLEARED RAM:

UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on USART:

PSR,ENU,ENUR,ENUI:Cleared except the TBMT bit which is set to https://www.wendangku.net/doc/c06705287.html,PARATORS:CMPSL;CLEARED WATCHDOG (if enabled):

10131713

FIGURE 8.Reset Logic

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5.0Functional Description(Continued)

The device comes out of reset with both the WATCH-

DOG logic and the Clock Monitor detector armed,with the

WATCHDOG service window bits set and the Clock Monitor

bit set.The WATCHDOG and Clock Monitor circuits are

inhibited during reset.The WATCHDOG service window bits

being initialized high default to the maximum WATCHDOG

service window of64k t C clock cycles.The Clock Monitor bit

being initialized high will cause a Clock Monitor error follow-

ing reset if the clock has not reached the minimum specified

frequency at the termination of reset.A Clock Monitor error

will cause an active low error output on pin G1.This error

output will continue until16t C–32t C clock cycles following

the clock frequency reaching the minimum specified value,

at which time the G1output will go high.

5.9.1External Reset

The RESET input when pulled low initializes the device.The

RESET pin must be held low for a minimum of one instruc-

tion cycle to guarantee a valid reset.During Power-Up ini-

tialization,the user must ensure that the RESET pin is held

low until the device is within the specified V CC voltage.An

R/C circuit on the RESET pin with a delay5times(5x)

greater than the power supply rise time or15μs whichever is

greater,is recommended.Reset should also be wide enough

to ensure crystal start-up upon Power-Up.

RESET may also be used to cause an exit from the HALT

mode.

A recommended reset circuit for this device is shown in

Figure9.

5.9.2On-Chip Power-On Reset

The on-chip reset circuit is selected by a bit in the ECON

reset as V CC rises to a voltage level above2.0V.The on-chip

reset circuitry is able to detect both fast and slow rise times

on V CC(V CC rise time between10ns and50ms).To guar-

antee an on-chip power-on-reset,V CC must start at a voltage

less than the start voltage specified in the DC characteris-

tics.Also,if V CC be lowered to the start voltage before

powering back up to the operating range.If this is not pos-

sible,it is recommended that external reset be used.

Under no circumstances should the RESET pin be allowed

to float.If the on-chip Power-On Reset feature is being used,

RESET pin should be connected directly,or through a

pull-up resistor,to V CC.The output of the power-on reset

detector will always preset the Idle timer to0FFF(4096t C).

At this time,the internal reset will be generated.

If the Power-On Reset feature is enabled,the internal reset

will not be turned off until the Idle timer underflows.The

internal reset will perform the same functions as external

reset.The user is responsible for ensuring that V CC is at the

minimum level for the operating frequency within the4096

t C.After the underflow,the logic is designed such that no

additional internal resets occur as long as V CC remains

above2.0V.

The contents of data registers and RAM are unknown fol-

lowing the on-chip reset.

10131714

RC>5x power supply rise time or15μs,whichever is greater.

FIGURE9.Reset Circuit Using External Reset

10131715

FIGURE10.Reset Timing(Power-On Reset Enabled)

with V CC Tied to RESET

10131716

FIGURE11.Reset Circuit Using Power-On Reset

COP8SG

Family

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5.0Functional Description

(Continued)

5.10OSCILLATOR CIRCUITS

There are four clock oscillator options available:Crystal Oscillator with or without on-chip bias resistor,R/C Oscillator with on-chip resistor and capacitor,and External Oscillator.The oscillator feature is selected by programming the ECON register,which is summarized in Table 1.

TABLE 1.Oscillator Option

ECON4ECON3Oscillator Option

00External Oscillator

10Crystal Oscillator without Bias Resistor 01R/C Oscillator

Crystal Oscillator with Bias Resistor

5.10.1Crystal Oscillator

The crystal Oscillator mode can be selected by programming ECON Bit 4to 1.CKI is the clock input while G7/CKO is the clock generator output to the crystal.An on-chip bias resistor connected between CKI and CKO can be enabled by pro-gramming ECON Bit 3to 1with the crystal oscillator option selection.The value of the resistor is in the range of 0.5M to 2M (typically 1.0M).Table 2shows the component values required for various standard crystal values.Resistor R2is only used when the on-chip bias resistor is disabled.Figure 12shows the crystal oscillator connection diagram.

TABLE 2.Crystal Oscillator Configuration,

T A =25?C,V CC =5V R1(k ?)

R2(M ?)

C1(pF)C2(pF)CKI Freq.(MHz)

011818150120201001252545.6

100

100–156

0.455

5.10.2External Oscillator

The External Oscillator mode can be selected by program-ming ECON Bit 3to 0and ECON Bit 4to 0.CKI can be driven by an external clock signal provided it meets the

specified duty cycle,rise and fall times,and input levels.G7/CKO is available as a general purpose input G7and/or Halt control.Figure 13shows the external oscillator connec-tion diagram.5.10.3R/C Oscillator

The R/C Oscillator mode can be selected by programming ECON Bit 3to 1and ECON Bit 4to 0.In R/C oscillation mode,CKI is left floating,while G7/CKO is available as a general purpose input G7and/or HALT control.The R/C controlled oscillator has on-chip resistor and capacitor for maximum R/C oscillator frequency operation.The maximum frequency is 5MHz ±35%for V CC between 4.5V to 5.5V and temperature range of ?40?C to +85?C.For max fre-quency operation,the CKI pin should be left floating.For lower frequencies,an external capacitor should be con-nected between CKI and either V CC or GND.Immunity of the R/C oscillator to external noise can be improved by connect-ing one half the external capacitance to V CC and one half to GND.PC board trace length on the CKI pin should be kept as short as possible.Table 3shows the oscillator frequency as a function of external capacitance on the CKI pin.Figure 14shows the R/C oscillator configuration.

TABLE 3.R/C Oscillator Configuration,?40?C to +85?C,V CC =4.5V to 5.5V,OSC Freq.Variation of ±35%External Capacitor (pF)*

R/C OSC Freq

(MHz)

Instr.Cycle (μs)

05 2.094 2.5522 5.01251106100

32kHz

312.5

*Assumes 3-5pF board capacitance.

With On-Chip Bias Resistor Without On-Chip Bias Resistor

1013171710131718

FIGURE 12.Crystal Oscillator

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