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KK74LV240N中文资料

TECHNICAL DATA

74LV240

OCTAL BUFFER/LINE DRIVE; 3-STATE

The KK 74LV240 is a low-voltage Si-gate CMOS device and is pin and function compatible with KK 74HC/HCT240.

The KK 74LV240 is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state.

The KK 74LV240 is identical to the KK outputs.

? Outputs Directly Interface to CMOS, NMOS, and TTL ? Operating Voltage Range: 1.2 to 3.6 V

? Low Input Current: 1.0 μA, 0.1 μА at Т = 25 °С ? Output Current: 8 mA at V CC = 3.0 V

? High Noise Immunity Characteristic of CMOS Devices

FUNCTION TABLE

H= high level L = low level X = don’t care

Z = high impedance

LOGIC DIAGRAM

PIN 20=V CC PIN 10 = GND

1A 01Y 02A 02Y 01A 21Y 22A 0

2Y 01A 11Y 12A 12Y 11A 31Y 32A 12Y 1

1OE 2OE

DATA INPUTS

INVERTING OUTPUTS

OUTPUT ENABLES

PIN ASSIGNMENT

V CC GND

2OE 1A 2Y 1A 2Y 1A 2Y 1A 2Y 1Y 02A 31Y 12A 21Y 22A 11Y 32A 0

MAXIMUM RATINGS*

Symbol Parameter Value

Unit V CC DC supply voltage -0.5 to +5.0 V

I IK *1DC Input diode current ±20 mA

I OK *2DC Output diode current ±50 mA

I O *3DC Output source or sink current ±35 mA

I CC DC V CC current ±70 mA

I GND DC GND current ±70 mA

P D Power dissipation per package: *4

Plastic DIP SO 750

500

Tstg Storage Temperature -65 to +150 °C

T L Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm

(SO Package) from Case for 4 Seconds

260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

*1 V I < -0.5 V or V I > V CC + 0.5 V.

*2 V O < -0.5 V or V O > V CC + 0.5 V.

*3 -0.5 V < V O < V CC + 0.5 V.

*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SO Package: : - 8 mW/°C from 70° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min

Max

Unit V CC DC Supply Voltage 1.2 3.6 V

V I Input Voltage 0 V CC V

V O Output Voltage 0 V CC V

T A Operating Temperature, All Package Types -40 +125 °C

t r, t f Input Rise and Fall Time (Figure 1) V CC =1.2 V

V CC =2.0 V

V CC =3.0 V

V CC =3.6 V 0

1000

700

500

400

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND≤(V IN or V OUT)≤V CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Test

V CC Guaranteed Limit Symbol Parameter conditions V 25°C-40°C to 85°C125°C Unit

min max min max min max

V IH HIGH level input

voltage 1.2

2.0

3.0

3.6

0.9

1.4

2.1

2.5

0.9

1.4

2.1

2.5

0.9

1.4

2.1

2.5

V IL LOW level input

voltage 1.2

2.0

3.0

3.6

0.3

0.6

0.9

1.1

0.3

0.6

0.9

1.1

0.3

0.6

0.9

1.1

V OH HIGH level output

voltage V I = V IH or V IL

I O = -50 μА

1.2

2.0

3.0

3.6

1.1

1.92

2.92

3.52

1.0

1.9

2.9

3.5

1.0

1.9

2.9

3.5

V I = V IH or V IL

I O = -8 mА

3.0 2.48- 2.34- 2.20 - V

V OL LOW level output

voltage V I = V IH or V IL

I O = 50 μА

1.2

2.0

3.0

3.6

0.09

0.1

V I = V IH or V IL

I O = 8 mА

3.0- 0.33- 0.4 - 0.5 V

I I Input current V I = V CC or 0 V * - ±0.1- ±1.0- ±1.0 μА

I OZ Three state leakage

current 3-state outputs

V I (01,19) = V IH

V O =V CC or 0 V

1.2

- ±0.5- ±5 - ±10 μА

I CC Supply current V I =V CC or 0 V

I O = 0 μА

* - 8.0- 80 - 160 μА* V CC = 3.3 ± 0.3 V

AC ELECTRICAL CHARACTERISTICS (C L =50 pF, t r =t f =6.0 ns)

* V CC = 3.3 ± 0.3 V

1A or 2A n 1Y or 2Y n V V CC

GND GND

V V OL CC

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

DEVICE UNDER TEST

OUTPUT

1 k C L

TEST POINT

Connect to V CC when testing t PLZ and t PZL Connect to GND when testing t PHZ and t PZH

DEVICE UNDER TEST

OUTPUT

C L

TEST POINT

* Includes all probe and jig capacitance

Figure 3. Test Circuit

Figure 4. Test Circuit