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Am29LV400B-120ECB中文资料

PRELIMINARY

Publication# 20514Rev: C Amendment/+1Issue Date: March 1998

Am29LV400

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

s Single power supply operation

—Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications —Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s High performance

—Full voltage range: access times as fast as 100 ns —Regulated voltage range: access times as fast as 90 ns s Ultra low power consumption (typical values at 5 MHz)—200 nA Automatic Sleep mode current —200 nA standby mode current —10 mA read current

—20 mA program/erase current s Flexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)—One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)—Supports full chip erase —Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within that sector

Sectors can be locked via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

s Top or bottom boot block configurations available s Embedded Algorithms

—Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors —Embedded Program algorithm automatically writes and verifies data at specified addresses s Typical 1,000,000 write cycles per sector (100,000 cycles minimum guaranteed)s Package option —48-ball FBGA —48-pin TSOP —44-pin SO

s Compatibility with JEDEC standards —Pinout and software compatible with single-power supply Flash —Superior inadvertent write protection s Data# Polling and toggle bits

—Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

GENERAL DESCRIPTION

The Am29LV400 is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3.0 volt V CC supply. No V PP is required for write or erase opera-tions. The device can also be programmed in standard EPROM programmers.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten-tion the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com-mands are written to the command register using standard microprocessor write timings. Register con-tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto-matically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase com-mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically pre-programs the array (if it is not already programmed) be-fore executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V CC detector that automatically inhibits write opera-tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem-ory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective-ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun-neling. The data is programmed using hot electron injection.

Am29LV4002

3Am29LV400

PRODUCT SELECTOR GUIDE

Note:See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29LV400

Speed Options

Regulated Voltage Range: V CC =3.0–3.6 V -90R

Full Voltage Range: V CC = 2.7–3.6 V

-100-120-150Max access time, ns (t ACC )90100120150Max CE# access time, ns (t CE )90100120150Max OE# access time, ns (t OE )

4040

40

55

Input/Output Buffers X-Decoder

Y-Decoder Chip Enable Output Enable

Logic

Erase Voltage Generator

PGM Voltage Generator

Timer

V CC Detector

State Control Command Register

V CC V SS WE#BYTE#

CE#OE#

STB

STB

DQ0–DQ15 (A-1)

Sector Switches RY/BY#

RESET#

Data Latch

Y-Gating

Cell Matrix

A d d r e s s L a t c h

A0–A17

20514C-1

20514C-2 Am29LV4004

20514C-3 5Am29LV400

Special Handling Instructions for Fine PItch Ball Grid Array (FBGA)

Special handling is required for Flash Memory products in FBGA packages.Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. T h e p a c k a g e a n d/o r d a t a i n t e g r i t y m a y b e compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

PIN CONFIGURATION

A0–A17=18 addresses

DQ0–DQ14=15 data inputs/outputs

DQ15/A-1=DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode) BYTE#=Selects 8-bit or 16-bit mode

CE#=Chip enable

OE#= Output enable

WE#=Write enable

RESET#=Hardware reset pin, active low

RY/BY#= Ready/Busy# output

V CC= 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances) V SS=Device ground

NC=Pin not connected internally LOGIC SYMBOL

20514C-4 18

16 or 8

DQ0–DQ15

(A-1)

A0–A17

CE#

OE#

WE#

RESET#

BYTE#RY/BY#

Am29LV4006

7Am29LV400

ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION Am29LV400

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase

C

E 70R Am29LV400T OPTIONAL PROCESSING Blank =Standard Processing B =Burn-in

(Contact an AMD representative for more information)TEMPERATURE RANGE

C =Commercial (0°C to +70°C)I =Industrial (–40°C to +85°C)E =Extended (–55°C to +125°C)

PACKAGE TYPE E =48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F =48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

S =44-Pin Small Outline Package (SO 044)WA =48-ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package SPEED OPTION

See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T =Top Sector B =Bottom Sector

Valid Combinations

Am29LV400T70R,Am29LV400B70R EC, EI, FC, FI, SC, SI, WAC

Am29LV400T80,Am29LV400B80EC, EI, EE, FC, FI, FE,SC, SI, SE,WAC, WAI, WAE

Am29LV400T90,Am29LV400B90Am29LV400T120,Am29LV400B120

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the com-mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in-puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1.Am29LV400 Device Bus Operations

Legend:

L = Logic Low = V IL, H = Logic High = V IH, V ID = 12.0 ± 0.5 V, X = Don’t Care, A IN = Addresses In, D IN = Data In, D OUT = Data Out Note:Addresses are A17:A0 in word mode (BYTE# = V IH), A17:A-1 in byte mode (BYTE# = V IL).

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configura-tion. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and control-led by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are ac-tive and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output con-trol and gates array data to the output pins. WE# should remain at V IH. The BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-tent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica-tions and to Figure 12 for the timing diagram. I CC1 in the DC Characteristics table represents the active cur-rent specification for reading array data.

Writing Commands/Command Sequences To write a command or command sequence (which in-cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to V IH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more in-formation.

An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector ad-dress” consists of the address bits required to uniquely select a sector. The “Command Definitions” section

Operation CE#OE#WE#RESET#Addresses

(See Note)

DQ0–

DQ7

DQ8–DQ15

BYTE#

= V IH

BYTE#

= V IL

Read L L H H A IN D OUT D OUT DQ8–DQ14 = High-Z,

DQ15 = A-1 Write L H L H A IN D IN D IN

Standby V CC ±

0.3 V

X X

V CC ±

0.3 V

X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z Temporary Sector Unprotect X X X V ID A IN D IN D IN High-Z

Am29LV4008

has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter-nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

I CC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris-tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde-pendent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or program-ming, the device draws active current until the operation is completed.

I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t A C C + 30 ns. The automatic sl eep m ode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-ting the device to reading array data. When the RE-SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (I CC4). If RESET# is held at V IL but not within V SS±0.3 V, the standby current will be greater.

If RESET# is asserted during a program or erase oper-ation, the RY/BY# pin remains a “0” (busy) until the in-ternal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo-rithms). The system can read data t RH after the RE-SET# pin returns to V IH.

Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 13 for the timing diagram. Output Disable Mode

When the OE# input is at V IH, output from the device is

9Am29LV400

Am29LV40010

Table 2.

Am29LV400T Top Boot Block Sector Address Table

Table 3.Am29LV400B Bottom Boot Block Sector Address Table

Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A171:A0 in word mode. See “Word/Byte Configuration” section for more information.

Sector A17A16A15A14A13A12Sector Size (Kbytes/Kwords)Address Range (in hexadecimal)(x8)

Address Range (x16)

Address Range SA0000X X X 64/3200000h–0FFFFh 00000h–07FFFh SA1001X X X 64/3210000h–1FFFFh 08000h–0FFFFh SA2010X X X 64/3220000h–2FFFFh 10000h–17FFFh SA3011X X X 64/3230000h–3FFFFh 18000h–1FFFFh SA4100X X X 64/3240000h–4FFFFh 20000h–27FFFh SA5101X X X 64/3250000h–5FFFFh 28000h–2FFFFh SA6110X X X 64/3260000h–6FFFFh 30000h–37FFFh SA71110X X 32/1670000h–77FFFh 38000h–3BFFFh SA81111008/478000h–79FFFh 3C000h–3CFFFh SA91111018/47A000h–7BFFFh 3D000h–3DFFFh SA10

1

1

1

1

1

X

16/8

7C000h–7FFFFh

3E000h–3FFFFh

Sector A17A16A15A14A13A12Sector Size (Kbytes/Kwords)

Address Range (in hexadecimal)(x8)

Address Range (x16)

Address Range SA000000X 16/800000h–03FFFh 00000h–01FFFh SA10000108/404000h–05FFFh 02000h–02FFFh SA20000118/406000h–07FFFh 03000h–03FFFh SA30001X X 32/1608000h–0FFFFh 04000h–07FFFh SA4001X X X 64/3210000h–1FFFFh 08000h–0FFFFh SA5010X X X 64/3220000h–2FFFFh 10000h–17FFFh SA6011X X X 64/3230000h–3FFFFh 18000h–1FFFFh SA7100X X X 64/3240000h–4FFFFh 20000h–27FFFh SA8101X X X 64/3250000h–5FFFFh 28000h–2FFFFh SA9110X X X 64/3260000h–6FFFFh 30000h–37FFFh SA10

1

1

1

X

X

X

64/32

70000h–7FFFFh

38000h–3FFFFh

Autoselect Mode

The autoselect mode provides manufacturer and de-vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V ID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corre-sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.

Table 4.Am29LV400 Autoselect Codes (High Voltage Method) L = Logic Low = V IL, H = Logic High = V IH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hard-ware sector unprotection feature re-enables both pro-gram and erase operations in previously protected sectors.

Sector protection/unprotection is implemented using programming equipment, and requires V ID on address pin A9 and OE#. Publication number 20873 contains further details; contact an AMD representative to re-quest a copy.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash? Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Temporary Sector Unprotect

This feature allows temporary unprotection of previ-ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE-SET# pin to V ID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V ID is removed from the RE-SET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 21 shows the timing diagrams, for this feature.

Description Mode CE#OE#WE#A17

to

A12

A11

to

A10A9

A8

to

A7A6

A5

to

A2A1A0

DQ8

to

DQ15

DQ7

to

DQ0

Manufacturer ID: AMD L L H X X V ID X L X L L X01h

Device ID:

Am29LV400 (Top Boot Block)Word L L H

X X V ID X L X L H

22h B9h Byte L L H X B9h

Device ID: Am29LV400 (Bottom Boot Block)Word L L H

X X V ID X L X L H

22h BAh Byte L L H X BAh

Sector Protection Verification L L H SA X V ID X L X H L X

01h

(protected) X

00h

(unprotected)

11Am29LV400

Am29LV40012

Figure 1.Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for com-mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise.Low V CC Write Inhibit

When V CC is less than V LKO , the device does not ac-cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO . The system must provide the proper signals to the control pins to prevent uninten-tional writes when V CC is greater than V LKO .Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =V IL , CE# = V IH or WE# = V IH . To initiate a write cycle,CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

START

Perform Erase or Program Operations

RESET# = V IH

Temporary Sector Unprotect Completed

(Note 2)

RESET# = V ID

(Note 1)Notes:

1.All protected sectors unprotected.

2.All previously protected sectors are protected once

again.

20514C-5

COMMAND DEFINITIONS

Writing specific address and data commands or se-quences into the command register initiates device op-erations. Table 5 defines the valid register command sequences. Writing incorrect address and data val-ues or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em-bedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys-tem can read array data using the standard read tim-ings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Sus-pend/Erase Resume Commands” for more information on this mode.

The system must issue the reset command to re-ena-ble the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com-mand” section, next.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame-ters, and Figure 12 shows the timing diagram. Reset Command

Writing the reset command to the device resets the de-vice to reading array data. Address bits are don’t care for this command.

The reset command may be written between the se-quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig-nores reset commands until the operation is complete. The reset command may be written between the se-quence cycles in a program command sequence be-fore programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.The reset command may be written between the se-quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read-ing array data (also applies during Erase Suspend). See “AC Characteristics” for parameters, and to Figure 13 for the timing diagram.

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V ID on address bit A9.

The autoselect command sequence is initiated by writ-ing two unlock cycles, followed by the autoselect com-mand. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufac-turer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) re-turns 01h if that sector is protected, or 00h if it is unpro-tected. Refer to Tables 2 and 3 for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program-ming is a four-bus-cycle operation. The program com-mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or tim-ings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and ad-dresses are no longer latched. The system can deter-mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status”for information on these status bits.

13Am29LV400

Any commands written to the device during the Em-bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program-ming operation. The Byte Program command se-quence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc-cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0”to a “1”.

Figure 2 illustrates the algorithm for the program oper-ation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 16 for timing diagrams.

Note: See T able 5 for program command sequence.

Figure 2.Program Operation Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algo-rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con-trols or timings during these operations. Table 5 shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embed-ded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately ter-minates the operation. The Chip Erase command se-quence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase op-eration by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these sta-tus bits. When the Embedded Erase algorithm is com-plete, the device returns to reading array data and addresses are no longer latched.

Figure 3 illustrates the algorithm for the erase opera-tion. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad-ditional unlock write cycles are then followed by the ad-dress of the sector to be erased, and the sector erase command. Table 5 shows the address and data re-quirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algo-rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim-ings during these operations.

After the command sequence is written, a sector erase time-out of 50 μs begins. During the time-out period, additional sector addresses and sector erase com-mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec-tors may be from one sector to all sectors. The time be-tween these additional cycles must be less than 50 μs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to

20514C-6

Am29LV40014

ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 μs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the ris-ing edge of the final WE# pulse in the command se-quence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the op-eration. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the sta-tus of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to “Write Operation Status” for informa-tion on these status bits.)

Figure 3 illustrates the algorithm for the erase opera-tion. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to Figure 17 for timing diagrams.

Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to in-terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 μs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo-rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Ad-dresses are “don’t-cares” when writing the Erase Sus-pend command.

When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 μs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter-minates the time-out period and suspends the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sec-tors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.

After an erase-suspended program operation is com-plete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence”for more information.

The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the de-

15Am29LV400

Notes:

1.See Table 5 for erase command sequence.

2.See “DQ3: Sector Erase Timer” for more information.

Figure 3.Erase Operation

Am29LV40016

17Am29LV400

Table 5.

Am29LV400 Command Definitions

Legend:X = Don’t care

RA = Address of the memory location to be read. RD = Data read from location RA during read operation.PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17–A12 uniquely select any sector.

Notes:

1.See Table 1 for description of bus operations.

2.All values are in hexadecimal.

3.Except when reading array or autoselect data, all bus cycles

are write operations.4.Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.5.Address bits A17–A11 are don’t cares for unlock and

command cycles, except when SA or PA required.6.No unlock or command cycles required when reading array

data.7.The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).

8.The fourth cycle of the autoselect command sequence is a

read cycle.9.The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” for more information.10.The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.11.The Erase Resume command is valid only during the Erase

Suspend mode.

Command Sequence (Note 1)

Bus Cycles (Notes 2–5)

First Second Third Fourth Fifth Sixth Addr Data

Addr

Data

Addr

Data Addr

Data

Addr Data

Addr

Data

Read (Note 6)1RA RD Reset (Note 7)

1XXX F0Manufacturer ID

Word 4555AA 2AA 5555590X0001Byte AAA 555AAA Device ID,

Top Boot Block Word 4555AA 2AA 5555590X01

22B9Byte AAA 555AAA X02

B9Device ID,

Bottom Boot Block Word 4

555AA

2AA 55

55590

X01

22BA Byte AAA 555AAA X02

BA Sector Protect Verify (Note 9)

Word

4

555

AA

2AA

55

555

90(SA)X02XX00XX01Byte AAA 555AAA (SA)X040001Program Word 4555AA 2AA 55555A0PA PD Byte AAA 555AAA Chip Erase Word 6555AA 2AA 5555580555AA 2AA 5555510Byte AAA 555AAA AAA 555AAA Sector Erase

Word 6555AA 2AA 5555580

555AA

2AA 55

SA

30

Byte

AAA 555

AAA

AAA

555

Erase Suspend (Note 10)1XXX B0Erase Resume (Note 11)

1

XXX

30

C y c l e s

A u t o s e l e c t (N o t e 8)

WRITE OPERATION STATUS

The device provides several bits to determine the sta-tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsections de-scribe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-tem whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command se-quence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum pro-grammed to DQ7. This DQ7 status also applies to pro-gramming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for ap-proximately 1 μs, then the device returns to reading array data.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase al-gorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status in-formation on DQ7.

After an erase command sequence is written, if all sec-tors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 μs, then the de-vice returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the se-lected sectors that are protected.

When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figure 18, Data# Polling Timings (During Embedded Algorithms), in the “AC Characteristics” section illustrates this.Table 6 shows the outputs for Data# Polling on DQ7. Figure 4 shows the Data# Polling algorithm.

Notes:

1.VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2.DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

20514C-8 Figure 4.Data# Polling Algorithm

Am29LV40018

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev-eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC.

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. Figures 13, 16 and 17 shows RY/BY# for reset, program, and erase operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase op-eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-eration, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is com-plete, DQ6 stops toggling.

After an erase command sequence is written, if all sec-tors selected for erasing are protected, DQ6 toggles for approximately 100 μs, then returns to reading array data. If not all selected sectors are protected, the Em-bedded Erase algorithm erases the unprotected sec-tors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to deter-mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately 2 μs after the program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro-gram algorithm is complete.Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-ure 5 shows the toggle bit algorithm. Figure 19 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also the subsec-tion on DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for eras-ure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6.

Figure 5 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When-ever the system initially begins reading toggle bit sta-tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has com-pleted the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cy-cle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys-tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.

19Am29LV400

be less than 50 μs, the system need not monitor DQ3. See also the “Sector Erase Command Sequence” sec-tion.

After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Poll-ing) or DQ6 (Toggle Bit I) to ensure the device has ac-cepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has be-gun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been ac-cepted. Table 6 shows the outputs for DQ3.Notes:

1.Read toggle bit twice to determine whether or not it is

toggling. See text.

2.Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

20514C-9 Figure 5.Toggle Bit Algorithm

Am29LV40020

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