当前位置：文档库 › UC3842中文使用

UC3842中文使用

应用笔记

U-100A

APPLICATION NOTE

UC3842/3/4/5 PROVIDES LOW-COST

CURRENT-MODE CONTROL

INTRODUCTION

CURRENT-MODE CONTROL

The fundamental challenge of power supply design is to simultaneously realize two conflicting objectives: good electrical performance and low cost. The is an integrated pulse width modulator designed with both these objectives in mind. This provides de-signers an inexpensive controller with which they can ob-tain all the performance advantages of current mode op-eration. In addition, the UC3842 series is optimized for ef-ficient power sequencing of off-line converters, DC to DC regulators and for driving power MOSFETs or transistors.

This application note provides a functional description of the UC3842 family and highlights the features of each in-dividual member, the UC3842, UC3843, UC3844 and UC3845 Throughout the text, the UC3842 part number will be referenced, however the generalized circuits and performance characteristics apply to each member of the UC3842 series unless otherwise noted. A review of cur-rent mode control and its benefits is included and meth-ods of avoiding common pitfalls are mentioned. The final section presents designs of power supplies utilizing UC3842 control.

Figure 1 shows the two-loop current-mode control system in a typical buck regulator application. A clock signal initi-ates power pulses at a fixed frequency. The termination of each pulse occurs when an analog of the inductor current reaches a threshold established by the error signal. In this

way the error signal actually controls peak inductor cur-rent. This contrasts with conventional schemes in which the error signal directly controls pulse width without regard to inductor current.

Several performance advantages result from the use of current-mode control. First, an input voltage feed-forward characteristic is achieved; i.e., the control circuit instanta-neously corrects for input voltage variations without using up any of the error amplifier’s dynamic range. Therefore,line regulation is excellent and the error amplifier can be dedicated to correcting for load variations exclusively.For converters in which inductor current is continuous,controlling peak current is nearly equivalent to controlling average current. Therefore, when such converters employ current-mode control, the inductor can be treated as an

Figure 1. Two-Loop Current-Mode Control System

UC3842/3/4/5提供了低成本的电流模式控制

引言

电源设计的主要难题是需要同时实现两个相互矛盾的目标，即：上佳的电性能和低成本。UC3842/3/4/5是一款集成脉宽

调制器 (PWM)，它在设计时兼顾了上述的两个目标。该IC

为设计师提供了一款廉价的控制器，他们借助该控制器能够获得电流模式操作的所有性能优势。此外，UC3842系列还专为隔离式转换器和DC-DC 稳压器的高效电源排序以及功率MOSFET 或晶体管的驱动进行了优化。

本应用笔记提供了UC3842系列的功能描述，并突出介绍了其每个成员 (UC3842、UC3843、UC3844和UC3845) 的特点。文章通篇以型号为UC3842的器件为参考，不过，除非特别注明，否则一般化的电路和性能特征将适用于UC3842系列的所有成员。本文评述了电流模式控制及其好处，并提及了避免常见易犯错误的方法。最后的章节给出了运用UC3842控制器的电源设计方案。电流模式控制

图1示出了双环路电流模式控制系统在典型降压型稳压器中的应用。时钟信号以一个固定频率来启动电源脉冲。当电感器电流的模拟量达到由误差信号所确定的门限时，脉冲将被终止。误差信号以这种方式实际上起到了控制峰值电感器电流的作用。这与传统方案截然不同，后者是由误差信号直接控制脉冲宽度，而不考虑电感器电流。通过使用电流模式控制获得了的一些性能优势。首先，实现了一种输入电压前馈特性；即：控制电路能够即刻校正输入电压偏差，而不会耗尽任何误差放大器的动态范围。因此，线路输入电压调节性能非常出色，而且误差放大器可被指定专门用于校正负载偏差。

对于那些具有连续电感器电流的转换器而言，控制峰值电流式控制时，可将电感器视作一个误差电压控制型电流源，以

便进行小信号分析。（接下页）member, the UC3842, UC3843, UC3844 and 图1：双环路电流模式控制系统

应用笔记

U-100A

-100A

APPLICATION NOTE

U-100A

error-voltage-controlled-current-source for the purposes of small-signal analysis. This is illustrated by Figure 2. The

two-pole control-to-output frequency response of these converters is reduced to a single-pole (filter capacitor in parallel with load) response. One result is that the error amplifier compensation can be designed to yield a stable closed-loop converter response with greater gainband-width than would be possible with pulse-width control, giv-ing the supply improved small-signal dynamic response to changing loads. A second result is that the error amplifier compensation circuit becomes simpler, as illustrated in Fig-ure 3. Capacitor and resistor in Figure 3a add a low frequency zero which cancels one of the two control-to-.output poles of non-current-mode converters. For large-signal load changes, in which converter response is limit-ed by inductor slew rate, the error amplifier will saturate while the inductor is catching up with the load. During this time, will charge to an abnormal level. When the induc-tor current reaches its required level, the voltage on causes a corresponding error in supply output voltage.

The recovery time is which may be quite long. How-ever, the compensation network of Figure can be used where current-mode control has eliminated the inductor pole. Large-signal dynamic response is then greatly im-proved due to the absence of

Current limiting is greatly simplified with current-mode con-trol. Pulse-by-pulse limiting is, of course, inherent in the control scheme. Furthermore, an upper limit on the peak current can be established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while ensur-ing reliable supply operation.

Finally, current-mode controlled power stages can be op-erated in parallel with equal current sharing. This opens the possibility of a modular approach to power supply de-sign.

Figure 2. Inductor Looks Like a Current Source to Small Signals

A) Direct Duty Cycle Control B) Current Mode Control Figure 3. Required Error Amplifier Compensation for Continuous Inductor Current Designs （接上页）这一点示于图2。这些转换器的双极点控制－输出频率响应被简化为一个单极点（滤波电容器与负载并联）响应。一个结果是：可以通过设计使误差放大器补偿产生稳定的闭环转换器响应和较大的增益带宽（相比于采用脉宽控制时），从而改善了电源对于变化中的负载的小信号动态响应。第二个结果是误差放大器补偿电路变得简单了，如图3所示。图3a 中的电容器C i 和电阻器Riz 增添了一个低频零点，该零点信号负载变化（这里，转换器响应受限于电感器转换速率），当电感器的阻抗逐步赶上负载时，误差放大器将发生饱和。在这段时间里，C i 将充电至一个异常的水平。当电感器电流达到其所需的水平时，C i 上的电压将在电源输出电压中引起一个对应的误差。恢复时间为R iz C i ，该时间有可能相当长。然而，在电流模式控制已经消除了电感器极点的场合中，可以采用图3b 中的补偿网络。由于不存在C i

，因此大信号动态响应得到了极

大的改善。

电流模式控制的运用大大地简化了电流限制。在该控制方案中，逐个脉冲电流限制当然是固有的特征。而且，通过简单地对误差电压进行箝位，即可确定峰值电流的上限。准确的电流限制可实现磁性元件和功率半导体元件的优化，并确保可靠的电源操作。

最后，电流模式控制功率级可以与均流电路并联运作。这为实现模块化的电源设计方法提供了可能性。

图2：电感器看起来像是一个至小信号的电流源A) 直接占空比控制B) 电流模式控制

图3：连续电感器电流设计所需的误差放大器补偿

应用笔记

U-100A

APPLICATION NOTE

U-100A

THE UC3842/3/4/5 SERIES OF CURRENT-MODE PWM IC’S

DESCRIPTION

FEATURES

The UC1842/3/4/5 family of control ICs provides the nec-essary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal

external parts count. Internally implemented circuits in-clude under-voltage lockout featuring start up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control,and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving ei-

ther N Channel MOSFETs or bipolar transistor switches, is low in the off state.

Differences between members of this family are the un-der-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applica-tions. The corresponding thresholds for the UC1843 and UC1845 are 8.5V and 7.9V. The UC1842 and UC1843 can

operate to duty cycles approaching 100%. A range of zero to <50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flip which blanks the output off every other clock cycle.

IC SELECTION GUIDE Optimized for Off-Line and DC to DC Converters

Low Start Up Current (< 1 mA)

Automatic Feed Forward Compensation Pulse-By-Pulse Current Limiting Enhanced Load Response Characteristics Under-Voltage Lockout with Hysteresis

Double Pulse Suppression High Current Totem Pole Output

Internally Trimmed Bandgap Reference 500 kHz Operation Low Error Amp RECOMMENDED USAGE

Note: 1. A= DIL-8 Pin Number. B = SO-16 Pin Number.

2. Toggle flip flop used only in 1844A and 1845A.

Figure 4UC3842/3/4/5系列电流模式PWM IC 描述

UC1842/3/4/5

系列控制IC 提供了利用极少的外部元件来实现隔离式或DC/DC 固定频率电流模式控制方案所必需的特点。在内部实现的电路包括启动电流小于1mA 的欠压闭锁电路、一个精准的基准（经过修整以在误差放大器输入端上提供高准确度）、用于确保闭锁操作的逻辑电路、一个另外还提供了电流限值控制功能的PWM 比较器、以及一个专为供应或吸收高峰值电流而设计的图腾柱输出级。这个适合于驱动N 沟道MOSFET

或双极晶体管开关的输出级在关断状态中为低电平。该系列各成员之间的差异在于欠压闭锁门限和最大占空比范围。UC1842和UC1844具有16V （接通）和10V （关断）的UVLO

门限，非常适合于隔离式应用。UC1843和UC1845的对应门限为8.5V 和7.9V 。UC1842和UC1843能够在占空比接近100%的条件下运作。通过增设一个内部电平转换触发器（它每隔一个时钟周期将输出关闭），UC1844和UC1845获得了0%至＜50%的占空比范围。特点专为隔离式和DC-DC 转换器而优化低启动电流 (＜1mA)自动前馈补偿逐个脉冲电流限制

增强的负载响应特性

具迟滞的欠压闭锁

双脉冲抑制高电流图腾柱输出

在内部修整的带隙基准500kHz 工作频率低RO 误差放大器

???????????IC

选择指南推荐的用法图4

应用笔记

U-100A

-100A

APPLICATION NOTE

U-100A is adequate to make fully operational before enabling the output stage. Figure that the turn-off thresholds internally oscillations shows supply than 1 cient bootstrapping from the rectified input of an off-line and must be charged to 16V through With a start-up current of 1 can be as large as 100 and still charge GIN when =90V RMS (low line). Power dissipation in would then be less than 350 mW even under high line = 130V During UVLO; the output driver is in a low state. While it doesn’t exhibit the same saturation characteristics as nor-Figure 6. During Under-Voltage Lockout, the output

driver is biased to sink minor amounts of

current.

OSCILLATOR The UC3842 oscillator is programmed as shown in Figure

8. Timing capacitor CT is charged from (5V) through

by an selecting and oscillator combinations versus oscillator frequency. The timing resistor can be cal- The UC3844 UC3845 have an internal flip-flop oscillator for a 50% kHz.

Figure 7. Providing Power to the

0019-8

图6：在欠压闭锁期间，对输出驱动器施加了偏压，以吸收较少量的电流。UVLO 电路用于确保V 足以在启用输出级之前使全面运作。如图5所示，接通和关断门限分别在内部固迟滞用于防止在电源排序期间发生示出了电源电流要求。由于能够从一个隔离式转换器的整流输入实现高效的自举，因此启动电流小于产生。然而，在启动时，充电至16V 。由于启动电流为1mA 的阻值最大可至100k Ω，而AC = 90VRMS （低线路输入电压）时仍然对进行充RIN 中的功耗于是将小于350mW ，即使在高线路输入电压(V AC = 130VRMS) 条件下也不例外。

在UVLO 期间；输出驱动器处于低电平状态。尽管它所呈现的饱和特性与正常操作时有所不同，但它仍然能够很容易地吸收1mA

的电流，这足以确保振荡器

UC3842振荡器的设置如图8所示。定时电容器CT 通过定时电RT V (5V) 来充电，并由一个内部电流源进行放电。在选择振荡器元件的过程中，第一步是确定所需的电路死区时T R T /C 组合与振荡器频率的关系曲线。定时电阻器的阻值可以由下式来计算。UC3844

具有一个由振荡器来驱动的内部二分频触发器，以提供一个50%的最大占空比。因此，必须将其振荡器的运行频率设定为期望的电源开关频率的两倍。APPLICATION NOTE U-100A that the turn-off thresholds internally spectively. The 6V hysteresis prevents during power sequencing. Figure 6 than 1 cient bootstrapping from the rectified input of an off-line converter, as illustrated by Figure 6. During normal circuit auxiliary winding to 16V With a start-up current of 1 can be as large as 100 and still charge GIN when =90V RMS (low line). Power dissipation in would then be less than 350 mW even under high line = 130V RMS) conditions.During UVLO; the output driver is in a low state. While it doesn’t exhibit the same saturation characteristics as nor-mal operation, it can easily sink 1 milliamp, enough to in-sure the MOSFET is held off.Figure 6. During Under-Voltage Lockout, the output

driver is biased to sink minor amounts of

current.OSCILLATOR The UC3842 oscillator is programmed as shown in Figure 8. Timing capacitor CT is charged from (5V) through the timing resistor and discharged by an internal cur-rent source.selecting oscillator components required deadtime. Once Figure 9 is used to pinpoint the nearest standard value of combinations versus oscillator frequency. The timing resistor can be cal-The UC3844 UC3845 have an internal flip-flop oscillator for a 50% cycle. Therefore, their oscillators must be set to run at twice power supply switching Figure 7. Providing Power to the

0019-8

图7：给UC3842/3/4/5供电

Rin.max=(Vin.min-16)/而言，此处的启动电流取定时电阻与定时电容选择时，可考虑相关的占空比限制

应用笔记

U-100A

APPLICATION NOTE

MAXIMUM DUTY CYCLE The UC3842 and UC3843 have a maximum duty cycle of approximately 100%, whereas the UC3844 and UC3845are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most fly-

back and forward converters. For optimum IC perform-ance the deadtime

should not exceed 15% of the oscilla-tor clock period.

During the discharge, or “dead” time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle to: = 1 - U C 3842/3 = 1 - / 2 X UC3844/5where T PERIOD = 1 / F oscillator

0019-9

Figure

8Deadtime vs > 5k)

Figure 9Timing Resistance vs Frequency

0019-10

FREOUENCY - (Hz)

0019-11

Figure 10

U-100A

CURRENT SENSING AND

LIMITING The UC3842 current sense input is configured as shown in Figure 12. Current-to-voltage conversion is done exter-nally with ground-referenced resistor Under normal operation the peak voltage across is controlled by the E/A according to the following relation:

where = control voltage = E/A output voltage.

can be connected to the power circuit directly or through a current transformer, as Figure 11 illustrates.While a direct connection is simpler, a transformer can re-duce power dissipation in reduce errors caused by the base current, and provide level shifting to eliminate the re-straint of ground-referenced sensing. The relation be-tween and peak current in the power stage is given by:

where: N = current sense transformer turns ratio

= 1 when transformer not used.For purposes of small-signal analysis, the control-to-sensed-current gain is:

When sensing current in series with the power transistor,as shown in Figure 11, the current waveform will often have a large spike at its leading edge. This is due to recti-fier recovery and/or inter-winding capacitance in the pow-er transformer. If unattenuated, this transient can prema-turely terminate the output pulse. As shown, a simple RC filter is usually adequate to suppress this spike. The RC time constant should be approximately equal to the cur-rent spike duration (usually a few hundred nanoseconds).The inverting input to the UC3842 current-sense compara-tor is internally clamped to 1V (Figure 12). Current limiting occurs if the voltage at pin 3 reaches this threshold value,i.e., the current limit is defined by:

0019-13

Figure 11. Transformer-Coupled Current Sensing

最大占空比

UC3842和UC3843具有约100%的最大占空比，而UC3844和UC3845

的最大占空比则被一个内部电平转换触发器箝位于50%

。在大多数反激式和正激式转换器中，这种占空比箝位是有好处的。为了获得最佳的IC 性能，死区时间不应超过振荡器时钟周期的15%。在放电期间（或“死区”时间）里，内部时钟信号将输出锁至低电平状态。这将最大占空比DMAX 限制为：D MAX = 1 – (t

DEAD / t PERIOD ) UC3842/3D MAX = 1 – (t DEAD / 2 x t PERIOD ) UC3844/5式中的t DEAD = 1 / F 振荡器

死区时间与CT 的关系曲线 (RT ＞5k)图8定时电阻与频率的关系曲线图9图10电流检测和限制UC3842电流检测输入的配置如图12所示。电流－电压转换利用接地参考电阻器R S 在外部完成。在正常工作条件下，RS 两端的峰值电压受控于E/A （误差放大器），依据的公式如下：

(V C – 1.4V)

(3 R S )

式中，V C = 控制电压 = E/A 输出电压。如图11所示，RS 可直接（或通过一个电流变压器）连接至电源电路。虽然直接连接的做法比较简单，但采用变压器能够降低RS 中的功耗、减少由基极电流引起的误差、并提供电平移位以消除接地参考检测的限制。VC 与功率级中的峰值电流之间的关系由下式给出：

V R S(pk) N

RS 3R S

式中：N = 电流检测变压器匝数比 = 1

（当未使用变压器时）。为了便于小信号分析，控制－检测电流增益为： i (pk) N

V C 3 R S

如图11所示，当检测与功率晶体管串联的电流时，电流波形在其前沿处常常将出现一个很大的尖峰。这是由于整流器恢复和/或电源变压器中的绕组间电容所造成的。如果不对其进行衰减，那么该瞬变会过早地终止输出脉冲。如图所示，采用一个简单的RC 滤波器往往足以抑制该尖峰。RC 时间常数应大致等于电流尖峰持续时间（通常为几百ns ）。UC3842电流检测比较器的反相输入在内部箝位于1V （图12）。如果引脚3上的电压达到其门限值，则电流限制电路开始起作用，也就是说：电流限值由下式决定： N x 1V

I P =

i (pk) = N ( V C – 1.4V )()

= i max =

APPLICATION NOTE MAXIMUM DUTY CYCLE

The UC3842 and UC3843 have a maximum duty cycle of approximately 100%, whereas the UC3844 and UC3845are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most fly-back and forward converters. For optimum IC perform-ance the deadtime should not exceed 15% of the oscilla-tor clock period.During the discharge, or “dead” time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle to: = 1 - U C 3842/3 = 1 - / 2 X UC3844/5where T PERIOD = 1 / F oscillator 0019-9

Figure 8

Deadtime vs > 5k)

Figure 9

Timing Resistance vs Frequency 0019-10

FREOUENCY - (Hz)0019-11Figure 10U-100A

CURRENT SENSING AND LIMITING

The UC3842 current sense input is configured as shown in Figure 12. Current-to-voltage conversion is done exter-

nally with ground-referenced resistor Under normal

operation the peak voltage across is controlled by the E/A according to the following relation:where

= control voltage = E/A output voltage.

= 1 when transformer not used.For purposes of small-signal analysis, the control-to-sensed-current gain is:

When sensing current in series with the power transistor,as shown in Figure 11, the current waveform will often

have a large spike at its leading edge. This is due to recti-fier recovery and/or inter-winding capacitance in the pow-er transformer. If unattenuated, this transient can prema-turely terminate the output pulse. As shown, a simple RC filter is usually adequate to suppress this spike. The RC time constant should be approximately equal to the cur-rent spike duration (usually a few hundred nanoseconds).The inverting input to the UC3842 current-sense compara-tor is internally clamped to 1V (Figure 12). Current limiting occurs if the voltage at pin 3 reaches this threshold value,i.e., the current limit is defined by:

0019-13

Figure 11. Transformer-Coupled Current Sensing

应用笔记

U-100A

-100A

APPLICATION NOTE U-100A

Figure 12. Current Sensing AMPLIFIER amplifier (E/A) configuration is shown in Figure

13. The non-inverting input is not brought out to a pin, but sen so that this pole cancels the zero of the output filter capacitor ESR in the power circuit. and fix the low-frequency gain. They are chosen to provide as much gain as possible while still allowing the pole formed by the out-put filter capacitor and load to roll off the loop gain to uni-converter stability while providing good dynamic response.Figure 14. Compensation The E/A output will source 0.5 mA amd sink 2 mA. A low-er limit for is given by:0019-14

Figure 13. E/A Configuration

图12：电流检测

(E/A) 配置示于图13。同相输入未被引出至一个引）。选择合适的R F 、C ，以使该极点抵消电源电路中输出滤波电容器ESR 的零点。R 固定了低频增益。它们的选择依据是：提供尽可能大的增益，同时仍然允许由输出滤波电容器和负载形成的极点在f ≈SWITCHING 。这种方法确保了转换器稳定0.5mA

电流并吸收2mA

图13：E/A 配置图14：补偿此处计算出了Rf 的下限

值，在根据误差放大器补偿电路所提供的极点0.25倍的开关频率，即可获得Cf 的值。

分压网络设计乘积为定值。

参数设计可参考输出滤E|A 输出端给源极电流，漏极2mA

应用笔记

U-100A

APPLICATION

E/A input bias curret (2

It is therefore desirable to keep the value of

as low as

possible.

Figure 15 shows the open-loop frequency response of the UC3842 E/A. The gain represents an upper limit on the

gain of the compensated E/A. Phase lag increases rapidly as frequency exceeds 1 MHz due

to second-order poles at ~ 10 MHz and above.Continuous-inductor-current boost and flyback converters each have a right-half-plane zero in their transfer function.An additional compensation pole is needed to roll off loop gain at a frequency less than that of the RHP zero. and in the circuit of Figure 16 provide this pole.TOTEM-POLE OUTPUT

The UC3842 PWM has a single totem-pole output which can be operated to ± 1 amp peak for driving MOSFET

gates, and a + 200 mA average current for bipolar power U-100A

transistors. Cross conduction between the output transis-tors is minimal, the average added power with = 30V is only 80 mW at 200 kHz.

Limiting the peak current through the IC is accomplished by placing a resistor between the totem-pole output and the gate of the MOSFET. The value is determined by di-viding the totem-pole collector voltage by the peak

current rating of the IC’s totem-pole. Without this resistor,the peak current is limited only by the dV/dT rate of the totem-pole switching and the FET gate capacitance.

The use of a Schottky diode from the PWM output to ground will prevent the output voltage from going exces-sively below ground, causing instabilities within the IC. To be effective, the diode selected should have a forward drop of less than 0.3V at 200 mA. Most l- to 3-amp Schottky diodes exhibit these traits above room tempera-ture. Placing the diode as physically close to the PWM as possible will enhance circuit performance. Implementation of the complete drive scheme is shown in the following di-agrams. Transformer driven circuits also require the use of the Schottky diodes to prevent a similar set of circum-0019-16

0019-17

Figure 16. E/A Compensation Circuit for Continuous Boost and Flyback Topologies E/A

中产生了一个DC 误差，由下式给出：ΔV O(MAX) = (2μA) R I ，因此，使RI 的阻值尽可能低是合乎需要的。

图15示出了UC3842 E/A 的开环频率响应。增益代表了补偿E/A 的增益的上限。由于二阶极点位于约

10MHz 及更高的频率，因此当频率超过1MHz 时，相位滞后将快速增加。

连续电感器电流升压和反激式转换器在其转移函数中均具有一个右半平面零点。需要一个额外的补偿极点，以在一个低于RHP 零点频率的频率条件下衰减环路增益。图16所示电路

中的R P 和C P 提供了该极点。

图腾柱输出

UC3842 PWM

具有单个可在至±1A （峰值）的电流条件下运作的图腾柱输出（用于驱动MOSFET 栅极）和+200mA 的平均电流（用于驱动双极功率二极管）。输出晶体管之间的交叉传导极小，V IN = 30V 时的平均附加功率仅为80mW （在200kHz

）。对流过IC 的峰值电流的限制是通过在图腾柱输出和MOSFET 的栅极之间布设一个电阻器来完成的。电流限值由“图腾柱集电极电压V C ÷IC 图腾柱的额定峰值电流”来确定。未采用该电阻器时，峰值电流仅受限于图腾柱开关操作的

dV/dT 速率和

FET 栅极电容。通过在PWM 输出和地之间采用一个肖特基二极管，将防止输出电压变至过分低于地电位的电平而在IC 内部导致不稳定。为了发挥效用，所选择的二极管在200mA 的电流条件下应具有小于0.3V 的正向压降。大多数1～3A 肖特基二极管在高于室温的PWM 的地方将增强电路性能。完整驱动电路的可实现方案见下面的示意图。由变压器驱动的电路也需要使用肖特基二极管，以防止在PWM 输出端上出现相似的情形。（接下页）

图16：针对连续升压和反激式拓扑结构的E/A 补偿电路

应用笔记U-100A

-100A stances from occurring on the PWM output. The ringing

below ground is greatly enhanced by the transformer leak-

age inductance and parasitic capacitance, in addition to

the magnetizing inductance and FET gate capacitance.

Circuit implementation is similar to the previous example.

Figures 18, 19 and 20 show suggested circuits for driving

MOSFETs and bipolar transistors with the UC3842 output.

The simple circuit of Figure 18 can be used when the

control IC is not electrically isolated from the MOSFET

turn-on and turn-off to ± 1 amp. It also provides damping

for a parasitic tank circuit formed by the FET input capaci-

tance and series wiring inductance. Schottky diode D1

prevents the output of the IC from going far below ground

during turn-off.

OUTPUT CURRENT SOURCE OR SINK - (A)

0019-18

Figure 17. Output Saturation Characteristics

20 TO 30V

Figure 19. Isolated MOSFET Drive

Figure 19 shows an isolated MOSFET drive circuit which

is appropriate when the drive signal must be level shifted

or transmitted across an isolation boundary. Bipolar tran-

sistors can be driven efficiently with the circuit of Figure

20. and

fix the on-state base

while capacitor provides a negative base current pulse

to remove stored charge at turn-off.

Since the UC3842 series has only a single output, an in-

terface circuit is needed to control push-pull half or full

bridge topologies. The UC3706 dual output driver with in-

ternal toggle flip-flop performs this function. A circuit ex-

ample at the end of this paper illustrates a typical applica-

tion for these two ICs. Increased drive capability for driv-

ing numerous FETs in parallel, or other loads can be ac-

complished using one of the UC3705/6/7 driver ICs.

10 TO 20V

Figure 18. Direct MOSFET Drive

12 TO 20V

（接上页）除了磁化电感和FET栅极电容之外，变压器漏电感

和寄生电容也极大地增强了低于地电位的振铃。电路实现方案

与前一个例子很相似。

图18、19和20示出了适合于采用UC3842输出来驱动MOSFET

和双极晶体管的推荐电路。当控制IC与MOSFET接通和关断电

隔离未达到±1A时，可以采用图18中的简单电路。它还为一

个由FET输入电容和串联导线电感组成的寄生谐振电路提供了

阻尼。肖特基二极管D1用于防止IC的输出在关断期间变至远

远低于地电位的电平。

图19示出了一款隔离式MOSFET驱动电路，当驱动信号必须进

行电平移位或穿越一个隔离边界进行传输时，很适合采用该电

路。利用图20所示的电路可以高效地驱动双极晶体管。电阻器

R1和R2C1

极电流脉冲，以在关断时清除累积电荷。

由于UC3842系列只具有单个输出，因此需要一个接口电路来

控制推挽半桥式或全桥式拓扑结构。具有内部电平转换触发器

的UC3706双路输出驱动器负责执行此项功能。本文末尾所举

的电路实例示出了这两款IC的一种典型应用。采用UC3705/6/7

驱动器IC当中的一款，就能够实现更强的驱动能力，以驱动多

个并联的FET或其他负载。

图17：输出饱和特性

图18：直接MOSFET驱动图19：隔离式MOSFET驱动

APPLICATION NOTE U-100A

stances from occurring on the PWM output. The ringing

below ground is greatly enhanced by the transformer leak-

age inductance and parasitic capacitance, in addition to

the magnetizing inductance and FET gate capacitance.

Circuit implementation is similar to the previous example.

Figures 18, 19 and 20 show suggested circuits for driving

MOSFETs and bipolar transistors with the UC3842 output.

The simple circuit of Figure 18 can be used when the

control IC is not electrically isolated from the MOSFET

turn-on and turn-off to ± 1 amp. It also provides damping

for a parasitic tank circuit formed by the FET input capaci-

tance and series wiring inductance. Schottky diode D1

prevents the output of the IC from going far below ground

during turn-off.

OUTPUT CURRENT SOURCE OR SINK - (A)

0019-18

Figure 17. Output Saturation Characteristics

20 TO 30V

Figure 19. Isolated MOSFET Drive

Figure 19 shows an isolated MOSFET drive circuit which

is appropriate when the drive signal must be level shifted

or transmitted across an isolation boundary. Bipolar tran-

sistors can be driven efficiently with the circuit of Figure

20. Resistors and fix the on-state base current

while capacitor provides a negative base current pulse

to remove stored charge at turn-off.

Since the UC3842 series has only a single output, an in-

terface circuit is needed to control push-pull half or full

bridge topologies. The UC3706 dual output driver with in-

ternal toggle flip-flop performs this function. A circuit ex-

ample at the end of this paper illustrates a typical applica-

tion for these two ICs. Increased drive capability for driv-

ing numerous FETs in parallel, or other loads can be ac-

complished using one of the UC3705/6/7 driver ICs.

10 TO 20V

Figure 18. Direct MOSFET Drive

12 TO 20V

应用笔记

U-100A

APPLICATION NOTE U-100A

NOISE

As mentioned earlier, noise on the current sense or con-

trol signals can cause significant pulse-width jitter, particu-

larly with continuous-inductor-current designs. While slope compensation helps alleviate this problem, a better solu-tion is to minimize the amount of noise. In general, noise immunity improves as impedances decrease at critical points in a circuit.One such point for a switching supply is the ground line.Small wiring inductances between various ground points on a PC board can support common-mode noise with suf-ficient amplitude to interfere with correct operation of the modulating IC. A copper ground plane and separate return lines for high-current paths greatly reduce common-mode noise. Note that the UC3842 has a single ground pin.High sink currents in the output therefore cannot be re-

turned separately.SYNCHRONIZATION

Ceramic monolythic bypass capacitors

(0.1 from and to ground will provide low-impedance paths for high frequency transients at those points. The input to the error amplifier, however, is a high-impedance point which

cannot be bypassed without affecting the dynamic re-sponse of the power supply. Therefore, care should be taken to lay out the board in such a way that the feed-back path is far removed from noise generating compo-nents such as the power transistor(s).

Figure 21 illustrates another common noise-induced prob-lem. When the power transistor turns off, a noise spike is coupled to the oscillator terminal. At high duty cy-cles the voltage at is approaching its threshold lev-el (~ 2.7V, established by the internal oscillator circuit)when this spike occurs. A spike of sufficient amplitude will prematurely trip the oscillator as shown by the dashed lines. In order to minimize the noise spike, choose as large as possible, remembering that deadtime increases with It is recommended that never be less than ~ 1000 Often the noise which causes this problem is caused by the output (pin 6) being pulled below ground at turn-off by external parasitics. This is particularly true

when driving MOSFETs. A Schottky diode clamp from ground to pin 6 will prevent such output noise from feed-ing to the oscillator. If these measures fail to correct the probelm, the oscillator frequency can always be stabilized

with an external clock. Using the circuit of Figure 31 re-sults in an waveform like that of Figure 21B. Here the oscillator is much more immune to noise because the ramp voltage never closely approaches the internal threshold.The simplest method to force synchronization utilizes the timing capacitor in near standard configuration. Rath-er than bring to ground directly, a small resistor is placed in series with to ground. This resistor serves as the input for the sync pulse which raises the voltage above the oscillator’s internal upper threshold. The PWM is allowed to run at the frequency set by and until

the sync pulse appears. This scheme offers several ad-vantages including having the local ramp available for slope compensation.The UC3842/3/4/5 oscillator

Figure 22. Sync Circuit Implementation

0019-32

Figure 21. (a.) Noise on Pin 4 can cause oscillator to pre-trigger.(b.) With external sync., noise does not approach threshold level.

噪声如前文所述，电流检测或控制信号上的噪声会引起显著的脉宽

抖动，对于连续电感器电流设计而言尤其如此。尽管斜率补偿有助于缓解这一问题，但更好的解决方案是最大限度地减少噪声量。一般来说，当阻抗在电路的关键点上减小时，抗噪声能力将有所改善。

对于开关电源面言，接地线就是这样的一个点。PC 板上各种不同接地点之间的小配线电感会助长具足够幅度的共模噪声对调制IC 正确运作的干扰。铜接地平面和用于大电流通路的单独回线可极大地降低共模噪声。请注意，UC3842具有单个接地引脚。因此，输出中的高吸收电流不能单独地返回。

连接在V CC 和V REF 与地之间的单片陶瓷旁路电容器 (0.1μF) 将

为这些点上的高频瞬变提供低阻抗通路。然而，误差放大器的输入是一个高阻抗点，无法在不影响电源动态响应的情况下对其进行旁路。因此，应谨慎地进行电路板的布局，使反馈通路远离诸如功率晶体管等噪声发生元件。图21示出了另一种由共模噪声引发的问题。当功率晶体管关断时，一个噪声尖峰被耦合至振荡器的R T /C T 端子。在高占空比条件下，当该尖峰出现时，R T /C T 上的电压将接近其门限电平（约2.7V ，由内部振荡电路确定）。如图中的虚线所示，一个具有足够幅度的尖峰将过早地使振荡器发生跳变。为了最大限度地减小噪声尖峰，应选择尽可能大的C T ，不要忘记：死区时间随着C T 的增大而增加。建议C T 永远不要小于约1000pF 。诱发该问题的噪声常常是由在关断时被外部寄生元件拉至地电位以下的输出（引脚6）所引起的。当驱动MOSFET 时，情况尤其如此。布设在地和引脚6之间的肖特基二极管箝位电路将防止此类输出噪声被馈送至振荡器。如果

这些措施未能纠正该问题，则始终可以利用一个外部时钟来稳定振荡器频率。采用图31中的电路将产生一个类似于图21B 的R T /C T 波形。这里，由于斜坡电压绝对不会非常接近内部门限，因此振荡器的抗噪声能力要强得多。同步

实施同步的最简单方法在接近标准的配置中利用了定时电容器 (C T )。布设了一个与C T 串联的小接地电阻器，而不是将C T 直接引至地。该电阻器充当同步脉冲的输入，负责将C T 电压提升至高于振荡器的内部上门限。允许PWM 以RT 和C T 所设定的频率运行，直到同步脉冲出现为止。这种方案提供了几个优点，包括拥有可用于斜率补偿的局部斜坡 (local ramp)。（接下页）

图21: (a) 引脚4上的噪声会导致振荡器提前触发。

(b) 利用外部同步，噪声不会接近门限电平。

应用笔记

U-100A

-100A

APPLICATION NOTE

U-100A

must be set to a lower frequency than the sync pulse stream, typically 20 percent with a 0.5V pulse applied across the resistor. Further information on synchronization can be found in “Practical Considerations in Current Mode Power Supplies” listed in the reference appendix.The UC3842 can also be synchronized to an external clock source through the terminal (Pin 4) as shown

the upper lower PWM is initiated and turns on. The timing capacitor contin-ues to charge until it reaches the upper threshold of the comparator. old is reached. During this discharge time the PWM output is disabled, thus insuring a “dead” or off time for the out-In instances like this, where no synchronization port is easily available, the timing circuitry can be driven from a digital logic input rather than the conventional analog

mode. The primary considerations of

on-time, dead-time,duty cycle and frequency can be encompassed in the digi-tal pulse train input.A LOW logic level input determines the PWM maximum ON time. Conversely, a HIGH input governs the OFF, or dead time. Critical constraints of frequency, duty cycle or Figure

23Synchronization to an External Clock

0019-34

Figure 24（接上页）必须将UC3842/3/4/5振荡器设定至一个低于同步脉冲流的频率（当在电阻器的两端施加一个0.5V 脉冲时通常要低20%）。如需了解有关同步的更多信息，请查阅列于参考文献附录中的“

Practical Considerations in Current Mode Power Supplies[

电流模式电源中的实际考虑因素]”。在正常操作中，定时电容器被上限和下限）之间。当启动并接通。定时电容器继续充电，直至它达到其内部比较器的上门限为止。一旦相交，则放电电路将立即起动并对进行放电，直至达到下门限为止。PWM 被停用，从而确保了输出的“死区”或关断时间。在诸如此类无法轻松获得同步端口的场合中，可以利用数字逻辑输入（而不是传统的模拟模式）来驱动定时电路。接通时间、死区时间、占空比和频率的主要考虑因素可以被包含在数字脉冲串输入中。

一个低逻辑电平输入负责确定PWM 最大接通时间。反之，一个高逻辑电平输入则用于控制最大关断时间（即死区时间）。频率、占空比或死区时间的关键限制条件可采用任意

方式（从555定时器到精心设计的微处理器控制型软件例程等）来准确地控制。

图23同步至一个外部时钟图24

应用笔记

U-100A

The UC3842/3/4/5 oscillator can be used to generate sync pulses with a minimum of external components. This simple circuit shown in Figure 25 triggers on the falling edge of the waveform, and generates the sync pulse scheme. Triggered by the master’s deadtime, this circuit is useable to several hundred kilohertz with a minimum of delays between the master and slave(s). The photos shown in Figures 26 and 27 depict the circuit waveforms required for the previously mentioned synchronization

of interest.

APPLICATION NOTE SYNC PULSE GENERATOR U-100A

Figure 25. Sync Pulse Generator Circuit

Top Trace:

Circuit Input

Bottom Trace:Circuit Output Across 24 Ohms Vertical: O.5V/CM Both Top Trace:Slave

Bottom Trace:Master

Vertical: 0.5V/CM Both Horizontal:

Horizontal:

001938

001939

Figure 26.0019-38

0019-39

Operating Waveforms at 500 kHz

Figure 27. Master/Slave Sync Waveforms at

同步脉冲发生器

UC3842/3/4/5

振荡器可用于产生同步脉冲，而所需的外部元件极少。这款示于图25的简单电路在C T 波形的下降沿上触发，并产生前文提到的同步电路所需要的同步脉冲。该电路由主控器的死区时间触发，可在至几百kHz 的频率条件下使用，而且主控器和受控器之间的延迟非常之小。图26和图27中的照片描绘了有关的电路波形。

图25：同步脉冲发生器电路图26：500kHz 时的工作波形

图27：CT 上的主控器/受控器同步波形

应用笔记

U-100A

-100A APPLICATION NOTE

U-100A

CHARGE PUMP CIRCUITS

LOW POWER DC/DC CONVERSION

Figure 28Figure 29

Low Power Buck Regulator-Voltage Mode The basic buck regulator is described in the UNITRODE Applications Hand-book.*Consult UNITRODE Power Supply Design Seminar Book for compensa-tion details; see “Closing The Feed-back Loop”, Buck Topology.

Figure

30APPLICATION NOTE U-100A

CHARGE PUMP CIRCUITS

LOW POWER DC/DC CONVERSION

Figure 28

Figure 29Low Power Buck Regulator-Voltage Mode

The basic buck regulator is described in the UNITRODE Applications Hand-book.

*Consult UNITRODE Power Supply Design Seminar Book for compensa-tion details; see “Closing The Feed-back Loop”, Buck Topology.

Figure 30

充电泵电路低功率DC/DC 转换图28

图29低功率降压型稳压器——电压模式

图30

应用笔记

U-100A

APPLICATION NOTE

U-100A CIRCUIT EXAMPLES

1. Off-Line Flyback Figure 31 shows a 25W multiple-output off-line flyback regulator controlled with the UC3844. This regulator is low in cost because it uses only two magnetic elements, a pri-mary-side voltage sensing technique, and an inexpensive control circuit. Specifications are listed below.

Also consult UNITRODE application note U-96 in the ap-plications handbook.

Figure

310019-46

Power Supply Specifications 1. Input Voltage:95 VAC to 130 VAC (50 Hz/60 Hz)2. Line Isolation:3750V 3. Switching Frequency:40 kHz 4. Efficiency @ Full Load:70%5. Output Voltage:A. + 5V, ± 5%: 1A to 4A load Ripple voltage: 50 mV P-P Max.6. +12V, ±3% 0.1A to 0.3A load Ripple voltage: 100 mV P-P Max.C. -12V ±3%, 0.1A to 0.3A load

Ripple voltage: 100 mV P-P Max.

APPLICATION NOTE

U-100A CIRCUIT EXAMPLES

Figure 31

0019-46

Power Supply Specifications

1. Input Voltage:

95 VAC to 130 VAC (50 Hz/60 Hz)2. Line Isolation:3750V 3. Switching Frequency:

40 kHz 4. Efficiency @ Full Load:

70%5. Output Voltage:

A. + 5V, ± 5%: 1A to 4A load Ripple voltage: 50 mV P-P Max.

6. +12V, ±3% 0.1A to 0.3A load Ripple voltage: 100 mV P-P Max.C. -12V ±3%, 0.1A to 0.3A load Ripple voltage: 100 mV P-P Max.电路实例1.隔离反激式图31示出了一款采用UC3844进行控制的25W 多输出隔离反激式稳压器。由于仅采用了两个磁性元件、一种初级侧电压检测方法和一个廉价的控制电路，因此该稳压器的成本很低。其技术规格罗列于下。

另外，还可以参考应用手册中的UNITRODE 应用笔记U-96。电源规格参数1. 输入电压：95VAC 至130VAC (50Hz/60Hz)2. 线路隔离：3750V 3. 开关频率：40kHz 4. 满负载时的效率：70%5. 输出电压A. +5V ，±5%：1A 至4A 负载纹波电压：50mVP-P （最大值）B. +12V ，±3%：0.1A 至0.3A 负载纹波电压：100mVP-P （最大值）C. -12V ，±3%：0.1A 至0.3A 负载纹波电压：100mVP-P （最大值）

图31

重要声明

德州仪器(TI)及其下属子公司有权在不事先通知的情况下，随时对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权随时中止提供任何产品和服务。客户在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。所有产品的销售都遵循在订单确认时所提供的TI销售条款与条件。

TI保证其所销售的硬件产品的性能符合TI标准保修的适用规范。仅在TI保修的范围内，且TI认为有必要时才会使用测试或其它质量控制技术。除非政府做出了硬性规定，否则没有必要对每种产品的所有参数进行测试。

TI对应用帮助或客户产品设计不承担任何义务。客户应对其使用TI组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，客户应提供充分的设计与操作安全措施。

TI不对任何TI专利权、版权、屏蔽作品权或其它与使用了TI产品或服务的组合设备、机器、流程相关的TI知识产权中授予的直接或隐含权限作出任何保证或解释。TI所发布的与第三方产品或服务有关的信息，不能构成从TI获得使用这些产品或服务的许可、授权、或认可。使用此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是TI的专利权或其它知识产权方面的许可。

对于TI的数据手册或数据表，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行复制。在复制信息的过程中对内容的篡改属于非法的、欺诈性商业行为。TI对此类篡改过的文件不承担任何责任。

在转售TI产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去相关TI产品或服务的明示或暗示授权，且这是非法的、欺诈性商业行为。TI对此类虚假陈述不承担任何责任。

可访问以下URL地址以获取有关其它TI产品和应用解决方案的信息：

产品

放大器https://www.wendangku.net/doc/f417473376.html,/amplifiers

数据转换器https://www.wendangku.net/doc/f417473376.html,/dataconverters

DSP https://www.wendangku.net/doc/f417473376.html,/dsp

接口https://www.wendangku.net/doc/f417473376.html,/interface

逻辑https://www.wendangku.net/doc/f417473376.html,/logic

电源管理https://www.wendangku.net/doc/f417473376.html,/power

微控制器https://www.wendangku.net/doc/f417473376.html,/microcontrollers

应用

音频https://www.wendangku.net/doc/f417473376.html,/audio

汽车https://www.wendangku.net/doc/f417473376.html,/automotive

宽带https://www.wendangku.net/doc/f417473376.html,/broadband

数字控制https://www.wendangku.net/doc/f417473376.html,/control

光纤网络https://www.wendangku.net/doc/f417473376.html,/opticalnetwork

安全https://www.wendangku.net/doc/f417473376.html,/security

电话https://www.wendangku.net/doc/f417473376.html,/telecom

视频与成像https://www.wendangku.net/doc/f417473376.html,/video

无线https://www.wendangku.net/doc/f417473376.html,/wireless

邮寄地址：Texas Instruments,Post Office Box655303,Dallas,Texas75265