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EN29LV320AT-70BIP中文资料

FEATURES

? Single power supply operation

- Full voltage range: 2.7 to 3.6 volts read and write operations

? High performance

- Access times as fast as 70 ns

? Low power consumption (typical values at 5 MHz)

- 9 mA typical active read current

- 20 mA typical program/erase current

- Less than 1 μA current in standby or automatic sleep mode.

? Flexible Sector Architecture:

- Eight 8-Kbyte sectors, sixty-three 64k-byte sectors.

- 8-Kbyte sectors for Top or Bottom boot. - Sector/Sector Group protection:

Hardware locking of sectors to prevent

program or erase operations within individual sectors

Additionally, temporary Sector Group

Unprotect allows code changes in previously locked sectors.

? High performance program/erase speed - Word program time: 8μs typical - Sector erase time: 500ms typical - Chip erase time: 70s typical

? JEDEC Standard compatible

? Standard DATA# polling and toggle bits feature

? Unlock Bypass Program command supported ? Erase Suspend / Resume modes:

Read and program another Sector during Erase Suspend Mode

? Support JEDEC Common Flash Interface (CFI). ? Low Vcc write inhibit < 2.5V

? Minimum 100K program/erase endurance cycles.

? RESET# hardware reset pin

- Hardware method to reset the device to read mode. ? WP#/ACC input pin

- Write Protect (WP#) function allows

protection of outermost two boot sectors, regardless of sector protect status - Acceleration (ACC) function provides accelerated program times ? Package Options - 48-pin TSOP (Type 1) - 48 ball 6mm x 8mm FBGA

? Commercial and Industrial Temperature Range.

GENERAL DESCRIPTION

The EN29LV320A is a 32-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 4,194,304 bytes or 2.097,152 words. Any word can be programmed typically in 8μs. The EN29LV320A features 3.0V voltage read and write operation, with access times as fast as 70ns to eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29LV320A has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full Chip erase operation, where each Sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K

program/erase cycles on each Sector. .

EN29LV320A 32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only

CONNECTION DIAGRAMS

A6 A5 A4

A3 A2 FBGA

Top View, Balls Facing Down

A13

A9 A3 RY/BY#WE# A7 B6 B5 B4

B1 B3 B2 A12

A8 A4

WP# /ACC

RESET# A17 C6 C5 C4

C3 C2 A14

A10 A2

A18

A6 D6D5D4D1

D3D2A15

A11 A1A20A19

A5 E6 E5 E4

E3 E2

A16

DQ7A0DQ2DQ5DQ0F6

F5 F4

F3 F2

BYTE#DQ14CE#DQ10DQ12DQ8G6

G5G4

G3G2

DQ15/A-1

DQ13OE#

DQ11Vcc

DQ9H6 H5

H3 H2 Vss

DQ6 Vss

DQ4

DQ1 F1

DQ3

TABLE 1. PIN DESCRIPTION LOGIC DIAGRAM

Pin Name Function

A0-A20 21 Address inputs

DQ0-DQ14 15 Data Inputs/Outputs

DQ15 / A-1 DQ15 (data input/output, in word mode), A-1 (LSB address input, in byte mode)

CE# Chip

Enable

OE# Output

Enable

WE# Write

Enable

WP#/ACC Write

Protect / Acceleration Pin RESET# Hardware Reset Pin

BYTE# Byte/Word

mode

selection RY/BY# Ready/Busy

Output

Vcc Supply Voltage (2.7-3.6V)

Vss Ground

NC Not Connected to anything

EN29 LV320

A0 – A20

CE#

RY/BY# RESET#

BYTE#

WP#/ACC

OE#

WE#

ORDERING INFORMATION

EN29LV320A T ─70 T C P

PACKAGING CONTENT

(Blank) = Conventional

P = Pb Free

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (-40°C to +85°C)

PACKAGE

T = 48-pin TSOP

B = 48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80mm pitch, 6mm x 8mm package

SPEED

70 = 70ns

90 = 90ns

BOOT CODE SECTOR ARCHITECTURE

Sector

boot

Top

boot

Sector

Bottom

BASE PART NUMBER

EN = EON Silicon Solution Inc.

29LV = FLASH, 3V Read, Program and Erase

320A = 32 Megabit (4M x 8 / 2M x 16)

T able 2A. Top Boot Sector Address Tables (EN29LV320AT)

Sector A20 – A12

Sector Size

(Kbytes / Kwords)

Address Range (h)

Byte mode (x8)

Address Range (h)

Word Mode (x16)

SA0 000000xxx 64/32 000000–00FFFF 000000–007FFF

SA1 000001xxx 64/32 010000–01FFFF 008000–00FFFF SA2 000010xxx 64/32 020000–02FFFF 010000–017FFF

SA3 000011xxx 64/32 030000–03FFFF 018000–01FFFF SA4 000100xxx 64/32 040000–04FFFF 020000–027FFF

SA5 000101xxx 64/32 050000–05FFFF 028000–02FFFF SA6 000110xxx 64/32 060000–06FFFF 030000–037FFF

SA7 000111xxx 64/32 070000–07FFFF 038000–03FFFF SA8 001000xxx 64/32 080000–08FFFF 040000–047FFF

SA9 001001xxx 64/32 090000–09FFFF 048000–04FFFF SA10 001010xxx 64/32 0A0000–0AFFFF 050000–057FFF SA11 001011xxx 64/32 0B0000–0BFFFF 058000–05FFFF SA12 001100xxx 64/32 0C0000–0CFFFF 060000–067FFF

SA13 001101xxx 64/32 0D0000–0DFFFF 068000–06FFFF SA14 001110xxx 64/32 0E0000–0EFFFF 070000–077FFF SA15 001111xxx 64/32 0F0000–0FFFFF 078000–07FFFF SA16 010000xxx 64/32 100000–10FFFF 080000–087FFF

SA17 010001xxx 64/32 110000–11FFFF 088000–08FFFF SA18 010010xxx 64/32 120000–12FFFF 090000–097FFF

SA19 010011xxx 64/32 130000–13FFFF 098000–09FFFF SA20 010100xxx 64/32 140000–14FFFF 0A0000–0A7FFF

SA21 010101xxx 64/32 150000–15FFFF 0A8000–0AFFFF

SA22 010110xxx 64/32 160000–16FFFF 0B0000–0B7FFF

SA23 010111xxx 64/32 170000–17FFFF 0B8000–0BFFFF

SA24 011000xxx 64/32 180000–18FFFF 0C0000–0C7FFF

SA25 011001xxx 64/32 190000–19FFFF 0C8000–0CFFFF

SA26 011010xxx 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA27 011011xxx 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA28 011100xxx 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA29 011101xxx 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA30 011110xxx 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA31 011111xxx 64/32 1F0000–1FFFFF 0F8000–0FFFFF SA32 100000xxx 64/32 200000–20FFFF 100000–107FFF

SA33 100001xxx 64/32 210000–21FFFF 108000–10FFFF SA34 100010xxx 64/32 220000–22FFFF 110000–117FFF

SA35 100011xxx 64/32 230000–23FFFF 118000–11FFFF SA36 100100xxx 64/32 240000–24FFFF 120000–127FFF

SA37 100101xxx 64/32 250000–25FFFF 128000–12FFFF

SA38 100110xxx 64/32 260000–26FFFF 130000–137FFF

SA39 100111xxx 64/32 270000–27FFFF 138000–13FFFF

SA40 101000xxx 64/32 280000–28FFFF 140000–147FFF

SA41 101001xxx 64/32 290000–29FFFF 148000–14FFFF

SA42 101010xxx 64/32 2A0000–2AFFFF 150000–157FFF

SA43 101011xxx 64/32 2B0000–2BFFFF 158000–15FFFF

SA44 101100xxx 64/32 2C0000–2CFFFF 160000–167FFF

SA45 101101xxx 64/32 2D0000–2DFFFF 168000–16FFFF

SA46 101110xxx 64/32 2E0000–2EFFFF 170000–177FFF

SA47 101111xxx 64/32 2F0000–2FFFFF 178000–17FFFF

SA48 110000xxx 64/32 300000–30FFFF 180000–187FFF

SA49 110001xxx 64/32 310000–31FFFF 188000–18FFFF

SA50 110010xxx 64/32 320000–32FFFF 190000–197FFF

SA51 110011xxx 64/32 330000–33FFFF 198000–19FFFF

1A0000–1A7FFF SA52 110100xxx 64/32 340000–34FFFF

1A8000–1AFFFF SA53 110101xxx 64/32 350000–35FFFF

1B0000–1B7FFF SA54 110110xxx 64/32 360000–36FFFF

1B8000–1BFFFF SA55 110111xxx 64/32 370000–37FFFF

SA56 111000xxx 64/32 380000–38FFFF

1C0000–1C7FFF

1C8000–1CFFFF SA57 111001xxx 64/32 390000–39FFFF

SA58 111010xxx 64/32 3A0000–3AFFFF 1D0000–1D7FFF

SA59 111011xxx 64/32 3B0000–3BFFFF 1D8000–1DFFFF

SA60 111100xxx 64/32 3C0000–3CFFFF 1E0000–1E7FFF

SA61 111101xxx 64/32 3D0000–3DFFFF 1E8000–1EFFFF

SA62 111110xxx 64/32 3E0000–3EFFFF 1F0000–1F7FFF

SA63 111111000 8/4 3F0000–3F1FFF 1F8000–1F8FFF

SA64 111111001 8/4 3F2000–3F3FFF 1F9000–1F9FFF

SA65 111111010 8/4 3F4000–3F5FFF 1FA000–1FAFFF

SA66 111111011 8/4 3F6000–3F7FFF 1FB000–1FBFFF

SA67 111111100 8/4 3F8000–3F9FFF 1FC000–1FCFFF

SA68 111111101 8/4 3FA000–3FBFFF 1FD000–1FDFFF

SA69 111111110 8/4 3FC000–3FDFFF 1FE000–1FEFFF

SA70 111111111 8/4 3FE000–3FFFFF 1FF000–1FFFFF

Note: The address bus is A20:A-1 in byte mode where BYTE# = V IL or A20:A0 in word mode where BYTE# = V IH

T able 2B. Bottom Boot Sector Address Tables (EN29LV320AB)

Sector A20 – A12

Sector Size

(Kbytes / Kwords)

Address Range (h)

Byte mode (x8)

Address Range (h)

Word Mode (x16)

SA0 000000000 8/4 000000–001FFF 000000–000FFF SA1 000000001 8/4 002000–003FFF 001000–001FFF SA2 000000010 8/4 004000–005FFF 002000–002FFF SA3 000000011 8/4 006000–007FFF 003000–003FFF SA4 000000100 8/4 008000–009FFF 004000–004FFF SA5 000000101 8/4 00A000–00BFFF 005000–005FFF SA6 000000110 8/4 00C000–00DFFF 006000–006FFF SA7 000000111 8/4 00E000–00FFFF 007000–007FFF SA8 000001xxx 64/32 010000–01FFFF 008000–00FFFF

SA9 000010xxx 64/32 020000–02FFFF 010000–017FFF

SA10 000011xxx 64/32 030000–03FFFF 018000–01FFFF SA11 000100xxx 64/32 040000–04FFFF 020000–027FFF

SA12 000101xxx 64/32 050000–05FFFF 028000–02FFFF SA13 000110xxx 64/32 060000–06FFFF 030000–037FFF

SA14 000111xxx 64/32 070000–07FFFF 038000–03FFFF SA15 001000xxx 64/32 080000–08FFFF 040000–047FFF

SA16 001001xxx 64/32 090000–09FFFF 048000–04FFFF SA17 001010xxx 64/32 0A0000–0AFFFF 050000–057FFF

SA18 001011xxx 64/32 0B0000–0BFFFF 058000–05FFFF SA19 001100xxx 64/32 0C0000–0CFFFF 060000–067FFF

SA20 001101xxx 64/32 0D0000–0DFFFF 068000–06FFFF SA21 001110xxx 64/32 0E0000–0EFFFF 070000–077FFF

SA22 001111xxx 64/32 0F0000–0FFFFF 078000–07FFFF SA23 010000xxx 64/32 100000–10FFFF 080000–087FFF

SA24 010001xxx 64/32 110000–11FFFF 088000–08FFFF SA25 010010xxx 64/32 120000–12FFFF 090000–097FFF

SA26 010011xxx 64/32 130000–13FFFF 098000–09FFFF SA27 010100xxx 64/32 140000–14FFFF 0A0000–0A7FFF SA28 010101xxx 64/32 150000–15FFFF 0A8000–0AFFFF SA29 010110xxx 64/32 160000–16FFFF 0B0000–0B7FFF SA30 010111xxx 64/32 170000–17FFFF 0B8000–0BFFFF SA31 011000xxx 64/32 180000–18FFFF 0C0000–0C7FFF SA32 011001xxx 64/32 190000–19FFFF 0C8000–0CFFFF SA33 011010xxx 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA34 011011xxx 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA35 011100xxx 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA36 011101xxx 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA37 011110xxx 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA38 011111xxx 64/32 1F0000–1FFFFF 0F8000–0FFFFF

SA39 100000xxx 64/32 200000–20FFFF 100000–107FFF

SA40 100001xxx 64/32 210000–21FFFF 108000–10FFFF

SA41 100010xxx 64/32 220000–22FFFF 110000–117FFF

SA42 100011xxx 64/32 230000–23FFFF 118000–11FFFF

SA43 100100xxx 64/32 240000–24FFFF 120000–127FFF

SA44 100101xxx 64/32 250000–25FFFF 128000–12FFFF

SA45 100110xxx 64/32 260000–26FFFF 130000–137FFF

SA46 100111xxx 64/32 270000–27FFFF 138000–13FFFF

SA47 101000xxx 64/32 280000–28FFFF 140000–147FFF

SA48 101001xxx 64/32 290000–29FFFF 148000–14FFFF

SA49 101010xxx 64/32 2A0000–2AFFFF 150000–157FFF

SA50 101011xxx 64/32 2B0000–2BFFFF 158000–15FFFF

SA51 101100xxx 64/32 2C0000–2CFFFF 160000–167FFF

SA52 101101xxx 64/32 2D0000–2DFFFF 168000–16FFFF

SA53 101110xxx 64/32 2E0000–2EFFFF 170000–177FFF

SA54 101111xxx 64/32 2F0000–2FFFFF 178000–17FFFF

SA55 110000xxx 64/32 300000–30FFFF 180000–187FFF

SA56 110001xxx 64/32 310000–31FFFF 188000–18FFFF

SA57 110010xxx 64/32 320000–32FFFF 190000–197FFF

SA58 110011xxx 64/32 330000–33FFFF 198000–19FFFF

SA59 110100xxx 64/32 340000–34FFFF 1A0000–1A7FFF

SA60 110101xxx 64/32 350000–35FFFF 1A8000–1AFFFF

SA61 110110xxx 64/32 360000–36FFFF 1B0000–1B7FFF

SA62 110111xxx 64/32 370000–37FFFF 1B8000–1BFFFF

SA63 111000xxx 64/32 380000–38FFFF 1C0000–1C7FFF

SA64 111001xxx 64/32 390000–39FFFF 1C8000–1CFFFF

SA65 111010xxx 64/32 3A0000–3AFFFF 1D0000–1D7FFF

SA66 111011xxx 64/32 3B0000–3BFFFF 1D8000–1DFFFF

SA67 111100xxx 64/32 3C0000–3CFFFF 1E0000–1E7FFF

SA68 111101xxx 64/32 3D0000–3DFFFF 1E8000–1EFFFF

SA69 111110xxx 64/32 3E0000–3EFFFF 1F0000–1F7FFF

SA70 111111xxx 64/32 3F0000–3FFFFF 1F8000–1FFFFF

Note: The address bus is A20:A-1 in byte mode where BYTE# = V IL or A20:A0 in word mode where BYTE# = V IH

PRODUCT SELECTOR GUIDE

Product Number EN29LV320A

Speed Option

-70 -90 Max Access Time, ns (t acc )

70 90 Max CE# Access, ns (t ce )

70 90 Max OE# Access, ns (t oe )

30 35

Notes:

1. Vcc=3.0 – 3.6 V for 70ns read operation

BLOCK DIAGRAM

WE#

CE# OE#

State Control

Command Register

Erase Voltage Generator

Input/Output Buffers

Program Voltage Generator

Chip Enable Output Enable

Logic

Data Latch

Y-Decoder X-Decoder Y-Gating

Cell Matrix

Timer

Vcc Detector

A0-A20

Vcc Vss

DQ0-DQ15 (A-1)

Address Latch

Block Protect Switches

STB

RY/BY#

TABLE 3. OPERATING MODES

32M FLASH USER MODE TABLE

DQ8-DQ15 Operation CE# OE# WE# RESET # WP#/AC C A0-A20

DQ0-DQ7

BYTE# = V IH BYTE# = V IL Read L L H H L/H A IN D OUT D OUT Write L H L H (Note 1) A IN

D IN

Accelerated Program L H L H

V HH

A IN

D IN

DQ8-DQ14=High-Z, DQ15 = A -1

CMOS Standby

V cc ±

0.3V X X V cc

± 0.3V

H X High-Z High-Z High-Z TTL Standby H X X H H X High-Z High-Z High-Z Output Disable L H H H L/H X High-Z High-Z High-Z Hardware Reset X X X L L/H X High-Z High-Z High-Z Sector (Group)

Protect

L H L V ID

L/H

SA, A6=L, A1=H, A0=L (Note 2)

Sector

Unprotect L H L V ID

(Note 1)

SA, A6=H, A1=H, A0=L (Note 2) X X

Temporary Sector Unprotect X X X V ID

(Note 1) A IN

(Note 2) (Note 2) High-Z

L=logic low= V IL , H=Logic High= V IH , V ID =V HH =11 ± 0.5V = 10.5-11.5V, X=Don’t Care (either L or H, but not floating ), SA=Sector Addresses, D IN =Data In, D OUT =Data Out, A IN =Address In

Notes:

1. If WP#/ACC = V IL , the two outermost boot sectors remain protected. If WP# / ACC = V IH , the outermost boot sector protection depends on whether they were last protected or unprotected. If WP#/ACC = V HH , all sectors will be unprotected.

2. Please refer to “Sector/Sector Group Protection & Chip Unprotection”, Flowchart 7a and Flowchart 7b.

TABLE 4. Autoselect Codes (Using High Voltage, V ID )

32M FLASH MANUFACTURER/DEVICE ID TABLE

L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector Addresses

Note:

1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh.

2. A9 = V ID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.

Description CE# OE# WE# A20 to A12 A11

to A10

A8A7A6

A5 to A2A1 A0 DQ8 to DQ15 DQ7 to DQ0

1Ch Manufacturer ID:

Eon L L H X X V ID

X L

7Fh

Word L L H 22h F6h Device ID

(top boot sector)

Byte L L H X X V ID

X X L X L H X F6h Word L L H 22h

F9h

Device ID

(bottom boot sector)

Byte L L H

X X V ID

X F9h

01h

(Protected)

Sector Protection

Verification

L L H SA X V ID

X X L X H L

00h

(Unprotected)

USER MODE DEFINITIONS

Word / Byte Configuration

The signal set on the BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the BYTE# Pin is set at logic ‘1’, then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.

On the other hand, if the BYTE# Pin is set at logic ‘0’, then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Standby Mode

The EN29LV320A has a CMOS-compatible standby mode, which reduces the c urrent to < 1μA (typical). It is placed in CMOS-compatible standby when the CE# pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC c urrent to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.

Automatic Sleep Mode

The EN29LV320A has a automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for t acc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change.

Read Mode

The device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm

After the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional information.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the “Reset Command” for additional details.

Output Disable Mode

When the OE# pin is at a logic high level (V IH), the output from the EN29LV320A is disabled. The output pins are placed in a high impedance state.

Autoselect Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V ID(10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying

sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.

To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.

Writing Command Sequences

To write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to V IL, and OE# to V IH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. An erase operation can erase one sector or the whole chip.

The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the “Command Definitions” for all the available commands.

RESET#: Hardware Reset

When RESET# is driven low for t RP, all output pins are tristates. All commands written in the internal state machine are reset to reading array data.

Please refer to timing diagram for RESET# pin in “AC Characteristics”.

Sector/Sector Group Protection & Chip Unprotection

The hardware sector group protection feature disables both program and erase operations in any sector. The hardware chip unprotection feature re-enables both program and erase operations in previously protected sectors. A sector group implies three or four adjacent sectors that would be protected at the same time. Please see the following tables which show the organization of sector groups.

There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure. 12 for the timings.

When doing Chip Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle.

The second method is for programming equipment. This method requires V ID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document named EN29LV320A Supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.

Top Boot Sector/Sector Group Organization Table (EN29LV320AT) for (Un)Protection

Sector Group

Sectors

A20-A12 Sector Group Size

SG 0 SA 0-SA 3 0000XXXXX 64 Kbytes x 4 SG 1 SA 4-SA 7 0001XXXXX 64 Kbytes x 4 SG 2 SA 8-SA11 0010XXXXX 64 Kbytes x 4 SG 3 SA12-SA15 0011XXXXX 64 Kbytes x 4 SG 4 SA16-SA19 0100XXXXX 64 Kbytes x 4 SG 5 SA20-SA23 0101XXXXX 64 Kbytes x 4 SG 6 SA24-SA27 0110XXXXX 64 Kbytes x 4 SG 7 SA28-SA31 0111XXXXX 64 Kbytes x 4 SG 8 SA32-SA35 1000XXXXX 64 Kbytes x 4 SG 9 SA36-SA39 1001XXXXX 64 Kbytes x 4 SG10 SA40-SA43 1010XXXXX 64 Kbytes x 4 SG11 SA44-SA47 1011XXXXX 64 Kbytes x 4 SG12 SA48-SA51 1100XXXXX 64 Kbytes x 4 SG13 SA52-SA55 1101XXXXX 64 Kbytes x 4 SG14

SA56-SA59

1110XXXXX 64 Kbytes x 4 SG15 SA60-SA62 111100XXX

111101XXX 111110XXX

64 Kbytes x 3

SG16 SA63 111111000 8 Kbytes SG17 SA64 111111001 8 Kbytes SG18 SA65 111111010 8 Kbytes SG19 SA66 111111011 8 Kbytes SG20 SA67 111111100 8 Kbytes SG21 SA68 111111101 8 Kbytes SG22 SA69 111111110 8 Kbytes SG23 SA70 111111111 8 Kbytes

Bottom Boot Sector/Sector Group Organization Table (EN29LV320AB) for (Un)Protection

Sector Group

Sectors

A20-A12

Sector Group Size

SG23 SA70-SA67 1111XXXXX 64 Kbytes x 4 SG22 SA66-SA63 1110XXXXX 64 Kbytes x 4 SG21 SA62-SA59 1101XXXXX 64 Kbytes x 4 SG20 SA58-SA55 1100XXXXX 64 Kbytes x 4 SG19 SA54-SA51 1011XXXXX 64 Kbytes x 4 SG18 SA50-SA47 1010XXXXX 64 Kbytes x 4 SG17 SA46-SA43 1001XXXXX 64 Kbytes x 4 SG16 SA42-SA39 1000XXXXX 64 Kbytes x 4 SG15 SA38-SA35 0111XXXXX 64 Kbytes x 4 SG14 SA34-SA31 0110XXXXX 64 Kbytes x 4 SG13 SA30-SA27 0101XXXXX 64 Kbytes x 4 SG12 SA26-SA23 0100XXXXX 64 Kbytes x 4 SG11 SA22-SA19 0011XXXXX 64 Kbytes x 4 SG10 SA18-SA15 0010XXXXX 64 Kbytes x 4 SG 9 SA14-SA11 0001XXXXX 64 Kbytes x 4 SG 8 SA10-SA 8 000011XXX 000010XXX 000001XXX 64 Kbytes x 3 SG 7 SA 7 000000111 8 Kbytes SG 6 SA 6 000000110 8 Kbytes SG 5 SA 5 000000101 8 Kbytes SG 4 SA 4 000000100 8 Kbytes SG 3 SA 3 000000011 8 Kbytes SG 2 SA 2 000000010 8 Kbytes SG 1 SA 1 000000001 8 Kbytes SG 0

SA 0

000000000

8 Kbytes

Write Protect / Accelerated Program (WP# / ACC)

The WP#/ACC pin provides two functions. The Write Protect (WP#) function provides a hardware method of protecting the outermost two 8K-byte Boot Sector. The ACC function allows faster manufacturing throughput at the factory, using an external high voltage.

When WP#/ACC is Low, the device protects the outermost tw 8K-byte Boot Sector; no matter the sectors are protected or unprotected using the method described in “Sector/Sector Group Protection & Chip Unprotection”, Program and Erase operations in these sectors are ignored.

When WP#/ACC is High, the device reverts to the previous protection status of the outermost two 8K-byte boot sector. Program and Erase operations can now modify the data in the two outermost 8K-byte Boot Sector unless the sector is protected using Sector Protection.

When WP#/ACC is raised to V HH the memory automatically enters the Unlock Bypass mode(please refer to “Command Definitions”), temporarily unprotects every protected sectors, and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When WP#/ACC returns to V IH or V IL , normal operation resumes. The transitions from V IH or V IL to V HH and from V HH to V IH or V IL must be slower than t V HH , see Figure 11.

Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin must not be at V HH for operations other than accelerated programming. It could cause the device to be damaged.

Never raise this pin to V HH from any mode except Read mode, otherwise the memory may be left in an indeterminate state.

A 0.1μF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PC

B track widths must be sufficient to carry the currents required during Unlock Bypass Program.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Unprotect mode is activated by setting the RESET# pin to VBIDB. During this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. Once VBIDB is removed from the RESET# pin, all the previously protected sectors are protected again. See accompanying flowchart and figure 10 for more timing details.

COMMON FLASH INTERFACE (CFI)

The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

Start Reset#=V ID (note 1)

Perform Erase or Program

Operations

RESET#=V IH

Temporary Sector Unprotect

Completed (note 2)

Notes:

1. All protected sectors are unprotected. (If

WP#/ACC=V IL , outermost boot sectors will remain protected.)

2. Previously protected sectors are protected again.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 5-8.In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.

Table 5. CFI Query Identification String

Addresses (Word Mode)

Adresses (Byte Mode)

Data Description 10h 11h 12h 20h 22h 24h 0051h

0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h

0000h Primary OEM Command Set

15h 16h 2Ah 2Ch 0040h

0000h Address for Primary Extended Table

17h 18h 2Eh 30h 0000h

0000h Alternate OEM Command set (00h = none exists)

19h 1Ah

32h 34h

0000h

Address for Alternate OEM Extended Table (00h = none exists)

Table 6. System Interface String

Addresses (Word Mode)

Addresses

(Byte Mode)

Data Description 1Bh 36h

0027h Vcc Min (write/erase)

DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt

1Ch 38h

0036h Vcc Max (write/erase)

DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt

1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present) 1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)

1Fh 3Eh

0004h Typical timeout per single byte/word write 2N μS 20h 40h

0000h Typical timeout for Min, size buffer write 2N μS (00h = not supported)21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max timeout for full chip erase 2N times typical (00h = not supported)

Table 7. Device Geometry Definition

Addresses (Word mode)

Addresses (Byte Mode)

Data Description 27h 4Eh 0016h Device Size = 2N bytes 28h 29h

50h 52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported)

2Ch 58h 0002h Number of Erase Block Regions within device

2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information

(refer to the CFI specification of CFI publication 100)

31h 32h 33h 34h 62h 64h 66h 68h 003Eh 0000h 0000h 0001h Erase Block Region 2 Information

35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information

39h 3Ah 3Bh 3Ch

72h 74h 76h 78h

0000h 0000h 0000h 0000h

Erase Block Region 4 Information

Table 8. Primary Vendor-specific Extended Query

Addresses (Word Mode)

Addresses (Byte Mode)

Data Description 40h 41h 42h 80h 82h 84h 0050h

0052h 0049h

Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h

88h

0031h Minor version number, ASCII

45h 8Ah 0000h

Address Sensitive Unlock

0 = Required, 1 = Not Required 46h 8Ch 0002h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0004h

Sector Protect

0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000h

Simultaneous Operation

00 = Not Supported, 01 = Supported 4Bh 96h 0000h

Burst Mode Type

00 = Not Supported, 01 = Supported 4Ch 98h 0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 00A5h

Minimum ACC (Acceleration) Supply Voltage

00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV 4Eh 9Ch 00B5h

Maximum ACC (Acceleration) Supply Voltage

00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV

4Fh 9Eh

0002h/ 0003h Top/Bottom Boot Sector Identifier

02h = Bottom Boot, 03h = Top Boot

Hardware Data protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.

Low V CC Write Inhibit

When Vcc is less than V LKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than V LKO.

Write Pulse “Glitch” protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V IL, CE# = V IH, or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = V IL, WE#= V IL and OE# = V IH, the device will not accept commands on the rising edge of WE#.

COMMAND DEFINITIONS

The operations of the device are selected by one or more commands written into the command register. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.

Table 9. EN29LV320A Command Definitions

Bus Cycles

1st

Cycle 2nd

Cycle

3rd

Cycle 4th

Cycle

5th

Cycle

6th

Cycle

Command

Sequence

C y c l e s

Addr Data

Read 1 RA RD Reset 1 xxx F0

0007F

Word

555 2AA

555

1001C

0007F

Manufacturer

ID Byte 4

AAA AA

55555

AAA

2001C

Word 555 2AA

555 x01 22F6

Device ID Top Boot Byte 4

AAA AA

55555

AAA 90

x02 F6 Word 555 2AA

555 x01 22F9

Device ID Bottom Boot Byte 4 AAA AA

55555

AAA 90

x02 F9 00 Word

555

2AA

555

(SA)

X0201 00 A u t o s e l e c t

Sector Protect Verify

Byte 4

AAA AA

555

AAA

(SA)X04

Word 555 2AA

555

Program Byte 4 AAA AA

55555 AAA

A0 PA PD

Word 555 2AA

555

Unlock Bypass

Byte

3 AAA AA

55555 AAA 20

Unlock Bypass Program 2 XXX A0 PA PD Unlock Bypass Reset 2 XXX 90

XXX

Word 555 2AA

555

5552AA 555

Chip Erase Byte 6 AAA AA

55555 AAA

AAA AA 555 55 AAA 10

Word 555 2AA

555

5552AA

Sector Erase

Byte

6 AAA AA

55555 AAA 80

AAA AA 555 55 SA 30

Sector Erase Suspend 1 xxx B0 Sector Erase Resume 1 xxx 30 Word 55 CFI Query Byte

Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PA

SA = Sector Address: address of the Sector to be erased or verified. Address bits A20-A12 uniquely select any Sector.

Reading Array Data

The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program

or Embedded Erase algorithm.

Following a Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system can read array data using the standard read timings from sectors other than the one which is being erase-suspended. If the system reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception.

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high during an active program or erase operation or while in the autoselect mode. See next section for details on Reset.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command.

The reset command may be written between the cycle sequences in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Sector Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the cycle sequences in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies in Sector Erase Suspend mode).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices ID codes, and determine whether or not a sector (group) is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires V ID on address bit A9 and is intended for commercial programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 9 any number of times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Word / Byte Programming Command

The device can be programmed by byte or by word, depending on the state of the BYTE# Pin. Programming the EN29LV320A is performed by using a four-bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.