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MM74HC423A中文资料

? 2004 Fairchild Semiconductor Corporation

DS005338

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September 1983Revised January 2004

MM74HC423A Dual Retriggerable Monostable Multivibrator

MM74HC423A

Dual Retriggerable Monostable Multivibrator

General Description

The 74HC423A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology.They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits.

Each multivibrator features both a negative, A, and a posi-tive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken LOW resets the one shot. The MM74HC423A cannot be triggered from clear.

The MM74HC423A is retriggerable. That is, it may be trig-gered repeatedly while its outputs are generating a pulse and the pulse will be extended.

Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques. The out-put pulse equation is simply: PW = (R EXT ) (C EXT ); where PW

is in seconds, R is in ohms, and C is in farads. All inputs are protected from damage due to static discharge by diodes to V CC and ground.Features

s Typical propagation delay: 40 ns s Wide power supply range: 2V–6V

s Low quiescent current: 80 μA maximum (74HC Series)s Low input current: 1 μA maximum s Fanout of 10 LS-TTL loads s Simple pulse width formula T = RC s Wide pulse range: 400 ns to ∞ (typ)s Part to part variation: ±5% (typ)

s Schmitt Trigger A & B inputs allow rise and fall times to be as slow as one second

Ordering Code:

Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X ” to the ordering code.

Connection Diagrams

Top View

Timing Component

Note: Pin 6 and Pin 14 must be hard-wired to GND.

Order Number Package Number

Package Description

MM74HC423AM (Note 1)

M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC423ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC423AMTC (Note 1)MTC1616-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC423AN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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M M 74H C 423A

Truth Table

=HIGH Level L =LOW Level

↑=Transition from LOW-to-HIGH ↓=Transition from HIGH-to-LOW =One HIGH Level Pulse =One LOW Level Pulse X =Irrelevant

Logic Diagram

Inputs

Outputs

Clear A B Q Q L X X L H X H X L H X X L

H L

↑ H

↓

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MM74HC423A

Theory of Operation

FIGURE 1.

TRIGGER OPERATION

As shown in Figure 1 and the Logic Diagram before an input trigger occurs, the one-shot is in the quiescent state with the Q output LOW, and the timing capacitor C EXT com-pletely charged to V CC . When the trigger input A goes from V CC to GND (while inputs B and clear are held to V CC ) a valid trigger is recognized, which turns on comparator C1and N-Channel transistor N11. At the same time the output latch is set. With transistor N1 on, the capacitor C EXT rap-idly discharges toward GND until V REF1 is reached. At this point the output of comparator C1 changes state and tran-sistor N1 turns OFF. Comparator C1 then turns OFF while at the same time comparator C2 turns on. With transistor N1 OFF, the capacitor C EXT begins to charge through the timing resistor, R EXT , toward V CC . When the voltage across C EXT equals V REF2, comparator C2 changes state causing the output latch to reset (Q goes LOW) while at the same time disabling comparator C2. This ends the timing cycle with the one-shot in the quiescent state, waiting for the next trigger.

A valid trigger is also recognized when trigger input

B goes from GND to V C

C (while input A is at GN

D and input clear is at V CC 2.)

It should be noted that in the quiescent state C EXT is fully charged to V CC causing the current through resistor R EXT to be zero. Both comparators are “OFF ” with the total device current due only to reverse junction leakages. An added feature of the MM74HC423A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is inde-pendent of the value of C EXT , R EXT , or the duty cycle of the input waveform.

RETRIGGER OPERATION

The MM74HC423A is retriggered if a valid trigger occurs 3followed by another trigger 4 before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at pin or has begun to rise from V REF1, but has not yet reached V REF2, will cause an increase in output pulse width T. When a valid retrigger is initiated 4, the voltage at the R/C EXT pin will again drop to V REF1 before progressing along the RC charging curve toward V CC . The Q output will remain high until time T, after the last valid retrigger.

Because the trigger-control circuit flip-flop resets shortly after C X has discharged to the reference voltage of the lower reference circuit, the minimum retrigger time, t rr is a function of internal propagation delays and the discharge time of C X :

Another removal/retrigger time occurs when a short clear pulse is used. Upon receipt of a clear, the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger. This time is dependent on the capacitor used and is approximately:

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M M 74H C 423A

Theory of Operation (Continued)

RESET OPERATION

These one shots may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to V CC by turning on transistor Q1 5. When the voltage on the capacitor reaches V REF2, the reset latch will clear and then be ready to accept another pulse. If the clear input is held LOW, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Clear input, the output pulse T can be made significantly shorter than the minimum pulse width specification.

Typical Output Pulse Width vs.

Timing Components

Typical Distribution of Output Pulse Width, Part to Part

Typical 1ms Pulse Width Variation vs. Supply Minimum R EXT vs. Supply Voltage

Typical 1ms Pulse Width Variation vs. Temperature

Note: R and C are not subjected to temperature. The C is polypropylene.

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MM74HC423A

Absolute Maximum Ratings (Note 2)

(Note 3)

Recommended Operating Conditions

Note 2: Maximum Ratings are those values beyond which damage to the device may occur.

Note 3: Unless otherwise specified all voltages are referenced to ground.Note 4: Power Dissipation Temperature Derating: Plastic “N ” Package: ?12mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 5)

Note 5: For a power supply of 5V ±10% the worst-case output voltages (V OH , V OL ) occur for HC at 4.5V. Thus the 4.5V values should be used when design-ing with this supply. Worst-case V IH and V IL occur at V CC = 5.5V and 4.5V respectively. (The V IH value at 5.5V is 3.85V.) The worst-case leakage current (I IN , I CC , and I OZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

Supply Voltage (V CC )?0.5V to +7.0V DC Input Voltage (V IN )?1.5V to V CC +1.5V DC Output Voltage (V OUT )?0.5V to V CC +0.5V

Clamp Diode Current (I IK , I OK )±20 mA DC Output Current, per pin (I OUT )±25 mA DC V CC or GND Current,per pin (I CC )

±50 mA

Storage Temperature Range (T STG )?65°C to +150°C

Power Dissipation (P D )(Note 4)

600 mW S.O. Package only 500 mW

Lead Temperature (T L ) (Soldering 10 seconds)

260°C Min

Max Units Supply Voltage (V CC )26V DC Input or Output Voltage 0

V CC

(V IN , V OUT )

Operating Temperature Range (T A )?40+85°C

Maximum Input Rise and Fall Time (Clear Input)

V CC = 2.0V 1000ns V CC = 4.5V 500ns V CC = 6.0V

400

Symbol Parameter

Conditions

V CC T A = 25°C T A = ?40 to 85°C T A = ?55 to 125°C Units

Typ

Guaranteed Limits

V IH

Minimum HIGH Level 2.0V 1.5 1.5 1.5V Input Voltage

4.5V 3.15 3.15 3.156.0V 4.2 4.2 4.2V IL

Maximum LOW Level 2.0V 0.30.30.3V Input Voltage

4.5V 0.90.90.96.0V

1.2

V OH

Minimum HIGH Level V IN = V IH or V IL V

Output Voltage

|I OUT | ≤ 20 μA

2.0V 2.0 1.9 1.9 1.94.5V 4.5 4.4 4.4 4.46.0V

6.0

5.9

V IN = V IH or V IL |I OUT | ≤ 4.0 mA 4.5V 3.96 3.84 3.7|I OUT | ≤ 5.2 mA

6.0V

5.46

5.34

5.2

V OL

Maximum LOW Level V IN = V IH or V IL V

Output Voltage

|I OUT | ≤ 20 μA

2.0V 00.10.10.14.5V 00.10.10.16.0V

0.1

V IN = V IH or V IL |I OUT | ≤ 4 mA 4.5V 0.260.330.4|I OUT | ≤ 5.2 mA

6.0V 0.260.330.4I IN Maximum Input Current V IN = V CC or GND

5.0V

0.5

5.0

μA

(Pins 7, 15)

I IN Maximum Input Current V IN = V CC or GND

6.0V

±0.1

±1.0

μA

(all other pins)I CC Maximum Quiescent V IN = V CC or GND 6.0V

8.0

160

μA

Supply Current (standby)I OUT = 0 μA I CC

Maximum Active Supply V IN = V CC or GND 2.0V 3680110130μA Current (per R/C EXT = 0.5V CC

4.5V 0.33 1.0 1.3 1.6mA monostable)

6.0V

0.7

2.0

2.6

3.2

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M M 74H C 423A

AC Electrical Characteristics

V CC = 5V, T A = 25°C, C L = 15 pF, t r = t f = 6 ns

AC Electrical Characteristics

C L = 50 pF t r = t f = 6 ns (Unless otherwise specified)Note 6: C P

D determines the no load dynamic power consumption, P D = C PD V CC 2 f + I CC V CC , and the no load dynamic current consumption, I S = C PD V CC f + I CC .

Symbol Parameter

Conditions

Typ Guatanteed

Limit

Units t PLH Maximum Trigger Propagation Delay, 22

A, B to Q

t PHL Maximum Trigger Propagation Delay, 25

A, B to Q

t PHL Maximum Propagation Delay,20

Clear to Q

t PLH Maximum Propagation Delay,22

Clear to Q

t W Minimum Pulse Width, A, B or Clear 14

26ns t REM Minimum Clear Removal Time 0

ns t WQ(MIN)Minimum Output Pulse Width C EXT = 28 pF 400ns

R EXT = 2 k ?t WQ

Output Pulse Width

C EXT = 1000 pF 10

μs

R EXT = 10 k ?

Symbol Parameter

Conditions V CC T A = 25°C T A = ?40 to 85°C T A = ?55 to 125°C Units

Typ Guaranteed Limits

t PLH

Maximum Trigger Propagation 2.0V 77169194210ns

Delay, A or B to Q

4.5V 264251576.0V 21323944t PHL

Maximum Trigger Propagation 2.0V 88197229250ns

Delay, A or B to Q

4.5V 294860676.0V 24384651t PHL

Maximum Propagation 2.0V 54114132143ns

Delay, Clear to Q

4.5V 233441456.0V 19283336t PLH

Maximum Propagation 2.0V 56116135147ns

Delay, Clear to Q

4.5V 253642466.0V 20293437t W

Minimum Pulse Width 2.0V 57123144157ns

A, B, Clear

4.5V 173037426.0V 12212730t REM

Minimum Clear 2.0V 0000ns Removal Time

4.5V 00006.0V

0000t WQ

Output Pulse Width

C EXT = 0.1 μF Min

5.0V 10.90.860.85ms R EXT = 10 k ?

Max

5.0V 1 1.1 1.14 1.15ms t TLH , t THL Maximum Output Rise

2.0V 307595110ns and Fall Time

4.5V 81519226.0V

713

C P

D Power Dissipation 83pF

Capacitance (Note 6)C IN Maximum Input

12202020pF Capacitance (Pins 7 & 15)C IN

Maximum Input

1010

Capacitance (other inputs)

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Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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M M 74H C 423A

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

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M M 74H C 423A D u a l R e t r i g g e r a b l e M o n o s t a b l e M u l t i v i b r a t o r

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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