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CS4344中文资料

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Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

CS4344/5/6/8

10-Pin, 24-Bit, 192kHz Stereo D/A Converter

Features

Multi-bit Delta-Sigma Modulator 24-Bit Conversion

Automatically Detects Sample Rates up to 192kHz

105 dB Dynamic Range -95 dB THD+N

Low Clock Jitter Sensitivity

Single +3.3V or +5V Power Supply Filtered Line Level Outputs On-Chip Digital De-emphasis Popguard ? Technology

Small 10-Pin TSSOP Package

Description

The CS4344 family members are complete, stereo digital-to-analog output systems including interpolation,multi-bit D/A conversion and output analog filtering in a 10-pin package. The CS4344/5/6/8 support all major audio data interface formats, and the individual devices differ only in the supported interface format.

The CS4344 family is based on a fourth order multi-bit delta-sigma modulator with a linear analog low-pass fil-ter. This family also includes auto-speed mode detection using both sample rate and master clock ratio as a meth-od of auto-selecting sampling rates between 2kHz and 200kHz.

The CS4344 family contains on-chip digital de-empha-sis, operates from a single +3.3V or +5V power supply,and requires minimal support circuitry. These features are ideal for DVD players & recorders, digital televisions,home theater and set top box products, and automotive audio systems.

ORDERING INFORMATION

See page 19

Sep ‘04

Revision History

Release Date Changes

A1SEP 2003Initial Release

PP1JUN 2004Updated Minimum Voltage Condition on page5

Updated Analog Dynamic Performance for 3.3V operation on page6

Updated Full Scale Output Voltage on page6

Updated “High-Level Input Voltage” on page8

Updated Current Consumption Specifications on page8

Corrected specifications for “Internal SCLK Mode” on page9

Updated VQ in “Recommended Connection Diagram” on page11

Updated Ramp Times for “Output Transient Control” on page15

Updated Legal Notice

PP2Sep 2004Update lead-free device ordering info.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to https://www.wendangku.net/doc/fc18449610.html,

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SE-CURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR-RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

TABLE OF CONTENTS

1. PIN DESCRIPTIONS (4)

2. CHARACTERISTICS AND SPECIFICATIONS (5)

SPECIFIED OPERATING CONDITIONS (5)

ABSOLUTE MAXIMUM RATINGS (5)

DAC ANALOG CHARACTERISTICS (6)

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (7)

DIGITAL INPUT CHARACTERISTICS (8)

POWER AND THERMAL CHARACTERISTICS (8)

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE (9)

3. TYPICAL CONNECTION DIAGRAM (11)

4. APPLICATIONS (12)

4.1 Master Clock (12)

4.2 Serial Clock (12)

4.2.1 External Serial Clock Mode (12)

4.2.2 Internal Serial Clock Mode (13)

4.3 De-Emphasis (14)

4.4 Initialization and Power-Down (15)

4.5 Output Transient Control (15)

4.5.1 Power-up (15)

4.5.2 Power-down (15)

4.6 Grounding and Power Supply Decoupling (17)

4.7 Analog Output and Filtering (17)

5. PARAMETER DEFINITIONS (18)

6. ORDER INFORMATION: (19)

7. FUNCTIONAL COMPATIBILITY (19)

8. PACKAGE DIMENSIONS (20)

9. APPENDIX (21)

1.PIN DESCRIPTIONS

Pin Name #Pin Description

SDIN 1Serial Audio Data Input (Input ) - Input for two’s complement serial audio data.

DEM/SCLK 2De-Emphasis/External Serial Clock Input (Input ) - used for de-emphasis filter control or external serial clock input.

LRCK 3Left Right Clock (Input ) - Determines which channel, Left or Right, is currently active on the serial audio data line.

MCLK 4Master Clock (Input ) - Clock source for the delta-sigma modulator and digital filters.VQ 5Quiescent Voltage (Output ) - Filter connection for internal quiescent voltage.

FILT+6Positive Voltage Reference (Output ) - Positive reference voltage for the internal sampling circuits.

AOUTL 7Left Channel Analog Output (Output ) - The full scale analog output level is specified in the Analog Characteristics specification table.GND 8Ground (Input ) - ground reference.

VA 9

Analog Power (Input ) - Positive power for the analog and digital sections.

AOUTR

10Right Channel Analog Output (Output ) - The full scale analog output level is specified in the

Analog Characteristics specification table.

SDIN AOUTR DEM/SCLK

VA LRCK GND MCLK AOUTL VQ

FILT+

2.CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltage and T A = 25°C.)

SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)

ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

Parameters

Symbol Min Nom Max

Units DC Power Supply

VA 4.753.00 5.0

3.3 5.253.47V V Specified Temperature Range

-CZZ -DZZ

T A

-10-40--+70+85

°C °C

Parameters

Symbol Min Max Units DC Power Supply

VA -0.3 6.0V Input Current, Any Pin Except Supplies I in -±10mA Digital Input Voltage

V IND -0.3VA+0.4V Ambient Operating Temperature (power applied)T op -55125°C Storage Temperature

T stg

-65

150

°C

DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997Hz (Note 1),

Fs =48/96/192kHz; Test load R L = 3k ?, C L = 10pF (see Figure 1). Measurement Bandwidth 10 Hz to 20kHz, unless otherwise specified.)

Note: 1.One-half LSB of triangular PDF dither added to data.

DAC ANALOG CHARACTERISTICS - ALL MODES

Parameter

5V Nom

3.3V Nom Min Typ Max Min Typ

Max

Unit

Dynamic Performance for CS4344/5/6/8-CZZ (-10 to 70°C)

Dynamic Range

18 to 24-Bit A-weighted unweighted 16-Bit

A-weighted unweighted

999690871051029693----979490871031009693----dB dB dB dB Total Harmonic Distortion + Noise

18 to 24-Bit

0 dB -20 dB -60 dB 16-Bit

0 dB -20 dB -60 dB -------95-82-42-93-73-33-89-76-36-87-67-27-------95-80-40-93-73-33-89-74-34-87-67-27dB dB dB dB dB dB Dynamic Performance for CS4344-DZZ (-40 to 85°C)Dynamic Range

18 to 24-Bit A-weighted unweighted 16-Bit

A-weighted unweighted

959286831051029693----939086831031009693----dB dB dB dB Total Harmonic Distortion + Noise

18 to 24-Bit

0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB

-------95-82-42-93-73-33

-85-72-32-83-63-23

-------95-80-40-93-73-33

-85-70-30-83-63-23

dB dB dB dB dB dB

Parameter

Symbol

Min Typ Max Unit Interchannel Isolation (1kHz)

-100

-dB

DC Accuracy

Interchannel Gain Mismatch -0.10.25dB Gain Drift -100

-ppm/°C

Analog Output

Full Scale Output Voltage 0.60?VA

0.65?VA 0.70?VA

Vpp Quiescent Voltage

V Q -0.5?VA -VDC Max DC Current draw from an AOUT pin I OUTmax -10-μA Max Current draw from VQ

I Qmax -100-μA Max AC-Load Resistance (see Figure 2 on page 8)R L -3-k ?Max Load Capacitance (see Figure 2)C L -100-pF Output Impedance

Z OUT

-100

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The

filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) (See note 6)

Notes: 2.Response is clock dependent and will scale with Fs.

3.For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.

For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.4.Refer to Figure 2.

5.De-emphasis is available only in Single Speed Mode.

6.Amplitude vs. Frequency plots of this data are available in “Appendix” on page 21.

Parameter

Symbol

Min Typ Max Unit Combined Digital and On-chip Analog Filter Response Single Speed Mode

Passband (Note 2)

to -0.05dB corner to -3dB corner

00--.4780.4996Fs Fs Frequency Response 10Hz to 20kHz -.01-+.08dB StopBand

.5465--Fs StopBand Attenuation (Note 3)

50--dB Group Delay

tgd

-10/Fs -s De-emphasis Error (Note 5)

Fs = 32kHz Fs = 44.1 kHz Fs = 48 kHz ------+1.5/+0+.05/-.25-.2/-.4dB dB dB Combined Digital and On-chip Analog Filter Response Double Speed Mode

Passband (Note 2)

to -0.1dB corner to -3dB corner

00--.4650.4982Fs Fs Frequency Response 10Hz to 20kHz -.05-+.2dB StopBand

.5770

--Fs StopBand Attenuation (Note 3)

55--dB Group Delay

tgd

-5/Fs -s Combined Digital and On-chip Analog Filter Response Quad Speed Mode

Passband (Note 2)

to -0.1dB corner to -3dB corner

00--0.3970.476Fs Fs Frequency Response 10Hz to 20kHz 0-+0.00004

dB StopBand

0.7

--Fs StopBand Attenuation (Note 3)

51--dB Group Delay

tgd

- 2.5/Fs

-s

DIGITAL INPUT CHARACTERISTICS

7.I in for LRCK is ±20μA max.

POWER AND THERMAL CHARACTERISTICS

8.Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are

based on highest FS and highest MCLK. Variance between speed modes is small.9.Power down mode is defined when all clock and data lines are held static.

10.Valid with the recommended capacitor values on VQ and FILT+ as shown in the typical connection

diagram in Section 3.

Parameters

Symbol Min Typ Max

Units High-Level Input Voltage (% of VA)V IH 55%

--V Low-Level Input Voltage (% of VA)V IL --30%V Input Leakage Current (Note 7)

I in --±10μA Input Capacitance

-8

-pF

5V Nom

3.3V Nom

Parameters

Symbol

Min Typ Max Min Typ Max Units Power Supplies

Power Supply Current normal operation (Note 8)power-down state (Note 9)I A I A --2222030---1610021-mA μA Power Dissipation normal operation

power-down state (Note 9)

--1101.1150---530.3369-mW mW Package Thermal Resistance θJA -95--95-°C/Watt Power Supply Rejection Ratio (Note 8)(1kHz)(60Hz)

PSRR

--6040

----6040

--dB dB

Figure 1. Output Test Load Figure 2. Maximum Loading

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

Notes:11.Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on

page 12 for supported ratio’s and frequencies.

12.In Internal SCLK Mode, the Duty Cycle must be 50% +/? 1/2 MCLK Period.

13.The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and

MCLK/LRCK ratio. (See figures 7-9)

Parameters

Symbol Min

Typ Max Units MCLK Frequency 0.512-50MHz MCLK Duty Cycle

55%Input Sample Rate All MCLK/LRCK ratios combined (Note 11)256x, 384x, 1024x

256x, 384x 512x, 768x

1152x 128x, 192x 64x, 96x 128x, 192x Fs

2284423050100168200501346734100200200

kHz kHz kHz kHz kHz kHz kHz kHz External SCLK Mode

LRCK Duty Cycle (External SCLK only)45

5055%SCLK Pulse Width Low t sclkl 20--ns SCLK Pulse Width High t sclkh 20--ns SCLK Duty Cycle

455055%SCLK rising to LRCK edge delay t slrd 20--ns SCLK rising to LRCK edge setup time t slrs 20--ns SDIN valid to SCLK rising setup time t sdlrs 20--ns SCLK rising to SDIN hold time t sdh

--ns Internal SCLK Mode

LRCK Duty Cycle (Internal SCLK only)(Note 12)-50-%SCLK Period

(Note 13)

t sclkw --ns SCLK rising to LRCK edge

t sclkr --μs SDIN valid to SCLK rising setup time

t sdlrs --ns SCLK rising to SDIN hold time

MCLK / LRCK =1152, 1024, 512, 256, 128, or 64t sdh --ns SCLK rising to SDIN hold time

MCLK / LRCK = 768, 384, 192, or 96

t sdh

109SCLK

----------------tsclkw 2

------------------109

512()Fs ---------------------10+109

512()Fs ---------------------15+109

384()Fs

---------------------15+

Figure 3. External Serial Mode Input Timing

Figure 4. Internal Serial Mode Input Timing

* The SCLK pulses shown are internal to the CS4344/5/6/8.

Figure 5. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS4344/5/6/8.

N equals MCLK divided by SCLK

3.TYPICAL CONNECTION DIAGRAM

Figure 6. Recommended Connection Diagram

4.APPLICATIONS

The CS4344 family accepts data at standard audio sample rates including 48, 44.1 and 32kHz in SSM, 96,88.2 and 64kHz in DSM, and 192, 176.4 and 128kHz in QSM. Audio data is input via the serial data input pin (SDIN). The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN,and the optional Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4344/5/6/8 differ in serial data formats as shown in Figures 7-10.

4.1 Master Clock

MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the fre-quency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the re-quired MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK,LRCK and SCLK must be synchronous.

Table 1. Common Clock Frequencies

4.2 Serial Clock

The serial clock controls the shifting of data into the input data buffers. The CS4344 family supports both

external and internal serial clock generation modes. Refer to Figures 7-10 for data formats.

4.2.1 External Serial Clock Mode

The CS4344 family will enter the External Serial Clock Mode when 16 low to high transitions are de-tected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock Mode and de-emphasis filter cannot be accessed. The CS4344 family will switch to Internal Serial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2consecutive frames of LRCK. Refer to Figure 12.

LRCK (kHz)MCLK (MHz)64x 96x 128x 192x 256x 384x 512x 768x

1024x

1152x 32----8.192012.2880--32.7680

36.8640

44.1----11.289616.934422.579233.868045.1580-48----12.288018.4320

24.576036.864049.1520-64--8.192012.2880

--32.7680

49.1520--88.2--11.289616.934422.579233.8680----96--12.288018.4320

24.576036.8640----1288.192012.2880--32.768049.1520

----176.411.289616.934422.579233.8680------19212.288018.432024.576036.8640

------

Mode QSM

DSM

SSM

4.2.2 Internal Serial Clock Mode

In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Figures 7 - 12 for details.

Figure 8. CS4345 Data Format (Left Justified)

Figure 10. CS4348 Data Format (Right Justified 16)

4.3 De-Emphasis

The CS4344 family includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.

The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges of LRCK. This function is available only in the internal serial clock mode.

4.4 Initialization and Power-Down

The Initialization and Power-Down sequence flow chart is shown in Figure 12. The CS4344 family enters the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are re-set, and the internal voltage reference, multi-bit digital-to-analog converters and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Fi-nally, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.

4.5 Output Transient Control

The CS4344 family uses Popguard? technology to minimize the effects of output transients during power-up and power-down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation.

4.5.1 Power-up

When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to VQ which is initially low. After MCLK is applied the outputs begin to ramp with VQ towards the nominal quiescent voltage. This ramp takes approximately 250ms with a 3.3 μF cap connected to VQ (420ms with a 10μF connected to VQ) to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once valid LRCK and SDIN are supplied (and SCLK if used) approximately 2000 sample periods later audio out-put begins.

4.5.2 Power-down

To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the power. In order to do this MCLK should be stopped for a period of about 250ms for a

3.3μF cap connected to VQ (420ms for a 10μF cap connected to VQ) before removing power. Dur-

ing this time voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this time period has passed a transient will occur when the VA supply drops below that of VQ.

There is no minimum time for a power cycle, power may be re-applied at any time.

Figure 12. CS4344/5/6/8 Initialization and Power-Down Sequence

When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it’s zero data state.

4.6 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4344 family requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement with VA connected to a clean +3.3V or +5V supply. For best performance, decoupling and filter capaci-tors should be located as close to the device package as possible with the smallest capacitors closest. 4.7 Analog Output and Filtering

The analog filter present in the CS4344 family is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 13 - 20. The recommended external analog circuitry is shown in the “Typical Connection Diagram” on page11.

5.PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth

made with a -60dBFS signal. 60dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering So-ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

6.ORDER INFORMATION:

Model Temperature Package Serial Interface CS4344-CZZ-10 to +70 °C10-pin Plastic TSSOP - Lead-Free16 to 24-bit, I2S

CS4344-DZZ-40 to +85 °C10-pin Plastic TSSOP - Lead-Free16 to 24-bit, I2S

CS4345-CZZ-10 to +70 °C10-pin Plastic TSSOP - Lead-Free16 to 24-bit, left justified CS4346-CZZ-10 to +70 °C10-pin Plastic TSSOP - Lead-Free24-bit, right justified

CS4348-CZZ-10 to +70 °C10-pin Plastic TSSOP - Lead-Free16-bit, right justified

7.FUNCTIONAL COMPATIBILITY

CS4334-KS ? CS4344-CZZ

CS4335-KS ? CS4345-CZZ

CS4336-KS ? CS4346-CZZ

CS4338-KS ? CS4348-CZZ

CS4334-BS ? CS4344-DZZ

CS4334-DS ? CS4344-DZZ

8.PACKAGE DIMENSIONS

Notes: 1.Reference document: JEDEC MO-187

2. D does not include mold flash or protrusions which is 0.15 mm max. per side.

3.E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side.

4.Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

5.Exceptions to JEDEC dimension.

INCHES

MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX A ----0.0433---- 1.10A10--0.00590--0.15A20.0295--0.03740.75--0.95b 0.0059--0.01180.15--0.304, 5c 0.0031--0.00910.08--0.23D --0.1181 BSC ---- 3.00 BSC --2E --0.1929 BSC ---- 4.90 BSC --E1--0.1181 BSC ---- 3.00 BSC --3

e --0.0197 BSC ----0.50 BSC --L 0.01570.02360.03150.400.600.80L1

--0.0374 REF

----0.95 REF

--∝

0°

--8°

0°

--8°

Controlling Dimension is Millimeters

10LD TSSOP (3mm BODY) PACKAGE DRAWING

123

A2A

SEATING PLANE E11

L SIDE VIEW

END VIEW

TOP VIEW

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