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AT89S52英文资料及中文翻译

AT89S52

Features

Compatible with MCS-51 Products

8K Bytes of In-System Programmable (ISP) Flash Memory –Endurance: 10,000 Write/Erase Cycles

4.0V to

5.5V Operating Range

Fully Static Operation: 0 Hz to 33 MHz

Three-level Program Memory Lock

256 x 8-bit Internal RAM

32 Programmable I/O Lines

Three 16-bit Timer/Counters

Eight Interrupt Sources

Full Duplex UART Serial Channel

Low-power Idle and Power-down Modes

Interrupt Recovery from Power-down Mode

Watchdog Timer、Dual Data Pointer

Power-off Flag、Fast Programming Time

Flexible ISP Programming (Byte and Page Mode)

Green (Pb/Halide-free) Packaging Option

1、Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

2、Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

2.1、Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.

2.2、Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

3、Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.

3.1 、Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT

overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

3.2、WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops.While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

4、 Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol-lowing equation.

The Timer can be configured for either timer or counter operation. In most applications, it is con-figured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency).The baud rate formula is given below.

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.

5、 Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.

Clock-Out Frequency=

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.

6、Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service

routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

7、Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

8、Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

9、Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

中文翻译

AT89S52单片机

主要性能：

与MCS-51单片机产品兼容

8K字节在系统可编程Flash存储器

1000次擦写周期

全静态操作：0Hz～33Hz

三级加密程序存储器

32个可编程I/O口线

三个16位定时器/计数器

八个中断源

全双工UART串行通道

低功耗空闲和掉电模式

掉电后中断可唤醒

看门狗定时器

双数据指针

掉电标识符

1、功能特征描述

AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。AT89S52具有以下标准功能： 8k字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。另外，AT89S52 可降至0Hz 静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下，RAM内容被保存，振荡器被冻结，单片

机一切工作停止，直到下一个中断或硬件复位为止。

2、存储器结构

MCS-51器件有单独的程序存储器和数据存储器。外部程序存储器和数据存储器都可以64K寻址。

2.1、程序存储器

如果EA引脚接地，程序读取只从外部存储器开始。对于89S52，如果EA 接VCC，程序读写先从内部存储器（地址为0000H～1FFFH）开始，接着从外部寻址，寻址地址为：2000H~FFFFH。

2.2、数据存储器

AT89S52 有256 字节片内数据存储器。高128 字节与特殊功能寄存器重叠。也就是说高128字节与特殊功能寄存器有相同的地址，而物理上是分开的。当一条指令访问高于7FH 的地址时，寻址方式决定CPU 访问高128字节RAM 还是特殊功能寄存器空间。直接寻址方式访问特殊功能寄存器（SFR）。例如，下面的直接寻址指令访问0A0H（P2口）存储单元

MOV 0A0H , #data

使用间接寻址方式访问高128 字节RAM。例如，下面的间接寻址方式中，R0 内容为0A0H，访问的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。

MOV @R0 , #data

堆栈操作也是简介寻址方式。因此，高128字节数据RAM也可用于堆栈空间。

3、看门狗定时器

WDT是一种需要软件控制的复位方式。WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器（WDTRST）构成。WDT 在默认情况下无法工作；为了激活WDT，户用必须往WDTRST 寄存器（地址：0A6H）中依次写入01EH 和0E1H。当WDT激活后，晶振工作，WDT在每个机器周期都会增加。WDT计时周期依赖于外部时钟频率。除了复位（硬件复位或WDT溢出复位），没有办法停止WDT工作。当WDT溢出，它将驱动RSR引脚一个高个电平输出。

3.1、WDT的使用

为了激活WDT，用户必须向WDTRST寄存器（地址为0A6H的SFR）依次写入0E1H

和0E1H。当WDT激活后，用户必须向WDTRST写入01EH和0E1H喂狗来避免WDT 溢出。当计数达到8191(1FFFH)时，13 位计数器将会溢出，这将会复位器件。晶振正常工作、WDT激活后，每一个机器周期WDT 都会增加。为了复位WDT，用户必须向WDTRST 写入01EH 和0E1H（WDTRST 是只读寄存器）。WDT 计数器不能读或写。当WDT 计数器溢出时，将给RST 引脚产生一个复位脉冲输出，这个复位脉冲持续96个晶振周期（TOSC），其中TOSC=1/FOSC。为了很好地使用WDT，应该在一定时间内周期性写入那部分代码，以避免WDT复位。

3.2、掉电和空闲方式下的WDT

在掉电模式下，晶振停止工作，这意味这WDT也停止了工作。在这种方式下，用户不必喂狗。有两种方式可以离开掉电模式：硬件复位或通过一个激活的外部中断。通过硬件复位退出掉电模式后，用户就应该给WDT 喂狗，就如同通常AT89S52 复位一样。通过中断退出掉电模式的情形有很大的不同。中断应持续拉低很长一段时间，使得晶振稳定。当中断拉高后，执行中断服务程序。为了防止WDT在中断保持低电平的时候复位器件，WDT 直到中断拉低后才开始工作。这就意味着WDT 应该在中断服务程序中复位。为了确保在离开掉电模式最初的几个状态WDT 不被溢出，最好在进入掉电模式前就复WDT。在进入待机模式前，特殊寄存器AUXR 的WDIDLE位用来决定WDT是否继续计数。默认状态下，在待机模式下，WDIDLE ＝0，WDT继续计数。为了防止WDT在待机模式下复位AT89S52，用户应该建

立一个定时器，定时离开待机模式，喂狗，再重新进入待机模式。

4、波特率发生器

通过设置T2CON中的TCLK或RCLK可选择定时器2 作为波特率发生器。如果定时器2作为发送或接收波特率发生器，定时器1可用作它用，发送和接收的波特率可以不同。设置RCLK 和（或）TCLK 可以使定时器2 工作于波特率产生模式。波特率产生工作模式与自动重载模式相似，因此，TH2 的翻转使得定时器 2 寄存器重载被软件预置16位值的RCAP2H和RCAP2L中的值。模式1和模式3的波特率由定时器2溢出速率决定，具体如下公式：

模式1和模式3波特率=

定时器可设置成定时器，也可为计数器。在多数应用情况下，一般配置成定时方

式（CP/T2=0）。定时器2 用于定时器操作与波特率发生器有所不同，它在每一机器周期 1/12晶振周期）都会增加；然而，作为波特率发生器，它在每一机器状态（1/2晶振周期）都会增加。波特率计算公式如下：

模式1和模式3波特率=

其中，（RCAP2H,RCAP2L）是RCAP2H和RCAP2L组成的16位无符号整数。特别强调，TH2的翻转并不置位TF2，也不产生中断；EXEN2置位后，T2EX引脚上1～0的下跳变不会使（RCAP2H，RCAP2L）重载到（TH2，TL2）中。因此，定时器2作为波特率发生器，T2EX也还可以作为一个额外的外部中断。定时器2处于波特率产生模式，TR2=1，定时器2正常工作。TH2或TL2不应该读写。在这种模式下，定时器在每一状态都会增加，读或写就不会准确。寄存器RCAP2可以读，但不能写，因为写可能和重载交迭，造成写和重载错误。在读写定时器2 或RCAP2寄存器时，应该关闭定时器（TR2清0）。

5、可编程时钟输出

可以通过编程在P1.0 引脚输出一个占空比为50%的时钟信号。这个引脚除了常规的I/O 角外，还有两种可选择功能。它可以通过编程作为定时器/计数器2 的外部时钟输入或占空比为50%的时钟输出。当工作频率为16MHZ时，时钟输出频率范围为61HZ到4HZ。为了把定时器2配置成时钟发生器，位C/2（T2CON.1）必须清0，位T2OE（T2MOD.1）必须置1。位TR2（T2CON.2）启动、停止定时器。时钟输出频率取决于晶振频率和定时器2捕捉寄存器（RCAP2H，RCAP2L）的重载值，如公式所示：

时钟输出频率=

在时钟输出模式下，定时器2不会产生中断，这和定时器2用作波特率发生器一样。定时器2也可以同时用作波特率发生器和时钟产生。不过，波特率和输出时钟频率相互并不独立，它们都依赖于RCAP2H和RCAP2L。

6、中断

AT89S52 有6个中断源：两个外部中断（INT0 和INT1），三个定时中断（定时器0、1、2）和一个串行中断。每个中断源都可以通过置位或清除特殊寄存器IE

中的相关中断允许控制位分别使得中断源有效或无效。IE还包括一个中4[65536]=×?晶振频率时钟输出频率（RCAP2H,RCAP2L）断允许总控制位EA，它能一次禁止所有中断。IE.6位是不可用的。对于AT89S52，IE.5位也是不能用的。用户软件不应给这些位写1。它们为AT89系列新产品预留。定时器2可以被寄存器T2CON中的TF2和EXF2的或逻辑触发。程序进入中断服务后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。它们的值一直到下一个周期被电路捕捉下来。然而，定时器2 的标志位TF2 在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。

7、晶振特性

89S52 单片机有一个用于构成内部振荡器的反相放大器，XTAL1 和XTAL2 分别是放大器的输入、输出端。石英晶体和陶瓷谐振器都可以用来一起构成自激振荡器。从外部时钟源驱动器件的话，XTAL2 可以不接，而从XTAL1 接入。由于外部时钟信号经过二分频触发后作为外部时钟电路输入的，所以对外部时钟信号的占空比没有其它要求，最长低电平持续时间和最少高电平持续时间等还是要符合要求的。

8、空闲模式

在空闲工作模式下，CPU 处于睡眠状态，而所有片上外部设备保持激活状态。这种状态可以通过软件产生。在这种状态下，片上RAM和特殊功能寄存器的内容保持不变。空闲模式可以被任一个中断或硬件复位终止。由硬件复位终止空闲模式只需两个机器周期有效复位信号，在这种情况下，片上硬件禁止访问内部RAM，而可以访问端口引脚。空闲模式被硬件复位终止后，为了防止预想不到的写端口，激活空闲模式的那一条指令的下一条指令不应该是写端口或外部存储器

9、掉电模式

在掉电模式下，晶振停止工作，激活掉电模式的指令是最后一条执行指令。片上RAM和特殊功能寄存器保持原值，直到掉电模式终止。掉电模式可以通过硬件复位和外部中断退出。复位重新定义了SFR 的值，但不改变片上RAM 的值。在VCC

未恢复到正常工作电压时，硬件复位不能无效，并且应保持足够长的时间以使晶振重新工作和初始化。

英文论文及中文翻译

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中文地址翻译成英文地址的方法和技巧中文地址的排列顺序是由大到小，如：Ｘ国Ｘ省Ｘ市Ｘ区Ｘ路Ｘ号，而英文地址则刚好相反，是由小到大。如上例写成英文就是：Ｘ号，Ｘ路，Ｘ区，Ｘ市，Ｘ省，Ｘ国。 1.各部分写法 ●Ｘ室：Room Ｘ ●Ｘ号：No. X ●Ｘ单元：Unit Ｘ ●X楼/层：X/F ●Ｘ号楼：Building No. Ｘ ●住宅区/小区：ResidentialQuater ●Ｘ街：ＸStreet ●Ｘ路：ＸRoad East/Central/West东路/ 中路/ 西路芙蓉西二路/ West 2nd Furong Road Central Dalian Rd. /大连中路芙蓉中路的“中”可以用Central，也有用Middle的，一般用Mid比较简洁。 ●Ｘ区：ＸDistrict ●Ｘ镇：ＸTown ●Ｘ县：ＸCounty ●Ｘ市：ＸCity ●Ｘ省：ＸProvince ●国家（State）中华人民共和国：The People’s Republic of China、P.R.China、P.R.C.、 China ●X信箱：M ailbox X 请注意：翻译人名、路名、街道名等，最好用拼音。各地址单元间要加逗号隔开。

2.英文通信地址常用翻译 201室/房Room 201 二单元Unit 2 马塘村MatangVallage 一号楼/栋Building 1 华为科技公司Huawei Technologies Co., Ltd.

xx公司xx Corp. / xx Co., Ltd. 宿舍Dormitory 厂Factory 楼/层Floor 酒楼/酒店Hotel 住宅区/小区Residential Quater 县County 甲/乙/丙/丁A/B/C/D 镇Town 巷/弄Lane 市City 路Road（也简写作Rd.，注意后面的点不能省略）一环路1st Ring Road 省Province(也简写作Prov.）花园Garden 院Yard 街Street/Avenue 大学College/University 信箱Mailbox 区District A座Suite A 广场Square 州State 大厦/写字楼Tower/Center/Plaza 胡同Alley（北京地名中的条即是胡同的意思）中国部分行政区划对照自治区Autonomous Region 直辖市Municipality 特别行政区Special Administration Region 简称SAR 自治州Autonomous Prefecture