e200z6汇编速查
Freescale Semiconductor Addendum
This errata describes corrections to the e200z6 PowerPC? Core Reference Manual , Revision 0. For convenience, the section number and page number of the errata item in the reference manual are provided. Items in bold are new since the last revision of this document.
To locate any published updates for this document, visit our website listed on the back cover of this document.
Section, Page No.
Changes
2.3.1, 2-8
Add the following to the description of MSR[EE]:
“If MSR[EE] = 0 and a transfer error occurs, a DSI or ISI is taken rather than a machine check or checkstop, as defined by the PowerPC architecture. For more information see the note in Section 5.6.2, “Machine Check Interrupt (IVOR1),”.1 This does not affect the e200z6 with VLE.”
1.Which is provided in an erratum below.
Document Number:e200z6RMAD
Rev. 0.2, 10/2006
Errata to the
e200z6 PowerPC? Core Reference Manual, Rev. 0
2.7.2.3, 2-26Machine Check Syndrome Register (MCSR) bits 59 and 60 are incorrectly shown
to be reserved. Replace Figure 2-21 and Table 2-14 with the following: 323334353637585960616263
Field
MCP—
CP_
PERR
CPERR
EXCP_
ERR
—
BUS_
IRERR
BUS_
DRERR
BUS_
WRERR
—
Reset All zeros
R/W R/W
SPR SPR 572
Figure2-21. Machine Check Syndrome Register (MCSR)
Table2-14. MCSR Field Descriptions
Bits Name Description Recoverable 32MCP Machine check input signal Maybe 33—Reserved, should be cleared.—34CP_PERR Cache push parity error Unlikely 35CPERR Cache parity error Precise 36EXCP_ERR ISI, ITLB, or bus error on first instruction fetch for an exception handler Precise 37–58—Reserved, should be cleared.—59BUS_IRERR Read bus error on Instruction fetch Unlikely 60BUS_DRERR Read bus error on data load Unlikely 61BUS_WRERR Write bus error on buffered store or cache line push Unlikely 62–63—Reserved, should be cleared.—
2.1
3.1, 2-55Add WAM bit 42 to the L1 Cache Control and Status Register 0 (L1CSR0).
Replace Figure 2-40 and Table 2-26 with the following:
Way Partitioning APU Bits
323536394041424344454647 Field WID WDD AWID AWDD WAM CWM DPB DSB DSTRM CPE Reset All zeros
R/W R/W
Line Locking APU Bits
48525354555660616263 Field—CUL CLO CLFR—CABT CFI CE Reset All zeros
R/W R/W
SPR SPR 1010
Figure2-40. L1 Cache Control and Status Register 0 (L1CSR0)
Table2-26. L1CSR0 Field Descriptions
Bits Name Description
32–35WID Way instruction disable. WID and WDD are used for locking ways of the cache and determining the cache replacement policy.
0The corresponding way is available for replacement by instruction miss line fills.
1The corresponding way is not available for replacement by instruction miss line fills.
Bit 0 corresponds to way 0, bit 1 corresponds to way 1, bit 2 corresponds to way 2, and
bit 3 corresponds to way 3.
36–39WDD Way data disable. WID and WDD are used for locking ways of the cache and determining the cache replacement policy.
0The corresponding way is available for replacement by data miss line fills.
1The corresponding way is not available for replacement by data miss line fills.
Bit 4 corresponds to way 0, bit 5 corresponds to way 1, bit 6 corresponds to way 2, bit 7 corresponds to
way 3.
40AWID Additional ways instruction disable
0Additional ways beyond 0–3 are available for replacement by instruction miss line fills.
1Additional ways beyond 0–3 are not available for replacement by instruction miss line fills.
For the 32-Kbyte 8-way cache, ways 4–7 are considered additional ways.
41AWDD Additional ways data disable
0Additional ways beyond 0–3 are available for replacement by data miss line fills.
1Additional ways beyond 0–3 are not available for replacement by data miss line fills.
For the 32-Kbyte 8-way cache, ways 4–7 are considered additional ways.
42WAM Cache way partitioning APU. Way access mode.
0All ways are available for access.
1Only ways partitioned for the specific type of access are used for a fetch or read operation.
Table2-26. L1CSR0 Field Descriptions (continued)
Bits Name Description
43CWM Cache write mode. When set to write-through mode, the W page attribute from an optional MMU is ignored and all writes are treated as write through required. When set, write accesses are performed in copy-back
mode unless the W page attribute from an optional MMU is set.
0Cache operates in write-through mode.
1 Cache operates in copy-back mode.
44DPB Disable push buffer
0Push buffer enabled
1Push buffer disabled
45DSB Disable store buffer
0Store buffer enabled
1Store buffer disabled
46DSTRM Disable streaming
0Streaming is enabled.
1Streaming is disabled.
47CPE Cache parity enable
0Parity checking is disabled.
1 Parity checking is enabled.
48–52—Reserved, should be cleared.
53CUL Cache unable to lock. Indicates a lock set instruction was not effective in locking a cache line. This bit is set by hardware on an “unable to lock” condition (other than lock overflows), and remain set until cleared by
software writing 0 to this bit location.
54CLO Cache lock overflow. Indicates a lock overflow (overlocking) condition occurred. Set by hardware on an overlocking condition, and remains set until cleared by software writing 0 to this bit location.
55CLFC Cache lock bits flash clear. When written to a 1, a cache lock bits flash clear operation is initiated by hardware. Once complete, this bit is reset to 0. Writing a 1 while a flash clear operation is in progress results
in an undefined operation. Writing a 0 to this bit while a flash clear operation is in progress has no effect.
Cache lock bits flash clear operations require approximately 134 cycles to complete. Clearing occurs
regardless of the enable (CE) value.
56–60—Reserved, should be cleared.
61CABT Cache operation aborted. Indicates a cache invalidate or a cache lock bits flash clear operation was aborted prior to completion. Set by hardware on an aborted condition, and remains set until cleared by software
writing 0 to this bit location.
62CINV Cache invalidate
0No cache invalidate
1Cache invalidation operation
When written to a 1, a cache invalidation operation is initiated by hardware. Then invalidation is complete,
CINV is reset to 0. Writing a 1 while invalidation is in progress causes an undefined operation. Writing a 0
to this bit while an invalidation operation is in progress is ignored. Cache invalidation operations require
approximately 134 cycles to complete. Invalidation occurs regardless of the enable (CE) value.
63CE Cache enable. When disabled, cache lookups are not performed for normal load or store accesses.
Other L1CSR0 cache control operations are still available. Also, store buffer operation is not affected by CE.
0Cache is disabled
1Cache is enabled
3.9.2, 3-33Add the following at the end of Section 3.9.2:1
Table 3-11 lists all supported instructions, including VLE instructions. Note that
only the e200z6 with VLE supports the instructions defined by the VLE, which
are designated with the prefixes, e_ and se_.
Table3-11. Full Instruction Listing
Mnemonic Instruction Name Source add Add Book E
add.Add & record CR Book E
addc Add Carrying Book E
addc.Add Carrying & record CR Book E
addco Add Carrying & record OV Book E
addco.Add Carrying & record OV & CR Book E
adde Add Extended with CA Book E
adde.Add Extended with CA & record CR Book E
addeo Add Extended with CA & record OV Book E
addeo.Add Extended with CA & record OV & CR Book E
addi Add Immediate Book E
addic Add Immediate Carrying Book E
addic.Add Immediate Carrying & record CR Book E
addis Add Immediate Shifted Book E
addme Add to Minus One Extended with CA Book E addme.Add to Minus One Extended with CA & record CR Book E addmeo Add to Minus One Extended with CA & record OV Book E addmeo.Add to Minus One Extended with CA & record OV & CR Book E
addo Add & record OV Book E
addo.Add & record OV & CR Book E
addze Add to Zero Extended with CA Book E
addze.Add to Zero Extended with CA & record CR Book E addzeo Add to Zero Extended with CA & record OV Book E addzeo.Add to Zero Extended with CA & record OV & CR Book E
and AND Book E
and.AND & record CR Book E
andc AND with Complement Book E
andc.AND with Complement & record CR Book E
andi.AND Immediate and record CR Book E
1.Note that this change appeared in Revision 0.1 of the addendum but the source for instructions designated with the prefixes e_ and se_ in T able 3-11 has been updated since then.
Mnemonic Instruction Name Source andis.AND Immediate Shifted and record CR Book E
b Branch Book E
ba Branch Absolute Book E bc Branch Conditional Book E bca Branch Conditional Absolute Book E bcctr Branch Conditional to Count Register Book E bcctrl Branch Conditional to Count Register and Link Book E bcl Branch Conditional and Link Book E bcla Branch Conditional and Link Absolute Book E bclr Branch Conditional to Link Register Book E bclrl Branch Conditional to Link Register and Link Book E bl Branch and Link Book E bla Branch and Link Absolute Book E brinc Bit Reversed Increment1SPE cmp Compare Book E cmpi Compare Immediate Book E cmpl Compare Logical Book E cmpli Compare Logical Immediate Book E cntlzw Count Leading Zeros Word Book E cntlzw.Count Leading Zeros Word and record CR Book E crand Condition Register AND Book E crandc Condition Register AND with Complement Book E creqv Condition Register Equivalent Book E crnand Condition Register NAND Book E crnor Condition Register NOR Book E cror Condition Register OR Book E crorc Condition Register OR with Complement Book E crxor Condition Register XOR Book E dcba Data Cache Block Allocate Book E dcbf Data Cache Block Flush Book E dcbi Data Cache Block Invalidate Book E dcblc Data Cache Block Lock Clear Cache locking dcbst Data Cache Block Store Book E dcbt Data Cache Block Touch Book E dcbtls Data Cache Block Touch and Lock Set Cache locking
Mnemonic Instruction Name Source dcbtst Data Cache Block Touch for Store Book E dcbtstls Data Cache Block Touch for Store and Lock Set Cache locking dcbz Data Cache Block set to Zero Book E divw Divide Word Book E divw.Divide Word and record CR Book E divwo Divide Word and record OV Book E divwo.Divide Word and record OV and CR Book E divwu Divide Word Unsigned Book E divwu.Divide Word Unsigned and record CR Book E divwuo Divide Word Unsigned and record OV Book E divwuo.Divide Word Unsigned and record OV and CR Book E efsabs Floating-Point Absolute Value Scalar SPFP efsadd Floating-Point Add Scalar SPFP efscfsf Convert Floating-Point from Signed Fraction Scalar SPFP efscfsi Convert Floating-Point from Signed Integer Scalar SPFP efscfuf Convert Floating-Point from Unsigned Fraction Scalar SPFP efscfui Convert Floating-Point from Unsigned Integer Scalar SPFP efscmpeq Floating-Point Compare Equal Scalar SPFP efscmpgt Floating-Point Compare Greater Than Scalar SPFP efscmplt Floating-Point Compare Less Than Scalar SPFP efsctsf Convert Floating-Point to Signed Fraction Scalar SPFP efsctsi Convert Floating-Point to Signed Integer Scalar SPFP efsctsiz Convert Floating-Point to Signed Integer with Round toward Zero Scalar SPFP efsctuf Convert Floating-Point to Unsigned Fraction Scalar SPFP efsctui Convert Floating-Point to Unsigned Integer Scalar SPFP efsctuiz Convert Floating-Point to Unsigned Integer with Round toward Zero Scalar SPFP efsdiv Floating-Point Divide Scalar SPFP efsmul Floating-Point Multiply Scalar SPFP efsnabs Floating-Point Negative Absolute Value Scalar SPFP efsneg Floating-Point Negate Scalar SPFP efssub Floating-Point Subtract Scalar SPFP efststeq Floating-Point Test Equal Scalar SPFP efststgt Floating-Point Test Greater Than Scalar SPFP efststlt Floating-Point Test Less Than Scalar SPFP eqv Equivalent Book E
Mnemonic Instruction Name Source eqv.Equivalent and record CR Book E evabs Vector Absolute Value SPE evaddiw Vector Add Immediate Word SPE evaddsmiaaw Vector Add Signed, Modulo, Integer to Accumulator Word SPE evaddssiaaw Vector Add Signed, Saturate, Integer to Accumulator Word SPE evaddumiaaw Vector Add Unsigned, Modulo, Integer to Accumulator Word SPE evaddusiaaw Vector Add Unsigned, Saturate, Integer to Accumulator Word SPE evaddw Vector Add Word SPE evand Vector AND SPE evandc Vector AND with Complement SPE evcmpeq Vector Compare Equal SPE evcmpgts Vector Compare Greater Than Signed SPE evcmpgtu Vector Compare Greater Than Unsigned SPE evcmplts Vector Compare Less Than Signed SPE evcmpltu Vector Compare Less Than Unsigned SPE evcntlsw Vector Count Leading Sign Bits Word SPE evcntlzw Vector Count Leading Zeros Word SPE evdivws Vector Divide Word Signed SPE evdivwu Vector Divide Word Unsigned SPE eveqv Vector Equivalent SPE evextsb Vector Extend Sign Byte SPE evextsh Vector Extend Sign Half Word SPE evfsabs Vector Floating-Point Absolute Value SPE evfsabs Floating-Point Absolute Value Vector SPFP evfsadd Vector Floating-Point Add SPE evfsadd Floating-Point Add Vector SPFP evfscfsf Vector Convert Floating-Point from Signed Fraction SPE evfscfsf Convert Floating-Point from Signed Fraction Vector SPFP evfscfsi Vector Convert Floating-Point from Signed Integer SPE evfscfsi Convert Floating-Point from Signed Integer Vector SPFP evfscfuf Vector Convert Floating-Point from Unsigned Fraction SPE evfscfuf Convert Floating-Point from Unsigned Fraction Vector SPFP evfscfui Vector Convert Floating-Point from Unsigned Integer SPE evfscfui Convert Floating-Point from Unsigned Integer Vector SPFP evfscmpeq Vector Floating-Point Compare Equal SPE
Mnemonic Instruction Name Source evfscmpeq Floating-Point Compare Equal Vector SPFP evfscmpgt Vector Floating-Point Compare Greater Than SPE evfscmpgt Floating-Point Compare Greater Than Vector SPFP evfscmplt Vector Floating-Point Compare Less Than SPE evfscmplt Floating-Point Compare Less Than Vector SPFP evfsctsf Vector Convert Floating-Point to Signed Fraction SPE evfsctsf Convert Floating-Point to Signed Fraction Vector SPFP evfsctsi Vector Convert Floating-Point to Signed Integer SPE evfsctsi Convert Floating-Point to Signed Integer Vector SPFP evfsctsiz Vector Convert Floating-Point to Signed Integer with Round toward Zero SPE evfsctsiz Convert Floating-Point to Signed Integer with Round toward Zero Vector SPFP evfsctuf Vector Convert Floating-Point to Unsigned Fraction SPE evfsctuf Convert Floating-Point to Unsigned Fraction Vector SPFP evfsctui Vector Convert Floating-Point to Unsigned Integer SPE evfsctui Convert Floating-Point to Unsigned Integer Vector SPFP evfsctuiz Vector Convert Floating-Point to Unsigned Integer with Round toward Zero SPE evfsctuiz Convert Floating-Point to Unsigned Integer with Round toward Zero Vector SPFP evfsdiv Vector Floating-Point Divide SPE evfsdiv Floating-Point Divide Vector SPFP evfsmul Vector Floating-Point Multiply SPE evfsmul Floating-Point Multiply Vector SPFP evfsnabs Vector Floating-Point Negative Absolute Value SPE evfsnabs Floating-Point Negative Absolute Value Vector SPFP evfsneg Vector Floating-Point Negate SPE evfsneg Floating-Point Negate Vector SPFP evfssub Vector Floating-Point Subtract SPE evfssub Floating-Point Subtract Vector SPFP evfststeq Vector Floating-Point T est Equal SPE evfststeq Floating-Point Test Equal Vector SPFP evfststgt Vector Floating-Point T est Greater Than SPE evfststgt Floating-Point Test Greater Than Vector SPFP evfststlt Vector Floating-Point T est Less Than SPE evfststlt Floating-Point Test Less Than Vector SPFP evldd Vector Load Double Word into Double Word SPE evlddx Vector Load Double Word into Double Word Indexed SPE
Mnemonic Instruction Name Source evldh Vector Load Double into Half Words SPE evldhx Vector Load Double into Half Words Indexed SPE evldw Vector Load Double into Two Words SPE evldwx Vector Load Double into Two Words Indexed SPE evlhhesplat Vector Load Half Word into Half Words Even and Splat SPE evlhhesplatx Vector Load Half Word into Half Words Even and Splat Indexed SPE evlhhossplat Vector Load Half Word into Half Word Odd Signed and Splat SPE evlhhossplatx Vector Load Half Word into Half Word Odd Signed and Splat Indexed SPE evlhhousplat Vector Load Half Word into Half Word Odd Unsigned and Splat SPE evlhhousplatx Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed SPE evlwhe Vector Load Word into T wo Half Words Even SPE evlwhex Vector Load Word into T wo Half Words Even Indexed SPE evlwhos Vector Load Word into Half Words Odd Signed (with sign extension)SPE evlwhosx Vector Load Word into Half Words Odd Signed Indexed (with sign extension)SPE evlwhou Vector Load Word into T wo Half Words Odd Unsigned (zero-extended)SPE evlwhoux Vector Load Word into T wo Half Words Odd Unsigned Indexed (zero-extended)SPE evlwhsplat Vector Load Word into Half Words and Splat SPE evlwhsplatx Vector Load Word into Half Words and Splat Indexed SPE evlwwsplat Vector Load Word into Word and Splat SPE evlwwsplatx Vector Load Word into Word and Splat Indexed SPE evmergehi Vector Merge High SPE evmergehilo Vector Merge High/Low SPE evmergelo Vector Merge Low SPE evmergelohi Vector Merge Low/High SPE evmhegsmfaa Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate SPE
SPE evmhegsmfan Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate
Negative
evmhegsmiaa Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate SPE
SPE evmhegsmian Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate
Negative
evmhegumiaa Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and Accumulate SPE
SPE evmhegumian Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and Accumulate
Negative
evmhesmf Vector Multiply Half Words, Even, Signed, Modulo, Fractional SPE evmhesmfa Vector Multiply Half Words, Even, Signed, Modulo, Fractional, Accumulate SPE
Mnemonic Instruction Name Source evmhesmfaaw Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate into
SPE Words
SPE evmhesmfanw Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate
Negative into Words
evmhesmi Vector Multiply Half Words, Even, Signed, Modulo, Integer SPE evmhesmia Vector Multiply Half Words, Even, Signed, Modulo, Integer, Accumulate SPE evmhesmiaaw Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate into Words SPE
SPE evmhesmianw Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate Negative
into Words
evmhessf Vector Multiply Half Words, Even, Signed, Saturate, Fractional SPE evmhessfa Vector Multiply Half Words, Even, Signed, Saturate, Fractional, Accumulate SPE evmhessfaaw Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate into
SPE Words
SPE evmhessfanw Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate
Negative into Words
SPE evmhessiaaw Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate into
Words
evmhessianw Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate Negative
SPE into Words
evmheumi Vector Multiply Half Words, Even, Unsigned, Modulo, Integer SPE evmheumia Vector Multiply Half Words, Even, Unsigned, Modulo, Integer, Accumulate SPE evmheumiaaw Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate into
SPE Words
SPE evmheumianw Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate
Negative into Words
SPE evmheusiaaw Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate into
Words
evmheusianw Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate
SPE Negative into Words
evmhogsmfaa Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate SPE
SPE evmhogsmfan Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate
Negative
evmhogsmiaa Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate SPE
SPE evmhogsmian Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate
Negative
evmhogumiaa Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate SPE
SPE evmhogumian Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate
Negative
evmhosmf Vector Multiply Half Words, Odd, Signed, Modulo, Fractional SPE evmhosmfa Vector Multiply Half Words, Odd, Signed, Modulo, Fractional, Accumulate SPE
Mnemonic Instruction Name Source evmhosmfaaw Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and Accumulate into
SPE Words
SPE evmhosmfanw Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and Accumulate
Negative into Words
evmhosmi Vector Multiply Half Words, Odd, Signed, Modulo, Integer SPE evmhosmia Vector Multiply Half Words, Odd, Signed, Modulo, Integer, Accumulate SPE evmhosmiaaw Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate into Words SPE
SPE evmhosmianw Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate Negative
into Words
evmhossf Vector Multiply Half Words, Odd, Signed, Saturate, Fractional SPE evmhossfa Vector Multiply Half Words, Odd, Signed, Saturate, Fractional, Accumulate SPE
SPE evmhossfaaw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate into
Words
SPE evmhossfanw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate
Negative into Words
evmhossiaaw Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate into Words SPE
SPE evmhossianw Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate Negative
into Words
evmhoumi Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer SPE evmhoumia Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer, Accumulate SPE evmhoumiaaw Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate into
SPE Words
SPE evmhoumianw Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate Negative
into Words
evmhousiaaw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate into
SPE Words
SPE evmhousianw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate
Negative into Words
evmra Initialize Accumulator SPE evmwhsmf Vector Multiply Word High Signed, Modulo, Fractional SPE evmwhsmfa Vector Multiply Word High Signed, Modulo, Fractional and Accumulate SPE evmwhsmi Vector Multiply Word High Signed, Modulo, Integer SPE evmwhsmia Vector Multiply Word High Signed, Modulo, Integer and Accumulate SPE evmwhssf Vector Multiply Word High Signed, Saturate, Fractional SPE evmwhssfa Vector Multiply Word High Signed, Saturate, Fractional and Accumulate SPE evmwhumi Vector Multiply Word High Unsigned, Modulo, Integer SPE evmwhumia Vector Multiply Word High Unsigned, Modulo, Integer and Accumulate SPE evmwlsmi Vector Multiply Word Low Unsigned, Modulo, Integer SPE
Mnemonic Instruction Name Source evmwlsmiaaw Vector Multiply Word Low Signed, Modulo, Integer and Accumulate in Words SPE evmwlsmianw Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words SPE evmwlssiaaw Vector Multiply Word Low Signed, Saturate, Integer and Accumulate in Words SPE
SPE evmwlssianw Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in
Words
evmwlumia Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate SPE evmwlumiaaw Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate in Words SPE
SPE evmwlumianw Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in
Words
evmwlusiaaw Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate in Words SPE
SPE evmwlusianw Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in
Words
evmwsmf Vector Multiply Word Signed, Modulo, Fractional SPE evmwsmfa Vector Multiply Word Signed, Modulo, Fractional and Accumulate SPE evmwsmfaa Vector Multiply Word Signed, Modulo, Fractional and Accumulate SPE evmwsmfan Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative SPE evmwsmi Vector Multiply Word Signed, Modulo, Integer SPE evmwsmia Vector Multiply Word Signed, Modulo, Integer and Accumulate SPE evmwsmiaa Vector Multiply Word Signed, Modulo, Integer and Accumulate SPE evmwsmian Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative SPE evmwssf Vector Multiply Word Signed, Saturate, Fractional SPE evmwssfa Vector Multiply Word Signed, Saturate, Fractional and Accumulate SPE evmwssfaa Vector Multiply Word Signed, Saturate, Fractional and Accumulate SPE evmwssfan Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative SPE evmwumi Vector Multiply Word Unsigned, Modulo, Integer SPE evmwumia Vector Multiply Word Unsigned, Modulo, Integer and Accumulate SPE evmwumiaa Vector Multiply Word Unsigned, Modulo, Integer and Accumulate SPE evmwumian Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative SPE evnand Vector NAND SPE evneg Vector Negate SPE evnor Vector NOR SPE evor Vector OR SPE evorc Vector OR with Complement SPE evrlw Vector Rotate Left Word SPE evrlwi Vector Rotate Left Word Immediate SPE evrndw Vector Round Word SPE
Mnemonic Instruction Name Source evsel Vector Select SPE
evslw Vector Shift Left Word SPE
evslwi Vector Shift Left Word Immediate SPE evsplatfi Vector Splat Fractional Immediate SPE evsplati Vector Splat Immediate SPE evsrwis Vector Shift Right Word Immediate Signed SPE evsrwiu Vector Shift Right Word Immediate Unsigned SPE evsrws Vector Shift Right Word Signed SPE evsrwu Vector Shift Right Word Unsigned SPE
evstdd Vector Store Double of Double SPE evstddx Vector Store Double of Double Indexed SPE
evstdh Vector Store Double of Four Half Words SPE evstdhx Vector Store Double of Four Half Words Indexed SPE evstdw Vector Store Double of Two Words SPE evstdwx Vector Store Double of Two Words Indexed SPE evstwhe Vector Store Word of T wo Half Words from Even SPE evstwhex Vector Store Word of T wo Half Words from Even Indexed SPE evstwho Vector Store Word of T wo Half Words from Odd SPE evstwhox Vector Store Word of T wo Half Words from Odd Indexed SPE evstwwe Vector Store Word of Word from Even SPE evstwwex Vector Store Word of Word from Even Indexed SPE evstwwo Vector Store Word of Word from Odd SPE evstwwox Vector Store Word of Word from Odd Indexed SPE evsubfsmiaaw Vector Subtract Signed, Modulo, Integer to Accumulator Word SPE evsubfssiaaw Vector Subtract Signed, Saturate, Integer to Accumulator Word SPE evsubfumiaaw Vector Subtract Unsigned, Modulo, Integer to Accumulator Word SPE evsubfusiaaw Vector Subtract Unsigned, Saturate, Integer to Accumulator Word SPE evsubfw Vector Subtract from Word SPE evsubifw Vector Subtract Immediate from Word SPE
evxor Vector XOR SPE
extsb Extend Sign Byte Book E extsb.Extend Sign Byte and record CR Book E extsh Extend Sign Half Word Book E extsh.Extend Sign Half Word and record CR Book E e_add16i Add Immediate VLE (32-bit opcodes)
Mnemonic Instruction Name Source
e_add2i.Add (2 operand) Immediate and Record CR VLE (32-bit opcodes) e_add2is Add (2 operand) Immediate Shifted VLE (32-bit opcodes) e_addi Add Immediate VLE (32-bit opcodes) e_addi.Add Immediate and Record VLE (32-bit opcodes) e_addic Add Immediate Carrying VLE (32-bit opcodes) e_addic.Add Immediate Carrying and Record VLE (32-bit opcodes) e_and2i.AND (2 operand) Immediate & record CR VLE (32-bit opcodes) e_and2is.AND (2 operand) Immediate Shifted & record CR VLE (32-bit opcodes) e_andi AND Immediate VLE (32-bit opcodes) e_andi. AND Immediate and Record VLE (32-bit opcodes) e_b Branch VLE (32-bit opcodes) e_bc Branch Conditional VLE (32-bit opcodes) e_bcl Branch Conditional & Link VLE (32-bit opcodes) e_bl Branch & Link VLE (32-bit opcodes) e_cmp16i Compare Immediate VLE (32-bit opcodes) e_cmph Compare Halfword VLE (32-bit opcodes) e_cmph16i Compare Halfword Immediate VLE (32-bit opcodes) e_cmphl Compare Halfword Logical VLE (32-bit opcodes) e_cmphl16i Compare Halfword Logical Immediate VLE (32-bit opcodes) e_cmpi Compare Immediate VLE (32-bit opcodes) e_cmpl16i Compare Logical Immediate VLE (32-bit opcodes) e_cmpli Compare Logical Immediate VLE (32-bit opcodes) e_crand Condition Register AND VLE (32-bit opcodes) e_crandc Condition Register AND with Complement VLE (32-bit opcodes) e_creqv Condition Register Equivalent VLE (32-bit opcodes) e_crnand Condition Register NAND VLE (32-bit opcodes) e_crnor Condition Register NOR VLE (32-bit opcodes) e_cror Condition Register OR VLE (32-bit opcodes) e_crorc Condition Register OR with Complement VLE (32-bit opcodes) e_crxor Condition Register XOR VLE (32-bit opcodes) e_lbz Load Byte & Zero VLE (32-bit opcodes) e_lbzu Load Byte & Zero with Update VLE (32-bit opcodes) e_lha Load Halfword Algebraic VLE (32-bit opcodes) e_lhau Load Halfword Algebraic With Update VLE (32-bit opcodes) e_lhz Load Halfword & Zero VLE (32-bit opcodes)
Mnemonic Instruction Name Source
e_lhzu Load Halfword & Zero with Update VLE (32-bit opcodes) e_li Load Immediate VLE (32-bit opcodes) e_lis Load Immediate Shifted VLE (32-bit opcodes) e_lmw Load Multiple Word VLE (32-bit opcodes) e_lwz Load Word & Zero VLE (32-bit opcodes) e_lwzu Load Word & Zero with Update VLE (32-bit opcodes) e_mcrf Move Condition Register Field VLE (32-bit opcodes) e_mull2i Multiply Low Word (2 operand) Immediate VLE (32-bit opcodes) e_mulli Multiply Low Immediate VLE (32-bit opcodes) e_or2i OR (2 operand) Immediate VLE (32-bit opcodes) e_or2is OR (2 operand) Immediate Shifted VLE (32-bit opcodes) e_ori OR Immediate VLE (32-bit opcodes) e_ori.OR Immediate and Record VLE (32-bit opcodes) e_rlw Rotate Left Word VLE (32-bit opcodes) e_rlw.Rotate Left Word & record CR VLE (32-bit opcodes) e_rlwi Rotate Left Word Immediate VLE (32-bit opcodes) e_rlwi.Rotate Left Word Immediate & record CR VLE (32-bit opcodes) e_rlwimi Rotate Left Word Immed then Mask Insert VLE (32-bit opcodes) e_rlwinm Rotate Left Word Immed then AND with Mask VLE (32-bit opcodes) e_slwi Shift Left Word Immediate VLE (32-bit opcodes) e_slwi.Shift Left Word Immediate & record CR VLE (32-bit opcodes) e_srwi Shift Right Word Immediate VLE (32-bit opcodes) e_srwi.Shift Right Word Immediate & record CR VLE (32-bit opcodes) e_stb Store Byte VLE (32-bit opcodes) e_stbu Store Byte with Update VLE (32-bit opcodes) e_sth Store Halfword VLE (32-bit opcodes) e_sthu Store Halfword with Update VLE (32-bit opcodes) e_stmw Store Multiple Word VLE (32-bit opcodes) e_stw Store Word VLE (32-bit opcodes) e_stwu Store Word with Update VLE (32-bit opcodes) e_subfic Subtract from Immediate Carrying VLE (32-bit opcodes) e_subfic. Subtract from Immediate and Record VLE (32-bit opcodes) e_xori XOR Immediate VLE (32-bit opcodes) e_xori.XOR Immediate and Record VLE (32-bit opcodes) icbi Instruction Cache Block Invalidate Book E
Mnemonic Instruction Name Source icblc Instruction Cache Block Lock Clear Cache locking icbt Instruction Cache Block Touch Book E icbtls Instruction Cache Block Touch and Lock Set Cache locking isel Integer Select EIS isync Instruction Synchronize Book E lbz Load Byte and Zero Book E lbzu Load Byte and Zero with Update Book E lbzux Load Byte and Zero with Update Indexed Book E lbzx Load Byte and Zero Indexed Book E lha Load Half Word Algebraic Book E lhau Load Half Word Algebraic with Update Book E lhaux Load Half Word Algebraic with Update Indexed Book E lhax Load Half Word Algebraic Indexed Book E lhbrx Load Half Word Byte-Reverse Indexed Book E lhz Load Half Word and Zero Book E lhzu Load Half Word and Zero with Update Book E lhzux Load Half Word and Zero with Update Indexed Book E lhzx Load Half Word and Zero Indexed Book E lmw Load Multiple Word Book E lwarx Load Word and Reserve Indexed Book E lwbrx Load Word Byte-Reverse Indexed Book E lwz Load Word and Zero Book E lwzu Load Word and Zero with Update Book E lwzux Load Word and Zero with Update Indexed Book E lwzx Load Word and Zero Indexed Book E mbar2Memory Barrier Book E mcrf Move Condition Register Field Book E mcrxr Move to Condition Register from XER Book E mfcr Move From Condition Register Book E mfdcr3Move From Device Control Register Book E mfdcrx3Move From Device Control Register Indexed Book E mfmsr Move From Machine State Register Book E mfspr Move From Special Purpose Register Book E msync2Memory Synchronize Book E mtcrf Move To Condition Register Fields Book E
Mnemonic Instruction Name Source mtdcr3Move To Device Control Register Book E mtdcrx3Move To Device Control Register Indexed Book E mtmsr Move To Machine State Register Book E mtspr Move To Special Purpose Register Book E mulhw Multiply High Word Book E mulhw.Multiply High Word and record CR Book E mulhwu Multiply High Word Unsigned Book E mulhwu.Multiply High Word Unsigned and record CR Book E mulli Multiply Low Immediate Book E mullw Multiply Low Word Book E mullw.Multiply Low Word and record CR Book E mullwo Multiply Low Word and record OV Book E mullwo.Multiply Low Word and record OV and CR Book E nand NAND Book E nand.NAND and record CR Book E neg Negate Book E neg.Negate and record CR Book E nego Negate and record OV Book E nego.Negate and record OV and record CR Book E nor NOR Book E nor.NOR and record CR Book E or OR Book E or.OR and record CR Book E orc OR with Complement Book E orc.OR with Complement and record CR Book E ori OR Immediate Book E oris OR Immediate Shifted Book E rfci Return From Critical Interrupt Book E rfdi Return From Debug Interrupt Debug rfi Return From Interrupt Book E rlwimi Rotate Left Word Immed then Mask Insert Book E rlwimi.Rotate Left Word Immed then Mask Insert and record CR Book E rlwinm Rotate Left Word Immed then AND with Mask Book E rlwinm.Rotate Left Word Immed then AND with Mask and record CR Book E rlwnm Rotate Left Word then AND with Mask Book E
Mnemonic Instruction Name Source rlwnm.Rotate Left Word then AND with Mask and record CR Book E sc System Call Book E
se_add Add VLE (16-bit opcodes) se_addi Add Immediate VLE (16-bit opcodes) se_and AND VLE (16-bit opcodes) se_and.AND and Record VLE (16-bit opcodes) se_andc AND with Complement VLE (16-bit opcodes) se_andi And Immediate VLE (16-bit opcodes) se_b Branch VLE (16-bit opcodes) se_bc Branch Conditional VLE (16-bit opcodes) se_bclri Bit Clear Immediate VLE (16-bit opcodes) se_bctr Branch to Count Register VLE (16-bit opcodes) se_bctrl Branch to Count Register & Link VLE (16-bit opcodes) se_bgeni Bit Generate Immediate VLE (16-bit opcodes) se_bl Branch and Link VLE (16-bit opcodes) se_blr Branch to Link Register VLE (16-bit opcodes) se_blrl Branch to Link Register & Link VLE (16-bit opcodes) se_bmaski Bit Mask Generate Immediate VLE (16-bit opcodes) se_bseti Bit Set Immediate VLE (16-bit opcodes) se_btsti Bit T est Immediate VLE (16-bit opcodes) se_cmp Compare VLE (16-bit opcodes) se_cmph Compare Halfword VLE (16-bit opcodes) se_cmphl Compare Halfword Logical VLE (16-bit opcodes) se_cmpi Compare Immediate VLE (16-bit opcodes) se_cmpl Compare Logical VLE (16-bit opcodes) se_cmpli Compare Logical Immediate VLE (16-bit opcodes) se_extsb Extend Sign Byte VLE (16-bit opcodes) se_extsh Extend Sign Halfword VLE (16-bit opcodes) se_extzb Extend with Zeros Byte VLE (16-bit opcodes) se_extzh Extend with Zeros Halfword VLE (16-bit opcodes) se_illegal Illegal VLE (16-bit opcodes) se_isync Instruction Synchronize VLE (16-bit opcodes) se_lbz Load Byte and Zero VLE (16-bit opcodes) se_lhz Load Halfword and Zero VLE (16-bit opcodes) se_li Load Immediate VLE (16-bit opcodes)
Mnemonic Instruction Name Source
se_lwz Load Word and Zero VLE (16-bit opcodes) se_mfar Move from Alternate Register VLE (16-bit opcodes) se_mfctr Move From Count Register VLE (16-bit opcodes) se_mflr Move From Link Register VLE (16-bit opcodes) se_mr Move Register VLE (16-bit opcodes) se_mtar Move to Alternate Register VLE (16-bit opcodes) se_mtctr Move To Count Register VLE (16-bit opcodes) se_mtlr Move To Link Register VLE (16-bit opcodes) se_mullw Multiply Low Word VLE (16-bit opcodes) se_neg Negate VLE (16-bit opcodes) se_not NOT VLE (16-bit opcodes) se_or OR VLE (16-bit opcodes) se_rfci Return From Critical Interrupt VLE (16-bit opcodes) se_rfdi Return From Debug Interrupt VLE (16-bit opcodes) se_rfi Return From Interrupt VLE (16-bit opcodes) se_sc System Call VLE (16-bit opcodes) se_slw Shift Left Word VLE (16-bit opcodes) se_slwi Shift Left Word Immediate VLE (16-bit opcodes) se_sraw Shift Right Algebraic Word VLE (16-bit opcodes) se_srawi Shift Right Algebraic Word Immediate VLE (16-bit opcodes) se_srw Shift Right Word VLE (16-bit opcodes) se_srwi Shift Right Word Immediate VLE (16-bit opcodes) se_stb Store Byte VLE (16-bit opcodes) se_sth Store Halfword VLE (16-bit opcodes) se_stw Store Word VLE (16-bit opcodes) se_sub Subtract VLE (16-bit opcodes) se_subf Subtract From VLE (16-bit opcodes) se_subi Subtract Immediate VLE (16-bit opcodes) se_subi.Subtract Immediate and Record VLE (16-bit opcodes) slw Shift Left Word Book E slw.Shift Left Word and record CR Book E sraw Shift Right Algebraic Word Book E sraw.Shift Right Algebraic Word and record CR Book E srawi Shift Right Algebraic Word Immediate Book E srawi.Shift Right Algebraic Word Immediate and record CR Book E
51单片机汇编指令速查表
51单片机汇编指令速查表 指令格式功能简述字节数周期 一、数据传送类指令 MOV A， Rn 寄存器送累加器 1 1 MOV Rn，A 累加器送寄存器 1 1 MOV A ，＠Ri 内部RAM单元送累加器 1 1 MOV ＠Ri ，A 累加器送内部RAM单元 1 1 MOV A ，#data 立即数送累加器 2 1 MOV A ，direct 直接寻址单元送累加器 2 1 MOV direct ，A 累加器送直接寻址单元 2 1 MOV Rn，#data 立即数送寄存器 2 1 MOV direct ，#data 立即数送直接寻址单元 3 2 MOV ＠Ri ，#data 立即数送内部RAM单元 2 1 MOV direct ，Rn 寄存器送直接寻址单元 2 2 MOV Rn ，direct 直接寻址单元送寄存器 2 2 MOV direct ，＠Ri 内部RAM单元送直接寻址单元 2 2 MOV ＠Ri ，direct 直接寻址单元送内部RAM单元 2 2 MOV direct2，direct1 直接寻址单元送直接寻址单元 3 2 MOV DPTR ，#data16 16位立即数送数据指针 3 2 MOVX A ，＠Ri 外部RAM单元送累加器(8位地址) 1 2 MOVX ＠Ri ，A 累加器送外部RAM单元(8位地址) 1 2 MOVX A ，＠DPTR 外部RAM单元送累加器(16位地址) 1 2 MOVX ＠DPTR ，A 累加器送外部RAM单元(16位地址) 1 2 MOVC A ，＠A+DPTR 查表数据送累加器(DPTR为基址) 1 2 MOVC A ，＠A+PC 查表数据送累加器(PC为基址) 1 2 XCH A ，Rn 累加器与寄存器交换 1 1 XCH A ，＠Ri 累加器与内部RAM单元交换 1 1 XCHD A ，direct 累加器与直接寻址单元交换 2 1 XCHD A ，＠Ri 累加器与内部RAM单元低4位交换 1 1 SWAP A 累加器高4位与低4位交换 1 1 POP direct 栈顶弹出指令直接寻址单元 2 2 PUSH direct 直接寻址单元压入栈顶 2 2 二、算术运算类指令 ADD A， Rn 累加器加寄存器 1 1
汇编指令和机器码的对应表
汇编指令和机器码的对应表 汇编2010-04-20 21:07:19 阅读259 评论0 字号：大中小订阅 一、汇编速查 MOV AA,BB 将BB 放到AA 里 CALL 调用子程序(相当于BASIC 的GOSUB) RET 与RETF 返回程序(相当于BASIC 的RETURN) CMP XX,YY 比较XX 与YY JZ 若相等则转移 JNZ 若不相等则转移 JB 若小于则转移 JG 若大于则转移 JMP 无条件转移 J??? (各种转移指令) LOOP 循环直到CX为0 INT XX 类似CALL 的中断涵数 PUSH 推入栈（STACK）ESP：PUSH AX POP 出栈ESP：POP CX XCHG 交换ESP：XCHG AX，BX IN、OUT 与PORT有关的IN/OUT XLAT 查表 LEA 段内偏移量。ESP：LEA AX，AREA1=MOV AX，OFFSET AREA1 LAHF、SAHF与棋标有关的寄存器AH PUSHF、POPF将棋标入/出栈 ADD ESP ADD AX，CX （AX=AX+CX） ADC 加入棋标C的ADD INC ESP INC AX（AX=AX+1） AAA 加法校正 SUB、SBB 减法 DEC ESP：DEC AX（AX=AX-1） NEG 去补， MUL、IMUL 乘 DIV、IDIV 除 SHR、SAR、SHL 算术、逻辑位移R=RIGHT L=LEFT OR、XOR、AND 逻辑运算ESP ：XOR AX，AX（AX=0） 直接标志转移 指令格式机器码测试条件如...则转移 JC 72 C=1 有进位 JNS 79 S=0 正号 JNC 73 C=0 无进位 JO 70 O=1 有溢出 JZ/JE 74 Z=1 零/等于 JNO 71 O=0 无溢出
(完整word版)汇编语言常用指令大全,推荐文档
MOV指令为双操作数指令,两个操作数中必须有一个是寄存器. MOV DST , SRC // Byte / Word 执行操作: dst = src 1.目的数可以是通用寄存器, 存储单元和段寄存器(但不允许用CS段寄存器). 2.立即数不能直接送段寄存器 3.不允许在两个存储单元直接传送数据 4.不允许在两个段寄存器间直接传送信息 PUSH入栈指令及POP出栈指令: 堆栈操作是以“后进先出”的方式进行数据操作. PUSH SRC //Word 入栈的操作数除不允许用立即数外，可以为通用寄存器，段寄存器(全部)和存储器. 入栈时高位字节先入栈，低位字节后入栈. POP DST //Word 出栈操作数除不允许用立即数和CS段寄存器外, 可以为通用寄存器,段寄存器和存储器. 执行POP SS指令后,堆栈区在存储区的位置要改变. 执行POP SP 指令后,栈顶的位置要改变. XCHG(eXCHanG)交换指令: 将两操作数值交换. XCHG OPR1, OPR2 //Byte/Word 执行操作: Tmp=OPR1 OPR1=OPR2 OPR2=Tmp 1.必须有一个操作数是在寄存器中 2.不能与段寄存器交换数据 3.存储器与存储器之间不能交换数据. XLAT(TRANSLATE)换码指令: 把一种代码转换为另一种代码. XLAT (OPR 可选) //Byte 执行操作: AL=(BX+AL) 指令执行时只使用预先已存入BX中的表格首地址,执行后,AL中内容则是所要转换的代码. LEA(Load Effective Address) 有效地址传送寄存器指令 LEA REG , SRC //指令把源操作数SRC的有效地址送到指定的寄存器中. 执行操作: REG = EAsrc 注: SRC只能是各种寻址方式的存储器操作数,REG只能是16位寄存器 MOV BX , OFFSET OPER_ONE 等价于LEA BX , OPER_ONE MOV SP , [BX] //将BX间接寻址的相继的二个存储单元的内容送入SP中 LEA SP , [BX] //将BX的内容作为存储器有效地址送入SP中 LDS(Load DS with pointer)指针送寄存器和DS指令 LDS REG , SRC //常指定SI寄存器。 执行操作: REG=(SRC), DS=(SRC+2) //将SRC指出的前二个存储单元的内容送入指令中指定的寄存器中，后二个存储单元送入DS段寄存器中。
51单片机汇编指令集(附记忆方法)
51单片机汇编指令集 一、数据传送类指令（7种助记符） MOV（英文为Move）：对内部数据寄存器RAM和特殊功能寄存器SFR的数据进行传送； MOVC（Move Code）读取程序存储器数据表格的数据传送； MOVX (Move External RAM) 对外部RAM的数据传送； XCH (Exchange) 字节交换； XCHD (Exchange low-order Digit) 低半字节交换； PUSH (Push onto Stack) 入栈； POP (Pop from Stack) 出栈； 二、算术运算类指令（8种助记符） ADD(Addition) 加法； ADDC(Add with Carry) 带进位加法； SUBB(Subtract with Borrow) 带借位减法； DA(Decimal Adjust) 十进制调整； INC(Increment) 加1； DEC(Decrement) 减1； MUL(Multiplication、Multiply) 乘法； DIV(Division、Divide) 除法； 三、逻辑运算类指令（10种助记符） ANL(AND Logic) 逻辑与； ORL(OR Logic) 逻辑或； XRL(Exclusive-OR Logic) 逻辑异或； CLR(Clear) 清零； CPL(Complement) 取反； RL(Rotate left) 循环左移； RLC(Rotate Left throught the Carry flag) 带进位循环左移； RR(Rotate Right) 循环右移； RRC (Rotate Right throught the Carry flag) 带进位循环右移； SWAP (Swap) 低4位与高4位交换； 四、控制转移类指令（17种助记符） ACALL（Absolute subroutine Call）子程序绝对调用； LCALL（Long subroutine Call）子程序长调用； RET（Return from subroutine）子程序返回； RETI（Return from Interruption）中断返回； SJMP（Short Jump）短转移； AJMP（Absolute Jump）绝对转移； LJMP（Long Jump）长转移； CJNE (Compare Jump if Not Equal)比较不相等则转移；
汇编语言指令表
汇编语言指令表文档编制序号：[KKIDT-LLE0828-LLETD298-POI08]
伪指令 1、定位伪指令 ORG m 2、定义字节伪指令 DB X1，X2，X3，…，Xn 3、字定义伪指令 DW Y1，Y2，Y3，…，Yn 4、汇编结束伪指令 END 寻址方式 MCS-51单片机有五种寻址方式： 1、寄存器寻址 2、寄存器间接寻址 3、直接寻址 4、立即数寻址 5、基寄存器加变址寄存器间接寻址 6、相对寻址 7、位寻址 数据传送指令 一、以累加器A为目的操作数的指令（4条） MOV A，Rn ；（Rn）→A n=0~7 MOV A，direct ；（ direct ）→A MOV A，@Ri ；（（Ri））→A i=0~1 MOV A，#data ； data →A 二、以Rn为目的操作数的指令（3条） MOV Rn ，A；（A）→ Rn MOV Rn ，direct；（ direct ）→ Rn MOV Rn ，#data； data → Rn 三、以直接寻址的单元为目的操作数的指令（5条） MOV direct，A；（A）→direct MOV direct，Rn；（Rn）→direct MOV direct，direct ；（源direct）→目的direct MOV direct，@Ri；（（Ri））→direct MOV direct，#data； data→direct 四、以寄存器间接寻址的单元为目的操作数的指令（3条） MOV @Ri，A；（A）→（Ri） MOV @Ri，direct；（direct）→（Ri） MOV @Ri，#data； data→（Ri） 五、十六位数据传送指令（1条） MOV DPTR，#data16；dataH→DPH，dataL →DPL
单片机汇编指令大全
单片机汇编指令一览表 作者：乡下人 助记符指令说明字节数周期数 （数据传递类指令） MOV A，Rn 寄存器传送到累加器 1 1 MOV A，direct 直接地址传送到累加器 2 1 MOV A，@Ri 累加器传送到外部RAM(8 地址) 1 1 MOV A，#data 立即数传送到累加器 2 1 MOV Rn，A 累加器传送到寄存器 1 1 MOV Rn，direct 直接地址传送到寄存器 2 2 MOV Rn，#data 累加器传送到直接地址 2 1 MOV direct，Rn 寄存器传送到直接地址 2 1 MOV direct，direct 直接地址传送到直接地址 3 2 MOV direct，A 累加器传送到直接地址 2 1 MOV direct，@Ri 间接RAM 传送到直接地址 2 2 MOV direct，#data 立即数传送到直接地址 3 2 MOV @Ri，A 直接地址传送到直接地址 1 2 MOV @Ri，direct 直接地址传送到间接RAM 2 1 MOV @Ri，#data 立即数传送到间接RAM 2 2 MOV DPTR，#data16 16 位常数加载到数据指针 3 1 MOVC A，@A+DPTR 代码字节传送到累加器 1 2 MOVC A，@A+PC 代码字节传送到累加器 1 2 MOVX A，@Ri 外部RAM(8 地址)传送到累加器 1 2 MOVX A，@DPTR 外部RAM(16 地址)传送到累加器 1 2 MOVX @Ri，A 累加器传送到外部RAM(8 地址) 1 2 MOVX @DPTR，A 累加器传送到外部RAM(16 地址) 1 2 PUSH direct 直接地址压入堆栈 2 2 POP direct 直接地址弹出堆栈 2 2 XCH A,Rn 寄存器和累加器交换 1 1 XCH A, direct 直接地址和累加器交换 2 1 XCH A, @Ri 间接RAM 和累加器交换 1 1 XCHD A, @Ri 间接RAM 和累加器交换低4 位字节 1 1 (算术运算类指令) INC A 累加器加1 1 1 INC Rn 寄存器加1 1 1 INC direct 直接地址加1 2 1 INC @Ri 间接RAM 加1 1 1 INC DPTR 数据指针加1 1 2 DEC A 累加器减1 1 1 DEC Rn 寄存器减1 1 1 DEC direct 直接地址减1 2 2
STM 常用汇编指令
在嵌入式开发中，汇编程序常常用于非常关键的地方，比如系统启动时初始化，进出中断时的环境保护，恢复等对性能有要求的地方。 ARM指令集可以分为六大类，分别为数据处理指令、Load/Store指令、跳转指令、程序状态寄存器处理指令、协处理器指令和异常产生指令。 ARM指令使用的基本格式如下： 〈opcode〉{〈cond〉}{S}〈Rd〉，〈Rn〉{，〈operand2〉} opcode操作码；指令助记符，如LDR、STR等。 cond可选的条件码；执行条件，如EQ、NE等。 S可选后缀；若指定“S”，则根据指令执行结果更新CPSR中的条件码。 Rd目标寄存器。 Rn存放第1操作数的寄存器。 operand2第2个操作数 arm的寻址方式如下： 立即寻址 寄存器寻址 寄存器间接寻址 基址加偏址寻址 堆栈寻址 块拷贝寻址 相对寻址 这里不作详细描述，可以查阅相关文档。 数据处理指令 Load/Store指令 程序状态寄存器与通用寄存器之间的传送指令 转移指令 异常中断指令 协处理器指令 在S3C2410、S3C2440的数据手册中对各种汇编指令有详细的描述；这里只对较常见的作写介绍。 1、相对跳转指令：b、bl 这两条指令的不同之处在于bl指令除了跳转之外，还将返回地址(bl的下一条指令的地址)保存在lr寄存器中。 这两条指令的可跳转范围是当前指令前后32M。 b funa .... funa: b funb ....
funb: .... 2、数据传送指令mov，地址读取伪指令ldr mov指令可以把一个寄存器的值赋给另外一个寄存器，或者把一个常数赋给寄存器。 mov r1,r2 mov r1,#1024 mov传送的常数必须能用立即数来表示。当不能用立即数表示时，可以用ldr命令来赋值。ldr是伪命令，不是真实存在的指令，编译器会把它扩展成真正的指令；如果该常数能用“立即数”来表示，则使用mov指令，否则编译时将该常数保存在某个位置，使用内存读取指令把它读出来。 ldr r1,=1024 3、内存访问指令ldr、str、ldm、stm ldr既可以指低至读取伪指令，也可以是内存访问指令。当他的第二个参数前面有'='时标伪指令，否则表内存访问指令。 ldr指令从内存中读取数据到寄存器，str指令把寄存器的指存储到内存中，他们的操作数都是32位的。 ldr r1,[r2,#4] ldr r1,[r2] ldr r1,[r2],#4 str r1,[r2,#4] str r1,[r2] str r1,[r2],#4 寄存器传送指令可以用一条指令将16个可见寄存器（R0~R15）的任意子集合（或全部）存储到存储器或从存储器中读取数据到该寄存器集合中。与单寄存器存取指令相比，多寄存器数据存取可用的寻址模式更加有限。多寄存器存取指令的汇编格式如下： LDM/STM{
单片机汇编语言指令集
汇编语言的所有指令数据传送指令集 MOV 功能: 把源操作数送给目的操作数 语法: MOV 目的操作数,源操作数 格式: MOV r1,r2 MOV r,m MOV m,r MOV r,data XCHG 功能: 交换两个操作数的数据 语法: XCHG 格式: XCHG r1,r2 XCHG m,r XCHG r,m PUSH,POP 功能: 把操作数压入或取出堆栈 语法: PUSH 操作数POP 操作数 格式: PUSH r PUSH M PUSH data POP r POP m PUSHF,POPF,PUSHA,POPA 功能: 堆栈指令群 格式: PUSHF POPF PUSHA POPA LEA,LDS,LES 功能: 取地址至寄存器 语法: LEA r,m LDS r,m LES r,m XLAT(XLATB) 功能: 查表指令 语法: XLAT XLAT m 算数运算指令 ADD,ADC 功能: 加法指令 语法: ADD OP1,OP2 ADC OP1,OP2 格式: ADD r1,r2 ADD r,m ADD m,r ADD r,data 影响标志: C,P,A,Z,S,O SUB,SBB 功能:减法指令 语法: SUB OP1,OP2 SBB OP1,OP2 格式: SUB r1,r2 SUB r,m SUB m,r SUB r,data SUB m,data 影响标志: C,P,A,Z,S,O
INC,DEC 功能: 把OP的值加一或减一 语法: INC OP DEC OP 格式: INC r/m DEC r/m 影响标志: P,A,Z,S,O NEG 功能: 将OP的符号反相(取二进制补码) 语法: NEG OP 格式: NEG r/m 影响标志: C,P,A,Z,S,O MUL,IMUL 功能: 乘法指令 语法: MUL OP IMUL OP 格式: MUL r/m IMUL r/m 影响标志: C,P,A,Z,S,O(仅IMUL会影响S标志) DIV,IDIV 功能:除法指令 语法: DIV OP IDIV OP 格式: DIV r/m IDIV r/m CBW,CWD 功能: 有符号数扩展指令 语法: CBW CWD AAA,AAS,AAM,AAD 功能: 非压BCD码运算调整指令 语法: AAA AAS AAM AAD 影响标志: A,C(AAA,AAS) S,Z,P(AAM,AAD) DAA,DAS 功能: 压缩BCD码调整指令 语法: DAA DAS 影响标志: C,P,A,Z,S 位运算指令集 AND,OR,XOR,NOT,TEST 功能: 执行BIT与BIT之间的逻辑运算 语法: AND r/m,r/m/data OR r/m,r/m/data XOR r/m,r/m/data TEST r/m,r/m/data NOT r/m 影响标志: C,O,P,Z,S(其中C与O两个标志会被设为0) NOT指令不影响任何标志位 SHR,SHL,SAR,SAL 功能: 移位指令 语法: SHR r/m,data/CL SHL r/m,data/CL SAR r/m,data/CL SAL r/m,data/CL
(完整word版)汇编语言指令集合-吐血整理,推荐文档
8086/8088指令系统记忆表 数据寄存器分为: AH&AL＝AX(accumulator)：累加寄存器，常用于运算;在乘除等指令中指定用来存放操作数,另外,所有的I/O指令都使用这一寄存器与外界设备传送数据. BH&BL＝BX(base)：基址寄存器，常用于地址索引； CH&CL＝CX(count)：计数寄存器，常用于计数；常用于保存计算值,如在移位指令,循环(loop)和串处理指令中用作隐含的计数器. DH&DL＝DX(data)：数据寄存器，常用于数据传递。他们的特点是,这4个16位的寄存器可以分为高8位: AH, BH, CH, DH.以及低八位：AL,BL,CL,DL。这2组8位寄存器可以分别寻址，并单独使用。 另一组是指针寄存器和变址寄存器，包括： SP（Stack Pointer）：堆栈指针，与SS配合使用，可指向目前的堆栈位置； BP（Base Pointer）：基址指针寄存器，可用作SS的一个相对基址位置； SI（Source Index）：源变址寄存器可用来存放相对于DS段之源变址指针； DI（Destination Index）：目的变址寄存器，可用来存放相对于ES 段之目的变址指针。 指令指针IP(Instruction Pointer) 标志寄存器FR(Flag Register) OF(overflow flag) DF(direction flag) CF(carrier flag) PF(parity flag) AF(auxiliary flag) ZF(zero flag) SF(sign flag) IF(interrupt flag) TF(trap flag) 段寄存器(Segment Register) 为了运用所有的内存空间，8086设定了四个段寄存器，专门用来保存段地址： CS（Code Segment）：代码段寄存器； DS（Data Segment）：数据段寄存器； SS（Stack Segment）：堆栈段寄存器；
汇编语言指令
汇编语言指令集 数据传送指令集 MOV 功能: 把源操作数送给目的操作数 语法: MOV 目的操作数,源操作数 格式: MOV r1,r2 MOV r,m MOV m,r MOV r,data XCHG 功能: 交换两个操作数的数据 语法: XCHG 格式: XCHG r1,r2 XCHG m,r XCHG r,m PUSH,POP 功能: 把操作数压入或取出堆栈 语法: PUSH 操作数POP 操作数 格式: PUSH r PUSH M PUSH data POP r POP m PUSHF,POPF,PUSHA,POPA 功能: 堆栈指令群 格式: PUSHF POPF PUSHA POPA LEA,LDS,LES 功能: 取地址至寄存器 语法: LEA r,m LDS r,m LES r,m XLAT(XLATB) 功能: 查表指令 语法: XLAT XLAT m 算数运算指令 ADD,ADC 功能: 加法指令 语法: ADD OP1,OP2 ADC OP1,OP2 格式: ADD r1,r2 ADD r,m ADD m,r ADD r,data 影响标志: C,P,A,Z,S,O SUB,SBB 功能:减法指令 语法: SUB OP1,OP2 SBB OP1,OP2
格式: SUB r1,r2 SUB r,m SUB m,r SUB r,data SUB m,data 影响标志: C,P,A,Z,S,O INC,DEC 功能: 把OP的值加一或减一 语法: INC OP DEC OP 格式: INC r/m DEC r/m 影响标志: P,A,Z,S,O NEG 功能: 将OP的符号反相(取二进制补码) 语法: NEG OP 格式: NEG r/m 影响标志: C,P,A,Z,S,O MUL,IMUL 功能: 乘法指令 语法: MUL OP IMUL OP 格式: MUL r/m IMUL r/m 影响标志: C,P,A,Z,S,O(仅IMUL会影响S标志) DIV,IDIV 功能:除法指令 语法: DIV OP IDIV OP 格式: DIV r/m IDIV r/m CBW,CWD 功能: 有符号数扩展指令 语法: CBW CWD AAA,AAS,AAM,AAD 功能: 非压BCD码运算调整指令 语法: AAA AAS AAM AAD 影响标志: A,C(AAA,AAS) S,Z,P(AAM,AAD) DAA,DAS 功能: 压缩BCD码调整指令 语法: DAA DAS 影响标志: C,P,A,Z,S 位运算指令集 AND,OR,XOR,NOT,TEST 功能: 执行BIT与BIT之间的逻辑运算 语法: AND r/m,r/m/data OR r/m,r/m/data XOR r/m,r/m/data TEST r/m,r/m/data NOT r/m 影响标志: C,O,P,Z,S(其中C与O两个标志会被设为0) NOT指令不影响任何标志位SHR,SHL,SAR,SAL 功能: 移位指令 语法: SHR r/m,data/CL SHL r/m,data/CL SAR r/m,data/CL SAL r/m,data/CL 影响标志: C,P,Z,S,O ROR,ROL,RCR,RCL
51单片机指令表汇总
51单片机指令表 助记符指令说明字节数周期数 （数据传递类指令） MOV A，Rn 寄存器内容传送到累加器 1 1 MOV A，direct 直接地址内容传送到累加器 2 1 MOV A，@Ri 间接RAM内容传送到累加器 1 1 MOV A，#data 立即数传送到累加器 2 1 MOV Rn，A 累加器内容传送到寄存器 1 1 MOV Rn，direct 直接地址内容传送到寄存器 2 2 MOV Rn，#data 立即数传送到寄存器 2 1 MOV direct，Rn 寄存器内容传送到直接地址 2 2 MOV direct，direct 直接地址传内容传送到直接地址 3 2 MOV direct，A 累加器内容传送到直接地址 2 1 MOV direct，@Ri 间接RAM内容传送到直接地址 2 2 MOV direct，#data 立即数传送到直接地址 3 2 MOV @Ri，A 累加器内容传送到间接RAM 1 1 MOV @Ri，direct 直接地址内容传送到间接RAM 2 2 MOV @Ri，#data 立即数传送到间接RAM 2 1 MOV DPTR，#data16 16 位地址传送到数据指针 3 2 MOVC A，@A+DPTR 代码字节传送到累加器 1 2 MOVC A，@A+PC 代码字节传送到累加器 1 2 MOVX A，@Ri 外部RAM(8位地址)内容传送到累加器 1 2 MOVX A，@DPTR 外部RAM(16位地址)内容传送到累加器 1 2 MOVX @Ri，A 累加器内容传送到外部RAM(8位地址) 1 2 MOVX @DPTR，A 累加器内容传送到外部RAM(16 地址) 1 2 PUSH direct 直接地址内容压入堆栈 2 2 POP direct 堆栈内容弹出到直接地址 2 2 XCH A,Rn 寄存器和累加器交换 1 1 XCH A, direct 直接地址和累加器交换 2 1
PIC16系列_单片机常用伪指令(汇编)
PIC 单片机端口电平变化中断使用必须注意的问题 PICC18使用说明 PIC 单片机常用伪指令 PIC单片机2009-02-19 11:16:40 阅读8 评论0 字号：大中小订阅 3.2.3 MPASM 的伪指令 我们在第一章中已经详细介绍了中档PIC 单片机的35 条指令，源程序的编写主要就是用这些基本的指令实现你的控制任务。但为了增加源程序的可读性和可维护性，我们引入了伪指令的概念。伪指令本身不会产生可执行的汇编指令，但它们可以帮组“管理”你编写的程序，其实用性和必要性绝不亚于35 条正真的汇编指令。我们在此着重介绍最常用的几种 伪指令。 #include 或include #include 伪指令的作用是把另外一个文件的内容全部包含复制到本伪指令所在的位置。 被包含复制的文件可以是任何形式的文本文件，当然文件中的内容和语法结构必须是MPASM 能够识别的。最经常被“include”的是针对PIC 单片机内部特殊功能寄存器定义的包含头文件，在MPLAB 安装后它们全部放在路径“ C:\Program Files\MPLAB IDE\MCHIP_Tools”下，每一个型号的PIC 单片机都有一个对应的预定义包含头文件，扩展名是“.inc”。除了一些符号预定义文件，你也可以把现有的其它程序文件作为一个代码模块直接“包含”进来作为自己程序的一部分。见例3-01。 #include
(完整版)51单片机汇编指令(全)
指令中常用符号说明 Rn当前寄存器区的8个工作寄存器R0~R7（n=0~7） Ri当前寄存器区可作为地址寄存器的2个工作寄存器R0和R1（i=0,1） Direct8位内部数据寄存器单元的地址及特殊功能寄存器的地址 #data表示8位常数（立即数） #data16表示16位常数 Add16表示16位地址 Addr11表示11位地址 Rel8位代符号的地址偏移量 Bit表示位地址 @间接寻址寄存器或基址寄存器的前缀 ( )表示括号中单元的内容 (( ))表示间接寻址的内容 指令系统 数据传送指令（8个助记符） 助记符中英文注释 MOV Move 移动 MOV A , Rn;Rn→A，寄存器Rn的内容送到累加器A MOV A , Direct;（direct）→A，直接地址的内容送A MOV A ,@ Ri;（Ri）→A，RI间址的内容送A MOV A , #data;data→A，立即数送A MOV Rn , A;A→Rn，累加器A的内容送寄存器Rn MOV Rn ,direct;（direct）→Rn，直接地址中的内容送Rn MOV Rn , #data;data→Rn，立即数送Rn MOV direct , A;A→（direct），累加器A中的内容送直接地址中 MOV direct , Rn;(Rn)→direct，寄存器的内容送到直接地址 MOV direct , direct;(direct)→direct，直接地址的内容送到直接地址 MOV direct , @Ri;（（Ri））→direct，间址的内容送到直接地址 MOV direct , #data;8位立即数送到直接地址中 MOV @Ri , A;(A)→@Ri，累加器的内容送到间址中 MOV @Ri , direct;direct→@Ri，直接地址中的内容送到间址中 MOV @Ri , #data; data→@Ri ，8位立即数送到间址中 MOV DPTR , #data16;data16→DPTR,16位常数送入数据指针寄存器，高8位送入DPH，低8位送入DPL中（单片机中唯一一条16位数据传送指令） （MOV类指令共16条）
微机原理与接口技术汇编语言指令详解吐血版
第一讲 第三章 指令系统--寻址方式 回顾: 8086/8088的内部结构和寄存器，地址分段的概念，8086/8088的工作过 程。 重点和纲要：指令系统--寻址方式。有关寻址的概念；6种基本的寻址方式及 有效地址的计算。 教学方法、实施步骤 时间分配 教学手段 回 顾 5”×2 板书 计算机 投影仪 多媒体课件等 讲 授 40” ×2 提 问 3” ×2 小 结 2” ×2 讲授内容： 3.1 8086/8088寻址方式 首先，简单讲述一下指令的一般格式： 操作码 操作数 …… 操作数 计算机中的指令由操作码字段和操作数字段组成。 操作码：指计算机所要执行的操作，或称为指出操作类型，是一种助记符。 操作数：指在指令执行操作的过程中所需要的操作数。该字段除可以是操作数本身外，也可以是操作数地址或是地址的一部分，还可以是指向操作数地址的指针或其它有关操作数的信息。 寻址方式就是指令中用于说明操作数所在地址的方法，或者说是寻找操作数有效地址的方法。8086／8088的基本寻址方式有六种。 1．立即寻址 所提供的操作数直接包含在指令中。它紧跟在操作码的后面，与操作码一起放在代码段区域中。如图所示。 例如：MOV AX ，3000H
立即数可以是8位的，也可以是16位的。若是16位的，则存储时低位在前，高位在后。 立即寻址主要用来给寄存器或存储器赋初值。 2．直接寻址 操作数地址的16位偏移量直接包含在指令中。它与操作码—起存放在代码段区域，操作数一般在数据段区域中，它的地址为数据段寄存器DS加上这16位地址偏移量。如图2-2所示。 例如： MOV AX，DS：[2000H]； 图2－2 （对DS来讲可以省略成 MOV AX，[2000H]，系统默认为数据段）这种寻址方法是以数据段的地址为基础，可在多达64KB的范围内寻找操作数。 8086/8088中允许段超越，即还允许操作数在以代码段、堆栈段或附加段为基准的区域中。此时只要在指令中指明是段超越的，则16位地址偏移量可以与CS或SS或ES相加，作为操作数的地址。 MOV AX，[2000H] ；数据段 MOV BX，ES：[3000H] ；段超越，操作数在附加段 即绝对地址＝（ES）＊16＋3000H 3．寄存器寻址 操作数包含在CPU的内部寄存器中，如寄存器AX、BX、CX、DX等。 例如：MOV DS，AX MOV AL，BH 4．寄存器间接寻址 操作数是在存储器中，但是，操作数地址的16位偏移量包含在以下四个寄
汇编语言手册
寄存器与存储器 1. 寄存器功能 . 寄存器的一般用途和专用用途 . CS:IP 控制程序执行流程 . SS:SP 提供堆栈栈顶单元地址 . DS:BX(SI,DI) 提供数据段内单元地址 . SS:BP 提供堆栈内单元地址 . ES:BX(SI,DI) 提供附加段内单元地址 . AX,CX,BX和CX寄存器多用于运算和暂存中间计算结果,但又专用于某些指令(查阅指令表)。. PSW程序状态字寄存器只能通过专用指令（LAHF, SAHF)和堆栈(PUSHF,POPF)进行存取。 2. 存储器分段管理 . 解决了16位寄存器构成20位地址的问题 . 便于程序重定位 . 20位物理地址=段地址* 16 + 偏移地址 . 程序分段组织: 一般由代码段,堆栈段,数据段和附加段组成,不设置堆栈段时则使用系统内部的堆栈。 3. 堆栈 . 堆栈是一种先进后出的数据结构, 数据的存取在栈顶进行, 数据入栈使堆栈向地址减小的方向扩展。 . 堆栈常用于保存子程序调用和中断响应时的断点以及暂存数据或中间计算结果。 .堆栈总是以字为单位存取 指令系统与寻址方式 1. 指令系统 . 计算机提供给用户使用的机器指令集称为指令系统,大多数指令为双操作数指令。执行指令后,一般源操作数不变,目的操作数被计算结果替代。 . 机器指令由CPU执行,完成某种运算或操作,8086/8088指令系统中的指令分为6类: 数据传送,算术运算,逻辑运算,串操作,控制转移和处理机控制。 2. 寻址方式 . 寻址方式确定执行指令时获得操作数地址的方法 . 分为与数据有关的寻址方式(7种)和与转移地址有关的寻址方式(4)种。 . 与数据有关的寻址方式的一般用途: (1) 立即数寻址方式--将常量赋给寄存器或存储单元 (2) 直接寻址方式--存取单个变量 (3) 寄存器寻址方式--访问寄存器的速度快于访问存储单元的速度 (4) 寄存器间接寻址方式--访问数组元素 (5) 变址寻址方式 (6) 基址变址寻址方式 (7) 相对基址变址寻址方式(5),(6),(7)都便于处理数组元素 . 与数据有关的寻址方式中,提供地址的寄存器只能是BX,SI,DI或BP . 与转移地址有关的寻址方式的一般用途: (1) 段内直接寻址--段内直接转移或子程序调用 (2) 段内间接寻址--段内间接转移或子程序调用
8088 汇编语言指令以及伪指令速查手册
数据传输指令 ───────────────────────────────────────它们在存贮器和寄存器、寄存器和输入输出端口之间传送数据. 1. 通用数据传送指令. MOV 传送字或字节. MOVSX 先符号扩展,再传送. MOVZX 先零扩展,再传送. PUSH 把字压入堆栈. POP 把字弹出堆栈. PUSHA 把AX,CX,DX,BX,SP,BP,SI,DI依次压入堆栈. POPA 把DI,SI,BP,SP,BX,DX,CX,AX依次弹出堆栈. PUSHAD 把EAX,ECX,EDX,EBX,ESP,EBP,ESI,EDI依次压入堆栈. POPAD 把EDI,ESI,EBP,ESP,EBX,EDX,ECX,EAX依次弹出堆栈. BSWAP 交换32位寄存器里字节的顺序 XCHG 交换字或字节.( 至少有一个操作数为寄存器,段寄存器不可作为操作数) CMPXCHG 比较并交换操作数.( 第二个操作数必须为累加器AL/AX/EAX ) XADD 先交换再累加.( 结果在第一个操作数里 ) XLAT 字节查表转换. ── BX 指向一张 256 字节的表的起点, AL 为表的索引值 (0-255,即 0-FFH); 返回 AL 为查表结果. ( [BX+AL]->AL ) 2. 输入输出端口传送指令. IN I/O端口输入. ( 语法: IN 累加器, {端口号│DX} ) OUT I/O端口输出. ( 语法: OUT {端口号│DX},累加器 ) 输入输出端口由立即方式指定时, 其范围是 0-255; 由寄存器 DX 指定时, 其范围是 0-65535. 3. 目的地址传送指令. LEA 装入有效地址. 例: LEA DX,string ;把偏移地址存到DX. LDS 传送目标指针,把指针内容装入DS. 例: LDS SI,string ;把段地址:偏移地址存到DS:SI. LES 传送目标指针,把指针内容装入ES. 例: LES DI,string ;把段地址:偏移地址存到ES:DI. LFS 传送目标指针,把指针内容装入FS. 例: LFS DI,string ;把段地址:偏移地址存到FS:DI. LGS 传送目标指针,把指针内容装入GS. 例: LGS DI,string ;把段地址:偏移地址存到GS:DI. LSS 传送目标指针,把指针内容装入SS. 例: LSS DI,string ;把段地址:偏移地址存到SS:DI. 4. 标志传送指令. LAHF 标志寄存器传送,把标志装入AH. SAHF 标志寄存器传送,把AH内容装入标志寄存器. PUSHF 标志入栈. POPF 标志出栈. PUSHD 32位标志入栈.
汇编指令
?应用 注册 用户名密码 ?HOHO ?照片PK ?分享 ?投票 ?测试 ?礼物 ?开心部落 ?汽车工厂 ?七彩鱼 更多?网页游戏 分享 ?热门分享 ?最新分享 ?好友的分享 ?我的分享 如何分享?问题反馈 shxc_3的分享 分享 PIC常用汇编指令 PIC常用汇编指令 常用指令 1．寄存器加1指令：INCF 【格式】INCF F，d 【功能】寄存器F加1
【说明】 （1）INCF是Increment F的缩写； （2）在PIC系列8位单片机中，常用符号F代表片内的各种寄存器和F的序号地址；（3）d＝0时，结果存入W；d＝1时，结果存入F。 【实例】INCF PORTC，1 ；将PORTC加1 2．寄存器减1指令：DECF 【格式】DECF F，d 【功能】寄存器F减1 【说明】 （1）DECF是Decrement F的缩写； （2）d＝0时，结果存入W；d＝1时，结果存入F。 【实例】ENCODER EQU 0X21 …… DECF ENCODER，1 ；将ENCODER减1 3．寄存器清零指令：CLRF 【格式】CLRF F 【功能】寄存器清零 【说明】 （1）CLRF是Clear F的缩写； （2）F寄存器被清为全0，使状态位Z＝1。 【实例】CLRF TRISC ；对TRISC 清零 4．W清零指令：CLRW 【格式】CLRW
【功能】寄存器W清零 【说明】 （1）CLRW是Clear W的缩写； （2）W为PIC单片机的工作寄存器； （3）W寄存器被清为全0，使状态位Z＝1。 【实例】CLRW ；W＝00H 5．F寄存器传送指令：MOVF 【格式】MOVF F，d 【功能】将F寄存器内容传送到F或W 【说明】 （1）MOVF是Move F的缩写； （2）当d＝1时，传到F本身；当d＝0时，传到W； （3）影响状态位Z 【实例】MOVF PORTB，0 ；PORTB口内容送W MOVWF PORTA；W内容即PORTB口内容送PORTA 6．W寄存器传送指令：MOVWF 【格式】MOVWF F 【功能】W寄存器传送 【说明】 （1）MOVWF是Move W to F的缩写； （2）将W寄存器内容传到F，W内容不变； （3）不影响状态位。
常用51单片机汇编指令
常用单片机汇编指令： 1 .MOV A,Rn寄存器内容送入累加器 2 .MOV A,direct 直接地址单元中的数据送入累加器 3 .MOV A,@Ri (i=0,1) 间接RAM中的数据送入累加器 4 .MOV A,#data 立即数送入累加器 5 .MOV Rn,A累加器内容送入寄存器 6 .MOV Rn,direct 直接地址单元中的数据送入寄存器 7 .MOV Rn,#data 立即数送入寄存器 8 .MOV direct,A 累加器内容送入直接地址单元 9 .MOV direct,Rn 寄存器内容送入直接地址单元 10. MOV direct,direct 直接地址单元中的数据送入另一个 直接地址单元 11 .MOV direct,@Ri (i=0,1) 间接RAM中的数据送入直接地址单元 12 MOV direct,#data 立即数送入直接地址单元 13 .MOV @Ri,A (i=0,1) 累加器内容送间接RAM单元 14 .MOV@Ri,direct (i=0,1)直接地址单元数据送入间接RAM 单元 15 .MOV @Ri,#data (i=0,1) 立即数送入间接RAM单元 16 .MOV DPTR,#data16 16 位立即数送入地址寄存器 17 .MOVC A,@A+DPTR以DPTR^基地址变址寻址单元中的数 据送入累加器
18 .MOVC A,@A+PC以PC为基地址变址寻址单元中的数据送入累加器 19 .MOVX A,@Ri (i=0,1) 外部RAM(8位地址)送入累加器 20 .MOVX A,@DPTR外部RAM(16位地址)送入累加器 21 .MOVX @Ri,A (i=0,1) 累计器送外部RAM(8位地址) 22 .MOVX @DPTR,A累计器送外部RAM( 16位地址) 23 .PUSH direct 直接地址单元中的数据压入堆栈 24 .POP direct 弹栈送直接地址单元 25 .XCH A,Rn 寄存器与累加器交换 26 .XCH A,direct 直接地址单元与累加器交换 27 .XCH A,@Ri (i=0,1) 间接RAM与累加器交换 28 .XCHD A,@Ri (i=0,1) 间接RAM的低半字节与累加器交换算术操作类指令： 1. ADD A,Rn 寄存器内容加到累加器 2 .ADD A,direct 直接地址单元的内容加到累加器 3 A.DD A,@Ri (i=0,1) 间接ROM的内容加到累加器 4 .ADD A,#data 立即数加到累加器 5 .ADDC A,Rn寄存器内容带进位加到累加器 6 .ADDC A,direct 直接地址单元的内容带进位加到累加器 7 .ADDC A,@Ri(i=0,1) 间接ROM的内容带进位加到累加器 8 .ADDC A,#data 立即数带进位加到累加器